Build for ARMv4T

Modify a few files in the system to use the macros introduced in
<machine/cpu-features.h> in order to build for ARMv4T.

1 files changed, 52 insertions, 0 deletions

diff --git a/libcutils/atomic-android-arm.S b/libcutils/atomic-android-arm.S
index 2a4c34f0..c56ec5d0 100644
--- a/libcutils/atomic-android-arm.S
+++ b/libcutils/atomic-android-arm.S
@@ -14,6 +14,8 @@
  * limitations under the License.
  */
 
+#include <machine/cpu-features.h>
+
 /*
  * NOTE: these atomic operations are SMP safe on all architectures, 
  * except swap(), see below.
@@ -59,8 +61,14 @@ android_atomic_write:
 1: @ android_atomic_write
     ldr     r0, [r2]
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #4
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
+#else
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
+    mov     lr, pc
+    bx      r3
+#endif
     bcc     1b
     ldmia   sp!, {r4, lr}
     bx      lr
@@ -78,9 +86,16 @@ android_atomic_inc:
 1: @ android_atomic_inc
     ldr     r0, [r2]
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #4
     add     r1, r0, #1
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
+#else
+    add     r1, r0, #1
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
+    mov     lr, pc
+    bx      r3
+#endif
     bcc     1b
     sub     r0, r1, #1
     ldmia   sp!, {r4, lr}
@@ -99,9 +114,16 @@ android_atomic_dec:
 1: @ android_atomic_dec
     ldr     r0, [r2]
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #4
     sub     r1, r0, #1
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
+#else
+    sub     r1, r0, #1
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
+    mov     lr, pc
+    bx      r3
+#endif
     bcc     1b
     add     r0, r1, #1
     ldmia   sp!, {r4, lr}
@@ -121,9 +143,16 @@ android_atomic_add:
 1: @ android_atomic_add
     ldr     r0, [r2]
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #4
     add     r1, r0, r4
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
+#else
+    add     r1, r0, r4
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
+    mov     lr, pc
+    bx      r3
+#endif
     bcc     1b
     sub     r0, r1, r4
     ldmia   sp!, {r4, lr}
@@ -144,10 +173,18 @@ android_atomic_and:
 1: @ android_atomic_and
     ldr     r0, [r2]            /* r0 = address[0] */
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #8
     mov     r5, r0              /* r5 = save address[0] */
     and     r1, r0, r4          /* r1 = new value */
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)  /* call cmpxchg() */
+#else
+    mov     r5, r0              /* r5 = save address[0] */
+    and     r1, r0, r4          /* r1 = new value */
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)  /* call cmpxchg() */
+    mov     lr, pc
+    bx      r3
+#endif
     bcc     1b
     mov     r0, r5
     ldmia   sp!, {r4, r5, lr}
@@ -167,10 +204,18 @@ android_atomic_or:
 1: @ android_atomic_or
     ldr     r0, [r2]            /* r0 = address[0] */
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #8
     mov     r5, r0              /* r5 = save address[0] */
     orr     r1, r0, r4          /* r1 = new value */
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)  /* call cmpxchg() */
+#else
+    mov     r5, r0              /* r5 = save address[0] */
+    orr     r1, r0, r4          /* r1 = new value */
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)  /* call cmpxchg() */
+    mov     lr, pc
+    bx      r3
+#endif
     bcc     1b
     mov     r0, r5
     ldmia   sp!, {r4, r5, lr}
@@ -202,9 +247,16 @@ android_atomic_cmpxchg:
     mov     r4, r0          /* r4 = save oldvalue */
 1: @ android_atomic_cmpxchg
     mov     r3, #kernel_atomic_base
+#ifdef __ARM_HAVE_PC_INTERWORK
     add     lr, pc, #4
     mov     r0, r4          /* r0 = oldvalue */
     add     pc, r3, #(kernel_cmpxchg - kernel_atomic_base)
+#else
+    mov     r0, r4          /* r0 = oldvalue */
+    add     r3, r3, #(kernel_cmpxchg - kernel_atomic_base)
+    mov     lr, pc
+    bx      r3
+#endif
     bcs     2f              /* swap was made. we're good, return. */
     ldr     r3, [r2]        /* swap not made, see if it's because *ptr!=oldvalue */
     cmp     r3, r4