gralloc: UBWC aligned buffers are Macro Tiled

All UBWC aligned buffers are Macro tiled.

Change-Id: I71bb0269d337d1ca2017ce9665010f738674f1a8

1 files changed, 6 insertions, 4 deletions

diff --git a/libgralloc/alloc_controller.cpp b/libgralloc/alloc_controller.cpp
index e37cdddf7..f43f64505 100644
--- a/libgralloc/alloc_controller.cpp
+++ b/libgralloc/alloc_controller.cpp
@@ -153,15 +153,17 @@ void AdrenoMemInfo::getAlignedWidthAndHeight(int width, int height, int format,
                             int usage, int& aligned_w, int& aligned_h)
 {
 
+    bool ubwc_enabled = isUBwcEnabled(format, usage);
+
     // Currently surface padding is only computed for RGB* surfaces.
     if (format <= HAL_PIXEL_FORMAT_sRGB_X_8888) {
-        int tileEnabled = isMacroTileEnabled(format, usage);
+        int tileEnabled = ubwc_enabled || isMacroTileEnabled(format, usage);
         AdrenoMemInfo::getInstance().getGpuAlignedWidthHeight(width,
             height, format, tileEnabled, aligned_w, aligned_h);
         return;
     }
 
-    if (isUBwcEnabled(format, usage)) {
+    if (ubwc_enabled) {
         getUBwcWidthAndHeight(width, height, format, aligned_w, aligned_h);
         return;
     }
@@ -620,9 +622,9 @@ unsigned int getBufferSizeAndDimensions(int width, int height, int format,
 
 
 void getBufferAttributes(int width, int height, int format, int usage,
-        int& alignedw, int &alignedh, int& tileEnabled, unsigned int& size)
+        int& alignedw, int &alignedh, int& tiled, unsigned int& size)
 {
-    tileEnabled = isMacroTileEnabled(format, usage);
+    tiled = isUBwcEnabled(format, usage) || isMacroTileEnabled(format, usage);
 
     AdrenoMemInfo::getInstance().getAlignedWidthAndHeight(width,
             height,