halimpl: NCI 2.0 init support added.

Bug: 63146248
Test: manual; NCI2.0 init works; Switching b/w NCI1.0 and NCI2.0 works.
Change-Id: I13a50b216aa6f3287e31a00eb910e88915582c73
(cherry picked from commit 6c57a73e2934df21a36b43db696a4812dab42ec9)

8 files changed, 1549 insertions, 44 deletions

diff --git a/halimpl/pn54x/dnld/phDnldNfc.c b/halimpl/pn54x/dnld/phDnldNfc.c
index 6feb644..0848d0b 100644
--- a/halimpl/pn54x/dnld/phDnldNfc.c
+++ b/halimpl/pn54x/dnld/phDnldNfc.c
@@ -1046,6 +1046,8 @@ NFCSTATUS phDnldNfc_LoadRecoveryFW(const char* pathName, uint8_t** pImgInfo,
     pathName = "/system/vendor/firmware/libpn548ad_fw.so";
 #elif (NFC_NXP_CHIP_TYPE == PN551)
     pathName = "/system/vendor/firmware/libpn551_fw.so";
+#elif (NFC_NXP_CHIP_TYPE == PN553)
+    pathName = "/system/vendor/firmware/libpn553_fw.so";
 #else
     pathName = "/system/vendor/firmware/libpn547_fw.so";
 #endif
diff --git a/halimpl/pn54x/dnld/phNxpNciHal_Dnld.c b/halimpl/pn54x/dnld/phNxpNciHal_Dnld.c
index d50d47f..42cadba 100644
--- a/halimpl/pn54x/dnld/phNxpNciHal_Dnld.c
+++ b/halimpl/pn54x/dnld/phNxpNciHal_Dnld.c
@@ -553,6 +553,11 @@ static void phNxpNciHal_fw_dnld_get_version_cb(void* pContext, NFCSTATUS status,
               ) {
         bExpectedLen = PHLIBNFC_IOCTL_DNLD_GETVERLEN_MRA2_1;
         (gphNxpNciHal_fw_IoctlCtx.bChipVer) = bHwVer;
+#if (NFC_NXP_CHIP_TYPE == PN553)
+        if (PHDNLDNFC_HWVER_PN553_MRA1_0_UPDATED & pRespBuff->pBuff[0]) {
+          (gphNxpNciHal_fw_IoctlCtx.bChipVer) = pRespBuff->pBuff[0];
+        }
+#endif
       } else if ((bHwVer >= PHDNLDNFC_HWVER_MRA1_0) &&
                  (bHwVer <= PHDNLDNFC_HWVER_MRA2_0)) {
         bExpectedLen = PHLIBNFC_IOCTL_DNLD_GETVERLEN;
@@ -1745,7 +1750,7 @@ NFCSTATUS phNxpNciHal_fw_download_seq(uint8_t bClkSrcVal, uint8_t bClkFreqVal) {
 }
 
 static NFCSTATUS phLibNfc_VerifyCrcStatus(uint8_t bCrcStatus) {
-#if (NFC_NXP_CHIP_TYPE == PN551)
+#if ((NFC_NXP_CHIP_TYPE == PN551) || (NFC_NXP_CHIP_TYPE == PN553))
   uint8_t bBitPos = 1;
   uint8_t bShiftVal = 2;
 #else
diff --git a/halimpl/pn54x/hal/phNxpNciHal.c b/halimpl/pn54x/hal/phNxpNciHal.c
index 3c5e07f..c24c04c 100644
--- a/halimpl/pn54x/hal/phNxpNciHal.c
+++ b/halimpl/pn54x/hal/phNxpNciHal.c
@@ -428,7 +428,8 @@ int phNxpNciHal_open(nfc_stack_callback_t* p_cback,
   static uint8_t cmd_init_nci[] = {0x20, 0x01, 0x00};
   /*NCI_RESET_CMD*/
   static uint8_t cmd_reset_nci[] = {0x20, 0x00, 0x01, 0x00};
-
+  /*NCI2_0_INIT_CMD*/
+  static uint8_t cmd_init_nci2_0[] = {0x20, 0x01, 0x02, 0x00, 0x00};
   if (nxpncihal_ctrl.halStatus == HAL_STATUS_OPEN) {
     NXPLOG_NCIHAL_E("phNxpNciHal_open already open");
     return NFCSTATUS_SUCCESS;
@@ -461,7 +462,8 @@ int phNxpNciHal_open(nfc_stack_callback_t* p_cback,
 
   nxpncihal_ctrl.p_nfc_stack_cback = p_cback;
   nxpncihal_ctrl.p_nfc_stack_data_cback = p_data_cback;
-
+  /*nci version NCI_VERSION_UNKNOWN version by default*/
+  nxpncihal_ctrl.nci_info.nci_version = NCI_VERSION_UNKNOWN;
   /* Read the nfc device node name */
   nfc_dev_node = (char*)malloc(max_len * sizeof(char));
   if (nfc_dev_node == NULL) {
@@ -549,7 +551,21 @@ init_retry:
     goto clean_and_return;
   }
 
-  status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+  status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci2_0), cmd_init_nci2_0);
+  if (status == NFCSTATUS_SUCCESS) {
+    if (nxpncihal_ctrl.nci_info.nci_version != NCI_VERSION_2_0) {
+      NXPLOG_NCIHAL_E("Chip is in NCI1.0 mode reset the chip again");
+      status = phNxpNciHal_send_ext_cmd(sizeof(cmd_reset_nci), cmd_reset_nci);
+      if (status == NFCSTATUS_SUCCESS) {
+        if (nxpncihal_ctrl.nci_info.nci_version == NCI_VERSION_2_0) {
+          status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci2_0),
+                                            cmd_init_nci2_0);
+        } else {
+          status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+        }
+      }
+    }
+  }
   if (status != NFCSTATUS_SUCCESS) {
     NXPLOG_NCIHAL_E("NCI_CORE_INIT : Failed");
     if (init_retry_cnt < 3) {
@@ -907,18 +923,25 @@ static void phNxpNciHal_read_complete(void* pContext,
     phNxpNciHal_print_res_status(nxpncihal_ctrl.p_rx_data,
                                  &nxpncihal_ctrl.rx_data_len);
     /* Check if response should go to hal module only */
-    if (nxpncihal_ctrl.hal_ext_enabled == 1 &&
-        (nxpncihal_ctrl.p_rx_data[0x00] & 0xF0) == 0x40) {
+    if (nxpncihal_ctrl.hal_ext_enabled == TRUE &&
+        (nxpncihal_ctrl.p_rx_data[0x00] & NCI_MT_MASK) == NCI_MT_RSP) {
       if (status == NFCSTATUS_FAILED) {
         NXPLOG_NCIHAL_D("enter into NFCC init recovery");
         nxpncihal_ctrl.ext_cb_data.status = status;
       }
       /* Unlock semaphore only for responses*/
-      if ((nxpncihal_ctrl.p_rx_data[0x00] & 0xF0) == 0x40 ||
+      if ((nxpncihal_ctrl.p_rx_data[0x00] & NCI_MT_MASK) == NCI_MT_RSP ||
           ((icode_detected == true) && (icode_send_eof == 3))) {
         /* Unlock semaphore */
         SEM_POST(&(nxpncihal_ctrl.ext_cb_data));
       }
+    }  // Notification Checking
+    else if ((nxpncihal_ctrl.hal_ext_enabled == TRUE) &&
+             ((nxpncihal_ctrl.p_rx_data[0x00] & NCI_MT_MASK) == NCI_MT_NTF) &&
+             (nxpncihal_ctrl.nci_info.wait_for_ntf == TRUE)) {
+      /* Unlock semaphore waiting for only  ntf*/
+      SEM_POST(&(nxpncihal_ctrl.ext_cb_data));
+      nxpncihal_ctrl.nci_info.wait_for_ntf = FALSE;
     }
     /* Read successful send the event to higher layer */
     else if ((nxpncihal_ctrl.p_nfc_stack_data_cback != NULL) &&
@@ -930,7 +953,9 @@ static void phNxpNciHal_read_complete(void* pContext,
     NXPLOG_NCIHAL_E("read error status = 0x%x", pInfo->wStatus);
   }
 
-  if (nxpncihal_ctrl.halStatus == HAL_STATUS_CLOSE) {
+  if (nxpncihal_ctrl.halStatus == HAL_STATUS_CLOSE &&
+      nxpncihal_ctrl.nci_info.wait_for_ntf == FALSE) {
+    NXPLOG_NCIHAL_E(" Ignoring read , HAL close triggered");
     return;
   }
   /* Read again because read must be pending always.*/
@@ -997,6 +1022,7 @@ int phNxpNciHal_core_initialized(uint8_t* p_core_init_rsp_params) {
   /*NCI_RESET_CMD*/
   static uint8_t cmd_reset_nci[] = {0x20, 0x00, 0x01,
                                     0x00};  // keep configuration
+  static uint8_t cmd_init_nci2_0[] = {0x20, 0x01, 0x02, 0x00, 0x00};
   /* reset config cache */
   static uint8_t retry_core_init_cnt;
   if (nxpncihal_ctrl.halStatus != HAL_STATUS_OPEN) {
@@ -1038,8 +1064,12 @@ int phNxpNciHal_core_initialized(uint8_t* p_core_init_rsp_params) {
       NXPLOG_NCIHAL_E(" Last command is CORE_RESET!!");
       goto invoke_callback;
     }
-
-    status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+    if (nxpncihal_ctrl.nci_info.nci_version == NCI_VERSION_2_0) {
+      status =
+          phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci2_0), cmd_init_nci2_0);
+    } else {
+      status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+    }
     if (status != NFCSTATUS_SUCCESS) {
       NXPLOG_NCIHAL_E("NCI_CORE_INIT : Failed");
       retry_core_init_cnt++;
@@ -2142,8 +2172,12 @@ retrySetclock:
   if (nxpprofile_ctrl.bClkSrcVal == CLK_SRC_PLL) {
     static uint8_t set_clock_cmd[] = {0x20, 0x02, 0x09, 0x02, 0xA0, 0x03,
                                       0x01, 0x11, 0xA0, 0x04, 0x01, 0x01};
+#if (NFC_NXP_CHIP_TYPE == PN553)
+    uint8_t param_clock_src = 0x00;
+#else
     uint8_t param_clock_src = CLK_SRC_PLL;
     param_clock_src = param_clock_src << 3;
+#endif
 
     if (nxpprofile_ctrl.bClkFreqVal == CLK_FREQ_13MHZ) {
       param_clock_src |= 0x00;
@@ -2159,7 +2193,11 @@ retrySetclock:
       param_clock_src |= 0x05;
     } else {
       NXPLOG_NCIHAL_E("Wrong clock freq, send default PLL@19.2MHz");
+#if (NFC_NXP_CHIP_TYPE == PN553)
+      param_clock_src = 0x01;
+#else
       param_clock_src = 0x11;
+#endif
     }
 
     set_clock_cmd[7] = param_clock_src;
@@ -2345,6 +2383,7 @@ void phNxpNciHal_enable_i2c_fragmentation() {
   static uint8_t cmd_reset_nci[] = {0x20, 0x00, 0x01, 0x00};
   /*NCI_INIT_CMD*/
   static uint8_t cmd_init_nci[] = {0x20, 0x01, 0x00};
+  static uint8_t cmd_init_nci2_0[] = {0x20, 0x01, 0x02, 0x00, 0x00};
   static uint8_t get_i2c_fragmentation_cmd[] = {0x20, 0x03, 0x03,
                                                 0x01, 0xA0, 0x05};
   isfound = (GetNxpNumValue(NAME_NXP_I2C_FRAGMENTATION_ENABLED,
@@ -2386,7 +2425,12 @@ void phNxpNciHal_enable_i2c_fragmentation() {
       if (status != NFCSTATUS_SUCCESS) {
         NXPLOG_NCIHAL_E("NCI_CORE_RESET: Failed");
       }
-      status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+      if (nxpncihal_ctrl.nci_info.nci_version == NCI_VERSION_2_0) {
+        status =
+            phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci2_0), cmd_init_nci2_0);
+      } else {
+        status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+      }
       if (status != NFCSTATUS_SUCCESS) {
         NXPLOG_NCIHAL_E("NCI_CORE_INIT : Failed");
       } else if (i2c_status == 0x01) {
@@ -2524,7 +2568,7 @@ NFCSTATUS phNxpNciHal_core_reset_recovery() {
   /*NCI_RESET_CMD*/
   static uint8_t cmd_reset_nci[] = {0x20, 0x00, 0x01,
                                     0x00};  // keep configuration
-
+  static uint8_t cmd_init_nci2_0[] = {0x20, 0x01, 0x02, 0x00, 0x00};
   /* reset config cache */
   uint8_t retry_core_init_cnt = 0;
 
@@ -2553,7 +2597,11 @@ retry_core_init:
     retry_core_init_cnt++;
     goto retry_core_init;
   }
-  status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+  if (nxpncihal_ctrl.nci_data.nci_version == NCI_VERSION_2_0) {
+    status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci2_0), cmd_init_nci2_0);
+  } else {
+    status = phNxpNciHal_send_ext_cmd(sizeof(cmd_init_nci), cmd_init_nci);
+  }
   if (status != NFCSTATUS_SUCCESS) {
     NXPLOG_NCIHAL_D("NCI_CORE_INIT : Failed");
     retry_core_init_cnt++;
diff --git a/halimpl/pn54x/hal/phNxpNciHal.h b/halimpl/pn54x/hal/phNxpNciHal.h
index 7fd9af0..e03ad7b 100644
--- a/halimpl/pn54x/hal/phNxpNciHal.h
+++ b/halimpl/pn54x/hal/phNxpNciHal.h
@@ -25,10 +25,24 @@
 #define NCI_POLL_DURATION 500
 #define HAL_NFC_ENABLE_I2C_FRAGMENTATION_EVT 0x07
 #undef P2P_PRIO_LOGIC_HAL_IMP
-
+#define NCI_VERSION_2_0 0x20
+#define NCI_VERSION_1_1 0x11
+#define NCI_VERSION_1_0 0x10
+#define NCI_VERSION_UNKNOWN 0x00
 typedef void(phNxpNciHal_control_granted_callback_t)();
 
 /* NCI Data */
+
+#define NCI_MT_CMD 0x20
+#define NCI_MT_RSP 0x40
+#define NCI_MT_NTF 0x60
+
+#define CORE_RESET_TRIGGER_TYPE_CORE_RESET_CMD_RECEIVED 0x02
+#define CORE_RESET_TRIGGER_TYPE_POWERED_ON 0x01
+#define NCI_MSG_CORE_RESET 0x00
+#define NCI_MSG_CORE_INIT 0x01
+#define NCI_MT_MASK 0xE0
+#define NCI_OID_MASK 0x3F
 typedef struct nci_data {
   uint16_t len;
   uint8_t p_data[NCI_MAX_DATA_LEN];
@@ -39,7 +53,10 @@ typedef enum { HAL_STATUS_CLOSE = 0, HAL_STATUS_OPEN } phNxpNci_HalStatus;
 /* Macros to enable and disable extensions */
 #define HAL_ENABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 1)
 #define HAL_DISABLE_EXT() (nxpncihal_ctrl.hal_ext_enabled = 0)
-
+typedef struct phNxpNciInfo {
+  uint8_t nci_version;
+  bool_t wait_for_ntf;
+} phNxpNciInfo_t;
 /* NCI Control structure */
 typedef struct phNxpNciHal_Control {
   phNxpNci_HalStatus halStatus; /* Indicate if hal is open or closed */
@@ -75,6 +92,7 @@ typedef struct phNxpNciHal_Control {
   /* retry count used to force download */
   uint16_t retry_cnt;
   uint8_t read_retry_cnt;
+  phNxpNciInfo_t nci_info;
 } phNxpNciHal_Control_t;
 
 typedef struct phNxpNciClock {
diff --git a/halimpl/pn54x/hal/phNxpNciHal_ext.c b/halimpl/pn54x/hal/phNxpNciHal_ext.c
index 4dbf206..a857c72 100644
--- a/halimpl/pn54x/hal/phNxpNciHal_ext.c
+++ b/halimpl/pn54x/hal/phNxpNciHal_ext.c
@@ -76,6 +76,8 @@ static void hal_extns_write_rsp_timeout_cb(uint32_t TimerId, void* pContext);
 #define PROPRIETARY_CMD_FELICA_READER_MODE 0xFE
 static uint8_t gFelicaReaderMode;
 
+static NFCSTATUS phNxpNciHal_ext_process_nfc_init_rsp(uint8_t* p_ntf,
+                                                      uint16_t* p_len);
 /*******************************************************************************
 **
 ** Function         phNxpNciHal_ext_init
@@ -260,6 +262,7 @@ NFCSTATUS phNxpNciHal_process_ext_rsp(uint8_t* p_ntf, uint16_t* p_len) {
         break;
     }
   }
+  phNxpNciHal_ext_process_nfc_init_rsp(p_ntf, p_len);
 
   if (p_ntf[0] == 0x61 && p_ntf[1] == 0x05 && p_ntf[2] == 0x15 &&
       p_ntf[4] == 0x01 && p_ntf[5] == 0x06 && p_ntf[6] == 0x06) {
@@ -296,17 +299,6 @@ NFCSTATUS phNxpNciHal_process_ext_rsp(uint8_t* p_ntf, uint16_t* p_len) {
     p_ntf[3] = 0x00;
     p_ntf[4] = 0x00;
     *p_len = 5;
-  } else if ((p_ntf[0] == 0x40) && (p_ntf[1] == 0x01)) {
-    int len = p_ntf[2] + 2; /*include 2 byte header*/
-    wFwVerRsp = (((uint32_t)p_ntf[len - 2]) << 16U) |
-                (((uint32_t)p_ntf[len - 1]) << 8U) | p_ntf[len];
-    if (wFwVerRsp == 0) status = NFCSTATUS_FAILED;
-    iCoreInitRspLen = *p_len;
-    memcpy(bCoreInitRsp, p_ntf, *p_len);
-    NXPLOG_NCIHAL_D("NxpNci> FW Version: %x.%x.%x", p_ntf[len - 2],
-                    p_ntf[len - 1], p_ntf[len]);
-    fw_maj_ver = p_ntf[len - 1];
-    rom_version = p_ntf[len - 2];
   }
   // 4200 02 00 01
   else if (p_ntf[0] == 0x42 && p_ntf[1] == 0x00 && ee_disc_done == 0x01) {
@@ -335,21 +327,6 @@ NFCSTATUS phNxpNciHal_process_ext_rsp(uint8_t* p_ntf, uint16_t* p_len) {
   } else if (p_ntf[0] == 0x41 && p_ntf[1] == 0x04 && cleanup_timer != 0) {
     status = NFCSTATUS_FAILED;
     return status;
-  } else if (p_ntf[0] == 0x60 && p_ntf[1] == 0x00) {
-    NXPLOG_NCIHAL_E("CORE_RESET_NTF received!");
-#if (NFC_NXP_CHIP_TYPE == PN548C2)
-    if (nfcdep_detected &&
-        !(p_ntf[2] == 0x06 && p_ntf[3] == 0xA0 && p_ntf[4] == 0x00 &&
-          ((p_ntf[5] == 0xC9 && p_ntf[6] == 0x95 && p_ntf[7] == 0x00 &&
-            p_ntf[8] == 0x00) ||
-           (p_ntf[5] == 0x07 && p_ntf[6] == 0x39 && p_ntf[7] == 0xF2 &&
-            p_ntf[8] == 0x00)))) {
-      nfcdep_detected = 0x00;
-    }
-#endif
-    phNxpNciHal_emergency_recovery();
-    status = NFCSTATUS_FAILED;
-    return status;
   }
 #if (NFC_NXP_CHIP_TYPE == PN547C2)
   else if (p_ntf[0] == 0x61 && p_ntf[1] == 0x05 && p_ntf[4] == 0x02 &&
@@ -422,6 +399,83 @@ NFCSTATUS phNxpNciHal_process_ext_rsp(uint8_t* p_ntf, uint16_t* p_len) {
 }
 
 /******************************************************************************
+ * Function         phNxpNciHal_ext_process_nfc_init_rsp
+ *
+ * Description      This function is used to process the HAL NFC core reset rsp
+ *                  and ntf and core init rsp of NCI 1.0 or NCI2.0 and update
+ *                  NCI version.
+ *                  It also handles error response such as core_reset_ntf with
+ *                  error status in both NCI2.0 and NCI1.0.
+ *
+ * Returns          Returns NFCSTATUS_SUCCESS if parsing response is successful
+ *                  or returns failure.
+ *
+ *******************************************************************************/
+static NFCSTATUS phNxpNciHal_ext_process_nfc_init_rsp(uint8_t* p_ntf,
+                                                      uint16_t* p_len) {
+  NFCSTATUS status = NFCSTATUS_SUCCESS;
+  /* Parsing CORE_RESET_RSP and CORE_RESET_NTF to update NCI version.*/
+  if (p_ntf == NULL || *p_len == 0x00) {
+    return NFCSTATUS_FAILED;
+  }
+  if (p_ntf[0] == NCI_MT_RSP &&
+      ((p_ntf[1] & NCI_OID_MASK) == NCI_MSG_CORE_RESET)) {
+    if (p_ntf[2] == 0x01 && p_ntf[3] == 0x00) {
+      NXPLOG_NCIHAL_D("CORE_RESET_RSP NCI2.0");
+      if (nxpncihal_ctrl.hal_ext_enabled == TRUE) {
+        nxpncihal_ctrl.nci_info.wait_for_ntf = TRUE;
+      }
+    } else if (p_ntf[2] == 0x03 && p_ntf[3] == 0x00) {
+      NXPLOG_NCIHAL_D("CORE_RESET_RSP NCI1.0");
+      nxpncihal_ctrl.nci_info.nci_version = p_ntf[4];
+    }
+  } else if (p_ntf[0] == NCI_MT_NTF &&
+             ((p_ntf[1] & NCI_OID_MASK) == NCI_MSG_CORE_RESET)) {
+    if (p_ntf[3] == CORE_RESET_TRIGGER_TYPE_CORE_RESET_CMD_RECEIVED ||
+        p_ntf[3] == CORE_RESET_TRIGGER_TYPE_POWERED_ON) {
+      NXPLOG_NCIHAL_D("CORE_RESET_NTF NCI2.0 reason CORE_RESET_CMD received !");
+      nxpncihal_ctrl.nci_info.nci_version = p_ntf[5];
+      int len = p_ntf[2] + 2; /*include 2 byte header*/
+      wFwVerRsp = (((uint32_t)p_ntf[len - 2]) << 16U) |
+                  (((uint32_t)p_ntf[len - 1]) << 8U) | p_ntf[len];
+      NXPLOG_NCIHAL_D("NxpNci> FW Version: %x.%x.%x", p_ntf[len - 2],
+                      p_ntf[len - 1], p_ntf[len]);
+    } else {
+#if (NFC_NXP_CHIP_TYPE == PN548C2)
+      if (nfcdep_detected &&
+          !(p_ntf[2] == 0x06 && p_ntf[3] == 0xA0 && p_ntf[4] == 0x00 &&
+            ((p_ntf[5] == 0xC9 && p_ntf[6] == 0x95 && p_ntf[7] == 0x00 &&
+              p_ntf[8] == 0x00) ||
+             (p_ntf[5] == 0x07 && p_ntf[6] == 0x39 && p_ntf[7] == 0xF2 &&
+              p_ntf[8] == 0x00)))) {
+        nfcdep_detected = 0x00;
+      }
+#endif
+      phNxpNciHal_emergency_recovery();
+      status = NFCSTATUS_FAILED;
+    } /* Parsing CORE_INIT_RSP*/
+  } else if (p_ntf[0] == NCI_MT_RSP &&
+             ((p_ntf[1] & NCI_OID_MASK) == NCI_MSG_CORE_INIT)) {
+    if (nxpncihal_ctrl.nci_info.nci_version == NCI_VERSION_2_0) {
+      NXPLOG_NCIHAL_D("CORE_INIT_RSP NCI2.0 received !");
+    } else {
+      NXPLOG_NCIHAL_D("CORE_INIT_RSP NCI1.0 received !");
+      int len = p_ntf[2] + 2; /*include 2 byte header*/
+      wFwVerRsp = (((uint32_t)p_ntf[len - 2]) << 16U) |
+                  (((uint32_t)p_ntf[len - 1]) << 8U) | p_ntf[len];
+      if (wFwVerRsp == 0) status = NFCSTATUS_FAILED;
+      iCoreInitRspLen = *p_len;
+      memcpy(bCoreInitRsp, p_ntf, *p_len);
+      NXPLOG_NCIHAL_D("NxpNci> FW Version: %x.%x.%x", p_ntf[len - 2],
+                      p_ntf[len - 1], p_ntf[len]);
+      fw_maj_ver = p_ntf[len - 1];
+      rom_version = p_ntf[len - 2];
+    }
+  }
+  return status;
+}
+
+/******************************************************************************
  * Function         phNxpNciHal_process_ext_cmd_rsp
  *
  * Description      This function process the extension command response. It
@@ -472,7 +526,6 @@ static NFCSTATUS phNxpNciHal_process_ext_cmd_rsp(uint16_t cmd_len,
 
   /* Stop Timer */
   status = phOsalNfc_Timer_Stop(timeoutTimerId);
-
   if (NFCSTATUS_SUCCESS == status) {
     NXPLOG_NCIHAL_D("Response timer stopped");
   } else {
@@ -480,6 +533,32 @@ static NFCSTATUS phNxpNciHal_process_ext_cmd_rsp(uint16_t cmd_len,
     status = NFCSTATUS_FAILED;
     goto clean_and_return;
   }
+  /* Start timer to wait for NTF*/
+  if (nxpncihal_ctrl.nci_info.wait_for_ntf == TRUE) {
+    status = phOsalNfc_Timer_Start(timeoutTimerId, HAL_EXTNS_WRITE_RSP_TIMEOUT,
+                                   &hal_extns_write_rsp_timeout_cb, NULL);
+    if (NFCSTATUS_SUCCESS == status) {
+      NXPLOG_NCIHAL_D("Response timer started");
+    } else {
+      NXPLOG_NCIHAL_E("Response timer not started!!!");
+      status = NFCSTATUS_FAILED;
+      goto clean_and_return;
+    }
+    if (SEM_WAIT(nxpncihal_ctrl.ext_cb_data)) {
+      NXPLOG_NCIHAL_E("p_hal_ext->ext_cb_data.sem semaphore error");
+      /* Stop Timer */
+      status = phOsalNfc_Timer_Stop(timeoutTimerId);
+      goto clean_and_return;
+    }
+    status = phOsalNfc_Timer_Stop(timeoutTimerId);
+    if (NFCSTATUS_SUCCESS == status) {
+      NXPLOG_NCIHAL_D("Response timer stopped");
+    } else {
+      NXPLOG_NCIHAL_E("Response timer stop ERROR!!!");
+      status = NFCSTATUS_FAILED;
+      goto clean_and_return;
+    }
+  }
 
   if (nxpncihal_ctrl.ext_cb_data.status != NFCSTATUS_SUCCESS) {
     NXPLOG_NCIHAL_E(
@@ -494,7 +573,7 @@ static NFCSTATUS phNxpNciHal_process_ext_cmd_rsp(uint16_t cmd_len,
 
 clean_and_return:
   phNxpNciHal_cleanup_cb_data(&nxpncihal_ctrl.ext_cb_data);
-
+  nxpncihal_ctrl.nci_info.wait_for_ntf = FALSE;
   return status;
 }
 
@@ -523,7 +602,26 @@ NFCSTATUS phNxpNciHal_write_ext(uint16_t* cmd_len, uint8_t* p_cmd_data,
   if (phNxpDta_IsEnable() == true) {
     status = phNxpNHal_DtaUpdate(cmd_len, p_cmd_data, rsp_len, p_rsp_data);
   }
-
+  if (nxpncihal_ctrl.nci_info.nci_version == NCI_VERSION_2_0 &&
+      p_cmd_data[0] == 0x21 && p_cmd_data[1] == 0x01) {
+    NXPLOG_NCIHAL_D("Setting up routing table - start");
+    p_cmd_data[2] = 0x0C;
+    p_cmd_data[3] = 0x00;
+    p_cmd_data[4] = 0x02;
+    p_cmd_data[5] = 0x01;
+    p_cmd_data[6] = 0x03;
+    p_cmd_data[7] = 0x00;
+    p_cmd_data[8] = 0x01;
+    p_cmd_data[9] = 0x05;
+    p_cmd_data[10] = 0x01;
+    p_cmd_data[11] = 0x03;
+    p_cmd_data[12] = 0x00;
+    p_cmd_data[13] = 0x01;
+    p_cmd_data[14] = 0x04;
+    *cmd_len = 15;
+    NXPLOG_NCIHAL_D("Setting up routing table - END");
+    status = NFCSTATUS_SUCCESS;
+  }
   if (p_cmd_data[0] == PROPRIETARY_CMD_FELICA_READER_MODE &&
       p_cmd_data[1] == PROPRIETARY_CMD_FELICA_READER_MODE &&
       p_cmd_data[2] == PROPRIETARY_CMD_FELICA_READER_MODE) {
diff --git a/halimpl/pn54x/libnfc-brcm_NCI2_0.conf b/halimpl/pn54x/libnfc-brcm_NCI2_0.conf
new file mode 100644
index 0000000..9d6d9f9
--- /dev/null
+++ b/halimpl/pn54x/libnfc-brcm_NCI2_0.conf
@@ -0,0 +1,398 @@
+###################### Start of libnfc-brcm.conf #######################
+
+###############################################################################
+# Application options
+APPL_TRACE_LEVEL=0xFF
+PROTOCOL_TRACE_LEVEL=0xFFFFFFFF
+
+###############################################################################
+# performance measurement
+# Change this setting to control how often USERIAL log the performance (throughput)
+# data on read/write/poll
+# defailt is to log performance dara for every 100 read or write
+#REPORT_PERFORMANCE_MEASURE=100
+
+###############################################################################
+# File used for NFA storage
+NFA_STORAGE="/data/nfc"
+
+###############################################################################
+# Snooze Mode Settings
+#
+#  By default snooze mode is enabled.  Set SNOOZE_MODE_CFG byte[0] to 0
+#  to disable.
+#
+#  If SNOOZE_MODE_CFG is not provided, the default settings are used:
+#  They are as follows:
+#       8             Sleep Mode (0=Disabled 1=UART 8=SPI/I2C)
+#       0             Idle Threshold Host
+#       0             Idle Threshold HC
+#       0             NFC Wake active mode (0=ActiveLow 1=ActiveHigh)
+#       1             Host Wake active mode (0=ActiveLow 1=ActiveHigh)
+#
+#SNOOZE_MODE_CFG={08:00:00:00:01}
+
+###############################################################################
+# Insert a delay in milliseconds after NFC_WAKE and before write to NFCC
+#NFC_WAKE_DELAY=20
+
+###############################################################################
+# Various Delay settings (in ms) used in USERIAL
+#  POWER_ON_DELAY
+#    Delay after turning on chip, before writing to transport (default 300)
+#  PRE_POWER_OFF_DELAY
+#    Delay after deasserting NFC-Wake before turn off chip (default 0)
+#  POST_POWER_OFF_DELAY
+#    Delay after turning off chip, before USERIAL_close returns (default 0)
+#
+#POWER_ON_DELAY=300
+#PRE_POWER_OFF_DELAY=0
+#POST_POWER_OFF_DELAY=0
+
+###############################################################################
+# Maximum time (ms) to wait for RESET NTF after setting REG_PU to high
+# The default is 1000.
+#NFCC_ENABLE_TIMEOUT=0
+
+###############################################################################
+# LPTD mode configuration
+#  byte[0] is the length of the remaining bytes in this value
+#     if set to 0, LPTD params will NOT be sent to NFCC (i.e. disabled).
+#  byte[1] is the param id it should be set to B9.
+#  byte[2] is the length of the LPTD parameters
+#  byte[3] indicates if LPTD is enabled
+#     if set to 0, LPTD will be disabled (parameters will still be sent).
+#  byte[4-n] are the LPTD parameters.
+#  By default, LPTD is enabled and default settings are used.
+#  See nfc_hal_dm_cfg.c for defaults
+#LPTD_CFG={23:B9:21:01:02:FF:FF:04:A0:0F:40:00:80:02:02:10:00:00:00:31:0C:30:00:00:00:00:00:00:00:00:00:00:00:00:00:00}
+
+###############################################################################
+# Startup Configuration (100 bytes maximum)
+#
+# For the 0xCA parameter, byte[9] (marked by 'AA') is for UICC0, and byte[10] (marked by BB) is
+#    for UICC1.  The values are defined as:
+#   0 : UICCx only supports ISO_DEP in low power mode.
+#   2 : UICCx only supports Mifare in low power mode.
+#   3 : UICCx supports both ISO_DEP and Mifare in low power mode.
+#
+#                                                                          AA BB
+#NFA_DM_START_UP_CFG={1F:CB:01:01:A5:01:01:CA:14:00:00:00:00:06:E8:03:00:00:00:00:00:00:00:00:00:00:00:00:00:80:01:01}
+
+###############################################################################
+# Startup Vendor Specific Configuration (100 bytes maximum);
+#  byte[0] TLV total len = 0x5
+#  byte[1] NCI_MTS_CMD|NCI_GID_PROP = 0x2f
+#  byte[2] NCI_MSG_FRAME_LOG = 0x9
+#  byte[3] 2
+#  byte[4] 0=turn off RF frame logging; 1=turn on
+#  byte[5] 0=turn off SWP frame logging; 1=turn on
+#  NFA_DM_START_UP_VSC_CFG={05:2F:09:02:01:01}
+
+###############################################################################
+# Antenna Configuration - This data is used when setting 0xC8 config item
+# at startup (before discovery is started).  If not used, no value is sent.
+#
+# The settings for this value are documented here:
+# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
+#   Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
+# This document is maintained by Paul Forshaw.
+#
+# The values marked as ?? should be tweaked per antenna or customer/app:
+# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
+# array[0] = 0x20 is length of the payload from array[1] to the end
+# array[1] = 0xC8 is PREINIT_DSP_CFG
+#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
+
+###############################################################################
+# Configure crystal frequency when internal LPO can't detect the frequency.
+#XTAL_FREQUENCY=0
+###############################################################################
+# Configure the default Destination Gate used by HCI (the default is 4, which
+# is the ETSI loopback gate.
+NFA_HCI_DEFAULT_DEST_GATE=0xF0
+
+###############################################################################
+# Configure the single default SE to use.  The default is to use the first
+# SE that is detected by the stack.  This value might be used when the phone
+# supports multiple SE (e.g. 0xF3 and 0xF4) but you want to force it to use
+# one of them (e.g. 0xF4).
+#ACTIVE_SE=0xF3
+
+###############################################################################
+# Configure the default NfcA/IsoDep techology and protocol route. Can be
+# either a secure element (e.g. 0xF4) or the host (0x00)
+#DEFAULT_ISODEP_ROUTE=0x00
+
+###############################################################################
+# Configure the NFC Extras to open and use a static pipe.  If the value is
+# not set or set to 0, then the default is use a dynamic pipe based on a
+# destination gate (see NFA_HCI_DEFAULT_DEST_GATE).  Note there is a value
+# for each UICC (where F3="UICC0" and F4="UICC1")
+#NFA_HCI_STATIC_PIPE_ID_F3=0x70
+#NFA_HCI_STATIC_PIPE_ID_01=0x19
+NFA_HCI_STATIC_PIPE_ID_C0=0x19
+###############################################################################
+# When disconnecting from Oberthur secure element, perform a warm-reset of
+# the secure element to deselect the applet.
+# The default hex value of the command is 0x3.  If this variable is undefined,
+# then this feature is not used.
+#OBERTHUR_WARM_RESET_COMMAND=0x03
+
+###############################################################################
+# Force UICC to only listen to the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B | NFA_TECHNOLOGY_MASK_F
+UICC_LISTEN_TECH_MASK=0x07
+
+###############################################################################
+# Force HOST listen feature enable or disable.
+# 0: Disable
+# 1: Enable
+HOST_LISTEN_ENABLE=0x01
+
+###############################################################################
+# Enabling/Disabling Forward functionality
+# Disable           0x00
+# Enable            0x01
+NXP_FWD_FUNCTIONALITY_ENABLE=0x01
+
+###############################################################################
+# Allow UICC to be powered off if there is no traffic.
+# Timeout is in ms. If set to 0, then UICC will not be powered off.
+#UICC_IDLE_TIMEOUT=30000
+UICC_IDLE_TIMEOUT=0
+
+###############################################################################
+# AID for Empty Select command
+# If specified, this AID will be substituted when an Empty SELECT command is
+# detected.  The first byte is the length of the AID.  Maximum length is 16.
+AID_FOR_EMPTY_SELECT={08:A0:00:00:01:51:00:00:00}
+###############################################################################
+# Maximum Number of Credits to be allowed by the NFCC
+#   This value overrides what the NFCC specifices allowing the host to have
+#   the control to work-around transport limitations.  If this value does
+#   not exist or is set to 0, the NFCC will provide the number of credits.
+MAX_RF_DATA_CREDITS=1
+
+###############################################################################
+# This setting allows you to disable registering the T4t Virtual SE that causes
+# the NFCC to send PPSE requests to the DH.
+# The default setting is enabled (i.e. T4t Virtual SE is registered).
+#REGISTER_VIRTUAL_SE=1
+
+###############################################################################
+# When screen is turned off, specify the desired power state of the controller.
+# 0: power-off-sleep state; DEFAULT
+# 1: full-power state
+# 2: screen-off card-emulation (CE4/CE3/CE1 modes are used)
+SCREEN_OFF_POWER_STATE=1
+
+###############################################################################
+# Firmware patch file
+#  If the value is not set then patch download is disabled.
+#FW_PATCH="/vendor/firmware/bcm2079x_firmware.ncd"
+
+###############################################################################
+# Firmware pre-patch file (sent before the above patch file)
+#  If the value is not set then pre-patch is not used.
+#FW_PRE_PATCH="/vendor/firmware/bcm2079x_pre_firmware.ncd"
+
+###############################################################################
+# Firmware patch format
+#   1 = HCD
+#   2 = NCD (default)
+#NFA_CONFIG_FORMAT=2
+
+###############################################################################
+# SPD Debug mode
+#  If set to 1, any failure of downloading a patch will trigger a hard-stop
+#SPD_DEBUG=0
+
+###############################################################################
+# SPD Max Retry Count
+#  The number of attempts to download a patch before giving up (defualt is 3).
+#  Note, this resets after a power-cycle.
+#SPD_MAX_RETRY_COUNT=3
+
+###############################################################################
+# transport driver
+#
+# TRANSPORT_DRIVER=<driver>
+#
+#  where <driver> can be, for example:
+#    "/dev/ttyS"        (UART)
+#    "/dev/bcmi2cnfc"   (I2C)
+#    "hwtun"            (HW Tunnel)
+#    "/dev/bcmspinfc"   (SPI)
+#    "/dev/btusb0"      (BT USB)
+#TRANSPORT_DRIVER="/dev/bcm2079x-i2c"
+
+###############################################################################
+# power control driver
+# Specify a kernel driver that support ioctl commands to control NFC_EN and
+# NFC_WAKE gpio signals.
+#
+# POWER_CONTRL_DRIVER=<driver>
+#  where <driver> can be, for example:
+#    "/dev/nfcpower"
+#    "/dev/bcmi2cnfc"   (I2C)
+#    "/dev/bcmspinfc"   (SPI)
+#    i2c and spi driver may be used to control NFC_EN and NFC_WAKE signal
+#POWER_CONTROL_DRIVER="/dev/bcm2079x-i2c"
+
+###############################################################################
+# I2C transport driver options
+# Mako does not support 10-bit I2C addresses
+# Revert to 7-bit address
+#BCMI2CNFC_ADDRESS=0x77
+
+###############################################################################
+# I2C transport driver try to read multiple packets in read() if data is available
+# remove the comment below to enable this feature
+#READ_MULTIPLE_PACKETS=1
+
+###############################################################################
+# SPI transport driver options
+#SPI_NEGOTIATION={0A:F0:00:01:00:00:00:FF:FF:00:00}
+
+###############################################################################
+# UART transport driver options
+#
+# PORT=1,2,3,...
+# BAUD=115200, 19200, 9600, 4800,
+# DATABITS=8, 7, 6, 5
+# PARITY="even" | "odd" | "none"
+# STOPBITS="0" | "1" | "1.5" | "2"
+
+#UART_PORT=2
+#UART_BAUD=115200
+#UART_DATABITS=8
+#UART_PARITY="none"
+#UART_STOPBITS="1"
+
+###############################################################################
+# Insert a delay in microseconds per byte after a write to NFCC.
+# after writing a block of data to the NFCC, delay this an amopunt of time before
+# writing next block of data.  the delay is calculated as below
+#   NFC_WRITE_DELAY * (number of byte written) / 1000 milliseconds
+# e.g. after 259 bytes is written, delay (259 * 20 / 1000) 5 ms before next write
+#NFC_WRITE_DELAY=20
+
+###############################################################################
+# Maximum Number of Credits to be allowed by the NFCC
+#   This value overrides what the NFCC specifices allowing the host to have
+#   the control to work-around transport limitations.  If this value does
+#   not exist or is set to 0, the NFCC will provide the number of credits.
+MAX_RF_DATA_CREDITS=1
+
+###############################################################################
+# Default poll duration (in ms)
+#  The defualt is 500ms if not set (see nfc_target.h)
+#NFA_DM_DISC_DURATION_POLL=333
+###############################################################################
+# Antenna Configuration - This data is used when setting 0xC8 config item
+# at startup (before discovery is started).  If not used, no value is sent.
+#
+# The settings for this value are documented here:
+# http://wcgbu.broadcom.com/wpan/PM/Project%20Document%20Library/bcm20791B0/
+#   Design/Doc/PHY%20register%20settings/BCM20791-B2-1027-02_PHY_Recommended_Reg_Settings.xlsx
+# This document is maintained by Paul Forshaw.
+#
+# The values marked as ?? should be tweaked per antenna or customer/app:
+# {20:C8:1E:06:??:00:??:??:??:00:??:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:??:01:00:00:40:04}
+# array[0] = 0x20 is length of the payload from array[1] to the end
+# array[1] = 0xC8 is PREINIT_DSP_CFG
+#PREINIT_DSP_CFG={20:C8:1E:06:1F:00:0F:03:3C:00:04:24:00:1C:00:75:00:77:00:76:00:1C:00:03:00:0A:00:48:01:00:00:40:04}
+
+###############################################################################
+# Choose the presence-check algorithm for type-4 tag.  If not defined, the default value is 1.
+# 0  NFA_RW_PRES_CHK_DEFAULT; Let stack selects an algorithm
+# 1  NFA_RW_PRES_CHK_I_BLOCK; ISO-DEP protocol's empty I-block
+# 2  NFA_RW_PRES_CHK_RESET; Deactivate to Sleep, then re-activate
+# 3  NFA_RW_PRES_CHK_RB_CH0; Type-4 tag protocol's ReadBinary command on channel 0
+# 4  NFA_RW_PRES_CHK_RB_CH3; Type-4 tag protocol's ReadBinary command on channel 3
+PRESENCE_CHECK_ALGORITHM=1
+
+###############################################################################
+# Force tag polling for the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_B |
+#            NFA_TECHNOLOGY_MASK_F | NFA_TECHNOLOGY_MASK_ISO15693 |
+#            NFA_TECHNOLOGY_MASK_B_PRIME | NFA_TECHNOLOGY_MASK_KOVIO |
+#            NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE.
+#
+# Notable bits:
+# NFA_TECHNOLOGY_MASK_A             0x01    /* NFC Technology A             */
+# NFA_TECHNOLOGY_MASK_B             0x02    /* NFC Technology B             */
+# NFA_TECHNOLOGY_MASK_F             0x04    /* NFC Technology F             */
+# NFA_TECHNOLOGY_MASK_ISO15693      0x08    /* Proprietary Technology       */
+# NFA_TECHNOLOGY_MASK_KOVIO         0x20    /* Proprietary Technology       */
+# NFA_TECHNOLOGY_MASK_ACTIVE      0x40    /* NFC Technology A active mode */
+POLLING_TECH_MASK=0x4F
+
+###############################################################################
+# Force P2P to only listen for the following technology(s).
+# The bits are defined as tNFA_TECHNOLOGY_MASK in nfa_api.h.
+# Default is NFA_TECHNOLOGY_MASK_A | NFA_TECHNOLOGY_MASK_F |
+#            NFA_TECHNOLOGY_MASK_A_ACTIVE | NFA_TECHNOLOGY_MASK_F_ACTIVE
+#
+# Notable bits:
+# NFA_TECHNOLOGY_MASK_A             0x01    /* NFC Technology A             */
+# NFA_TECHNOLOGY_MASK_F             0x04    /* NFC Technology F             */
+# NFA_TECHNOLOGY_MASK_ACTIVE      0x40    /* NFC Technology A active mode */
+P2P_LISTEN_TECH_MASK=0x45
+
+PRESERVE_STORAGE=0x01
+
+###############################################################################
+# Override the stack default for NFA_EE_MAX_EE_SUPPORTED set in nfc_target.h.
+# The value is set to 3 by default as it assumes we will discover 0xF2,
+# 0xF3, and 0xF4. If a platform will exclude and SE, this value can be reduced
+# so that the stack will not wait any longer than necessary.
+
+# Maximum EE supported number
+# NXP PN547C2 0x02
+# NXP PN65T 0x03
+# NXP PN548C2 0x02
+# NXP PN66T 0x03
+NFA_MAX_EE_SUPPORTED=0x02
+
+###############################################################################
+# NCI Hal Module name
+NCI_HAL_MODULE="nfc_nci"
+
+##############################################################################
+# Deactivate notification wait time out in seconds used in ETSI Reader mode
+# 0 - Infinite wait
+#NFA_DM_DISC_NTF_TIMEOUT=0
+
+###############################################################################
+# AID_MATCHING constants
+# AID_MATCHING_EXACT_ONLY 0x00
+# AID_MATCHING_EXACT_OR_PREFIX 0x01
+# AID_MATCHING_PREFIX_ONLY 0x02
+AID_MATCHING_MODE=0x01
+
+###############################################################################
+# Default Secure Element route id
+DEFAULT_OFFHOST_ROUTE=0x02
+
+###############################################################################
+# Vendor Specific Proprietary Protocol & Discovery Configuration
+# Set to 0xFF if unsupported
+#  byte[0] NCI_PROTOCOL_18092_ACTIVE
+#  byte[1] NCI_PROTOCOL_B_PRIME
+#  byte[2] NCI_PROTOCOL_DUAL
+#  byte[3] NCI_PROTOCOL_15693
+#  byte[4] NCI_PROTOCOL_KOVIO
+#  byte[5] NCI_PROTOCOL_MIFARE
+#  byte[6] NCI_DISCOVERY_TYPE_POLL_KOVIO
+#  byte[7] NCI_DISCOVERY_TYPE_POLL_B_PRIME
+#  byte[8] NCI_DISCOVERY_TYPE_LISTEN_B_PRIME
+NFA_PROPRIETARY_CFG={05:FF:FF:06:81:80:70:FF:FF}
+
+###############################################################################
+# Bail out mode
+#  If set to 1, NFCC is using bail out mode for either Type A or Type B poll.
+NFA_POLL_BAIL_OUT_MODE=0x01
diff --git a/halimpl/pn54x/libnfc-nxp-PN553_example_NCI2_0.conf b/halimpl/pn54x/libnfc-nxp-PN553_example_NCI2_0.conf
new file mode 100644
index 0000000..e3783fc
--- /dev/null
+++ b/halimpl/pn54x/libnfc-nxp-PN553_example_NCI2_0.conf
@@ -0,0 +1,448 @@
+## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
+## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
+###############################################################################
+# Application options
+# Logging Levels
+# NXPLOG_DEFAULT_LOGLEVEL    0x01
+# ANDROID_LOG_DEBUG          0x03
+# ANDROID_LOG_WARN           0x02
+# ANDROID_LOG_ERROR          0x01
+# ANDROID_LOG_SILENT         0x00
+NXPLOG_EXTNS_LOGLEVEL=0x03
+NXPLOG_NCIHAL_LOGLEVEL=0x03
+NXPLOG_NCIX_LOGLEVEL=0x03
+NXPLOG_NCIR_LOGLEVEL=0x03
+NXPLOG_FWDNLD_LOGLEVEL=0x03
+NXPLOG_TML_LOGLEVEL=0x03
+
+###############################################################################
+# Nfc Device Node name
+NXP_NFC_DEV_NODE="/dev/pn553"
+
+###############################################################################
+# Extension for Mifare reader enable
+MIFARE_READER_ENABLE=0x01
+
+###############################################################################
+# Vzw Feature enable
+VZW_FEATURE_ENABLE=0x01
+
+###############################################################################
+# File name for Firmware
+NXP_FW_NAME="libpn553_fw.so"
+
+###############################################################################
+# System clock source selection configuration
+#define CLK_SRC_XTAL       1
+#define CLK_SRC_PLL        2
+NXP_SYS_CLK_SRC_SEL=0x02
+
+###############################################################################
+# System clock frequency selection configuration
+#define CLK_FREQ_13MHZ         1
+#define CLK_FREQ_19_2MHZ       2
+#define CLK_FREQ_24MHZ         3
+#define CLK_FREQ_26MHZ         4
+#define CLK_FREQ_38_4MHZ       5
+#define CLK_FREQ_52MHZ         6
+NXP_SYS_CLK_FREQ_SEL=0x02
+
+###############################################################################
+# The timeout value to be used for clock request acknowledgment
+# min value = 0x01 to max = 0x06
+NXP_SYS_CLOCK_TO_CFG=0x01
+
+###############################################################################
+# NXP proprietary settings
+NXP_ACT_PROP_EXTN={2F, 02, 00}
+
+###############################################################################
+# NFC forum profile settings
+NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
+
+###############################################################################
+# NFCC Configuration Control
+# Allow NFCC to manage RF Config       0x01
+# Don't allow NFCC to manage RF Config 0x00
+NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
+
+###############################################################################
+# Standby enable settings
+#NXP_CORE_STANDBY={2F, 00, 01, 01}
+
+###############################################################################
+# NXP TVDD configurations settings
+# Allow NFCC to configure External TVDD, two configurations (1 and 2) supported,
+# out of them only one can be configured at a time.
+NXP_EXT_TVDD_CFG=0x02
+
+###############################################################################
+#config1:SLALM, 3.3V for both RM and CM
+NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C}
+
+###############################################################################
+#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
+#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F, 00, D0, 0C}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_1={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_2={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_3={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_4={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_5={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_6={
+#}
+
+###############################################################################
+# Set configuration optimization decision setting
+# Enable    = 0x01
+# Disable   = 0x00
+NXP_SET_CONFIG_ALWAYS=0x00
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# Wired mode settings A0ED, A0EE
+# Tag Detector A040, A041, A043
+# Low Power mode A007
+# Clock settings A002, A003
+# PbF settings A008
+# Clock timeout settings A004
+# eSE (SVDD) PWR REQ settings A0F2
+# How eSE connected to PN553 A012
+# UICC2 bit rate A0D1
+# SWP1A interface A0D4
+# DWP intf behavior config, SVDD Load activated by default if set to 0x31 - A037
+NXP_CORE_CONF_EXTN={20, 02, 25, 09,
+    A0, EC, 01, 01,
+    A0, ED, 01, 00,
+    A0, 5E, 01, 01,
+    A0, 12, 01, 02,
+    A0, 40, 01, 01,
+    A0, DD, 01, 2D,
+    A0, D1, 01, 02,
+    A0, D4, 01, 01,
+    A0, 37, 01, 35
+   }
+#       A0, F2, 01, 01,
+#       A0, 40, 01, 01,
+#       A0, 41, 01, 02,
+#       A0, 43, 01, 04,
+#       A0, 02, 01, 01,
+#       A0, 03, 01, 11,
+#       A0, 07, 01, 03,
+#       A0, 08, 01, 01
+#       }
+
+###############################################################################
+# Core configuration rf field filter settings to enable set to 01 to disable set
+# to 00 last bit
+NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }
+
+###############################################################################
+# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set
+# to 0x00
+NXP_I2C_FRAGMENTATION_ENABLED=0x00
+
+###############################################################################
+# Core configuration settings
+NXP_CORE_CONF={ 20, 02, 31, 0F,
+        85, 01, 01,
+        28, 01, 00,
+        21, 01, 00,
+        30, 01, 08,
+        31, 01, 03,
+        32, 01, 60,
+        38, 01, 01,
+        33, 04, 01, 02, 03, 04,
+        54, 01, 06,
+        50, 01, 02,
+        5B, 01, 00,
+        80, 01, 01,
+        81, 01, 01,
+        82, 01, 0E,
+        18, 01, 01
+        }
+
+###############################################################################
+# Mifare Classic Key settings
+#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
+#                                     A0, 52, 06, D3, F7, D3, F7, D3, F7,
+#                                     A0, 53, 06, FF, FF, FF, FF, FF, FF,
+#                                     A0, 54, 06, 00, 00, 00, 00, 00, 00}
+
+
+###############################################################################
+# Default SE Options
+# No secure element 0x00
+# eSE               0x01
+# UICC              0x02
+# UICC2             0x04
+
+NXP_DEFAULT_SE=0x07
+
+###############################################################################
+#Enable SWP full power mode when phone is power off
+NXP_SWP_FULL_PWR_ON=0x00
+
+###############################################################################
+#### Select the CHIP ####
+#PN547C2            0x01
+#PN65T              0x02
+#PN548AD            0x03
+#PN66T              0x04
+#PN551              0x05
+#PN67T              0x06
+#PN553              0x07
+#PN80T              0x08
+NXP_NFC_CHIP=0x07
+
+###############################################################################
+# CE when Screen state is locked
+# This setting is for DEFAULT_AID_ROUTE,
+# DEFAULT_DESFIRE_ROUTE and DEFAULT_MIFARE_CLT_ROUTE
+# Disable           0x00
+# Enable            0x01
+NXP_CE_ROUTE_STRICT_DISABLE=0x01
+
+###############################################################################
+#Timeout in secs to get NFCEE Discover notification
+NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
+
+###############################################################################
+NXP_DEFAULT_NFCEE_TIMEOUT=20
+
+###############################################################################
+#Timeout in secs
+NXP_SWP_RD_START_TIMEOUT=0x0A
+
+###############################################################################
+#Timeout in secs
+NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
+
+###############################################################################
+#Set the default AID route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_AID_ROUTE=0x00
+
+###############################################################################
+#Set the Mifare Desfire route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_DESFIRE_ROUTE=0x02
+
+###############################################################################
+#Set the Mifare CLT route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_MIFARE_CLT_ROUTE=0x02
+
+###############################################################################
+#Set the default AID Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_AID_PWR_STATE=0x19
+
+###############################################################################
+#Set the Mifare Desfire Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_DESFIRE_PWR_STATE=0x1B
+
+###############################################################################
+#Set the Mifare CLT Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
+
+###############################################################################
+#Set the Felica CLT route Location :
+#This settings will be used when application does not set this parameter
+# eSE  0x01
+# UICC 0x02
+# UICC2 0x03
+DEFAULT_FELICA_CLT_ROUTE=0x01
+
+###############################################################################
+#Set the Felica CLT Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_FELICA_CLT_PWR_STATE=0x1B
+
+###############################################################################
+# AID Matching platform options
+# AID_MATCHING_L 0x01
+# AID_MATCHING_K 0x02
+AID_MATCHING_PLATFORM=0x01
+
+###############################################################################
+# P61 interface options
+# NFC 0x01
+# SPI 0x02
+NXP_P61_LS_DEFAULT_INTERFACE=0x01
+
+###############################################################################
+# P61 LTSM interface options
+# NFC 0x01
+# SPI 0x02
+NXP_P61_LTSM_DEFAULT_INTERFACE=0x01
+
+###############################################################################
+#CHINA_TIANJIN_RF_SETTING
+#Enable  0x01
+#Disable  0x00
+NXP_CHINA_TIANJIN_RF_ENABLED=0x01
+
+###############################################################################
+#SWP_SWITCH_TIMEOUT_SETTING
+# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
+# Timeout in milliseconds, for example
+# No Timeout  0x00
+# 10 millisecond timeout 0x0A
+NXP_SWP_SWITCH_TIMEOUT=0x0A
+
+###############################################################################
+# P61 interface options for JCOP Download
+# NFC 0x01
+# SPI 0x02
+NXP_P61_JCOP_DEFAULT_INTERFACE=0x01
+
+###############################################################################
+# P61 JCOP OS download  options
+# FRAMEWORK API BY APPLICATION 0x00
+# AT BOOT_TIME 0x01
+NXP_JCOPDL_AT_BOOT_ENABLE=0x00
+
+###############################################################################
+# Loader service version
+# NFC service checks for LS version 2.0 or 2.1
+# LS2.0 0x20
+# LS2.1 0x21
+# LS2.2 0x22
+# AT NFC service intialization
+NXP_LOADER_SERVICE_VERSION=0x22
+
+###############################################################################
+#Timeout value  in milliseconds for NFCC standby mode.The range is between 5000
+#msec to 20000 msec and zero is to disable.
+NXP_NFCC_STANDBY_TIMEOUT=20000
+
+###############################################################################
+#Dynamic RSSI feature enable
+# Disable           0x00
+# Enable            0x01
+NXP_AGC_DEBUG_ENABLE=0x00
+
+###############################################################################
+#Virtual Mode ESE and Wired Mode ongoing delay Wired Mode
+# For Technology routing to ESE Technology Mask = 4
+# For ISO-DEP Protocol routing to ESE Mask      = 2
+# It can also take TECH|PROTO    = 6
+# To ignore the delay set mask to = 0
+NXP_ESE_WIRED_PRT_MASK=0x00
+
+###############################################################################
+#Virtual Mode UICC and Wired Mode  ongoing delay Wired Mode
+#For Technology routing to UICC Technology Mask = 4
+#For ISO-DEP Protocol routing to UICC set Mask  = 2
+#For Select AID Routing to UICC       set Mask  = 1
+#It can also take values TECH|PROTO|SELECT_AID  = 7 , 6 , 5 ,3 .To ignore delay
+#set mask = 0
+NXP_UICC_WIRED_PRT_MASK=0x00
+
+###############################################################################
+#RF field true delay Wired Mode
+# delay wired mode = 1
+# allow wired mode = 0
+NXP_WIRED_MODE_RF_FIELD_ENABLE=0x00
+
+###############################################################################
+#Config to allow adding aids
+#NFC on/off is required after this config
+#1 = enabling adding aid  to NFCC routing table.
+#0 = disabling adding aid to NFCC routing table.
+NXP_ENABLE_ADD_AID=0x01
+
+###############################################################################
+# JCOP-3.3 continuous process timeout in msec and value should be in Hexadecimal
+# JCOP CP TIMEOUT
+NXP_CP_TIMEOUT={00, 77}
+
+###############################################################################
+# Enable/Disable checking default proto SE Id
+# Disable           0x00
+# Enable            0x01
+NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
+
+###############################################################################
+#NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE
+#Enable/Disable block number checks for china transit use case
+#Enable  0x01
+#Disable  0x00
+NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE=0x01
+
+###############################################################################
+# Restrict routing to first matched rule only.
+# Blacklist enable   0x01
+# Blacklist disable  0x00
+NXP_PROP_BLACKLIST_ROUTING=0x00
+
+###############################################################################
+# Timeout value in milliseconds to send response for Felica command received
+NXP_HCEF_CMD_RSP_TIMEOUT_VALUE=5000
+
+###############################################################################
\ No newline at end of file
diff --git a/halimpl/pn54x/libnfc-nxp-PN80T_example_NCI2_0.conf b/halimpl/pn54x/libnfc-nxp-PN80T_example_NCI2_0.conf
new file mode 100644
index 0000000..1f64ec7
--- /dev/null
+++ b/halimpl/pn54x/libnfc-nxp-PN80T_example_NCI2_0.conf
@@ -0,0 +1,488 @@
+## This file is used by NFC NXP NCI HAL(external/libnfc-nci/halimpl/pn547)
+## and NFC Service Java Native Interface Extensions (packages/apps/Nfc/nci/jni/extns/pn547)
+###############################################################################
+# Application options
+# Logging Levels
+# NXPLOG_DEFAULT_LOGLEVEL    0x01
+# ANDROID_LOG_DEBUG          0x03
+# ANDROID_LOG_WARN           0x02
+# ANDROID_LOG_ERROR          0x01
+# ANDROID_LOG_SILENT         0x00
+NXPLOG_EXTNS_LOGLEVEL=0x03
+NXPLOG_NCIHAL_LOGLEVEL=0x03
+NXPLOG_NCIX_LOGLEVEL=0x03
+NXPLOG_NCIR_LOGLEVEL=0x03
+NXPLOG_FWDNLD_LOGLEVEL=0x03
+NXPLOG_TML_LOGLEVEL=0x03
+
+###############################################################################
+# Nfc Device Node name
+NXP_NFC_DEV_NODE="/dev/pn553"
+
+###############################################################################
+# Extension for Mifare reader enable
+MIFARE_READER_ENABLE=0x01
+
+###############################################################################
+# Vzw Feature enable
+VZW_FEATURE_ENABLE=0x01
+
+###############################################################################
+# File name for Firmware
+NXP_FW_NAME="libpn553_fw.so"
+
+###############################################################################
+# System clock source selection configuration
+#define CLK_SRC_XTAL       1
+#define CLK_SRC_PLL        2
+NXP_SYS_CLK_SRC_SEL=0x02
+
+###############################################################################
+# System clock frequency selection configuration
+#define CLK_FREQ_13MHZ         1
+#define CLK_FREQ_19_2MHZ       2
+#define CLK_FREQ_24MHZ         3
+#define CLK_FREQ_26MHZ         4
+#define CLK_FREQ_38_4MHZ       5
+#define CLK_FREQ_52MHZ         6
+NXP_SYS_CLK_FREQ_SEL=0x02
+
+###############################################################################
+# The timeout value to be used for clock request acknowledgment
+# min value = 0x01 to max = 0x06
+NXP_SYS_CLOCK_TO_CFG=0x06
+
+###############################################################################
+# NXP proprietary settings
+NXP_ACT_PROP_EXTN={2F, 02, 00}
+
+###############################################################################
+# NFC forum profile settings
+NXP_NFC_PROFILE_EXTN={20, 02, 05, 01, A0, 44, 01, 00}
+
+###############################################################################
+# NFCC Configuration Control
+# Allow NFCC to manage RF Config       0x01
+# Don't allow NFCC to manage RF Config 0x00
+NXP_NFC_MERGE_RF_PARAMS={20, 02, 04, 01, 85, 01, 01}
+
+###############################################################################
+# Standby enable settings
+#NXP_CORE_STANDBY={2F, 00, 01, 01}
+
+###############################################################################
+# NXP TVDD configurations settings
+# Allow NFCC to configure External TVDD, two configurations (1 and 2) supported,
+# out of them only one can be configured at a time.
+NXP_EXT_TVDD_CFG=0x02
+
+###############################################################################
+#config1:SLALM, 3.3V for both RM and CM
+NXP_EXT_TVDD_CFG_1={20, 02, 0F, 01, A0, 0E, 0B, 31, 01, 01, 31, 00, 00, 00, 01, 00, D0, 0C}
+
+###############################################################################
+#config2: use DCDC in CE, use Tx_Pwr_Req, set CFG2 mode, SLALM,
+#monitoring 5V from DCDC, 3.3V for both RM and CM, DCDCWaitTime=4.2ms
+NXP_EXT_TVDD_CFG_2={20, 02, 0F, 01, A0, 0E, 0B, 11, 01, C2, B2, 00, B2, 1E, 1F, 00, D0, 0C}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_1={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_2={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_3={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_4={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_5={
+#}
+
+###############################################################################
+# NXP RF configuration ALM/PLM settings
+# This section needs to be updated with the correct values based on the platform
+#NXP_RF_CONF_BLK_6={
+#}
+
+###############################################################################
+# Set configuration optimization decision setting
+# Enable    = 0x01
+# Disable   = 0x00
+NXP_SET_CONFIG_ALWAYS=0x00
+
+###############################################################################
+# Core configuration extensions
+# It includes
+# Wired mode settings A0ED, A0EE
+# Tag Detector A040, A041, A043
+# Low Power mode A007
+# Clock settings A002, A003
+# PbF settings A008
+# Clock timeout settings A004
+# eSE (SVDD) PWR REQ settings A0F2
+# Window size A0D8
+# DWP Speed   A0D5
+# How eSE connected to PN553 A012
+# UICC2 bit rate A0D1
+# SWP1A interface A0D4
+# DWP intf behavior config, SVDD Load activated by default if set to 0x31 A037
+NXP_CORE_CONF_EXTN={20, 02, 29, 0A,
+    A0, EC, 01, 01,
+    A0, ED, 01, 01,
+    A0, 5E, 01, 01,
+    A0, 12, 01, 02,
+    A0, 40, 01, 01,
+    A0, D1, 01, 02,
+    A0, D4, 01, 01,
+    A0, 37, 01, 35,
+    A0, D8, 01, 02,
+    A0, D5, 01, 0A
+   }
+#       A0, F2, 01, 01,
+#       A0, 40, 01, 01,
+#       A0, 41, 01, 02,
+#       A0, 43, 01, 04,
+#       A0, 02, 01, 01,
+#       A0, 03, 01, 11,
+#       A0, 07, 01, 03,
+#       A0, 08, 01, 01
+#       }
+
+###############################################################################
+# Core configuration rf field filter settings to enable set to 01 to disable set
+# to 00 last bit
+NXP_CORE_RF_FIELD={ 20, 02, 05, 01, A0, 62, 01, 00 }
+
+###############################################################################
+# To enable i2c fragmentation set i2c fragmentation enable 0x01 to disable set
+# to 0x00
+NXP_I2C_FRAGMENTATION_ENABLED=0x00
+
+###############################################################################
+# Core configuration settings
+NXP_CORE_CONF={ 20, 02, 31, 0F,
+        85, 01, 01,
+        28, 01, 00,
+        21, 01, 00,
+        30, 01, 08,
+        31, 01, 03,
+        32, 01, 60,
+        38, 01, 01,
+        33, 04, 01, 02, 03, 04,
+        54, 01, 06,
+        50, 01, 02,
+        5B, 01, 00,
+        80, 01, 01,
+        81, 01, 01,
+        82, 01, 0E,
+        18, 01, 01
+        }
+
+###############################################################################
+# Mifare Classic Key settings
+#NXP_CORE_MFCKEY_SETTING={20, 02, 25,04, A0, 51, 06, A0, A1, A2, A3, A4, A5,
+#                                     A0, 52, 06, D3, F7, D3, F7, D3, F7,
+#                                     A0, 53, 06, FF, FF, FF, FF, FF, FF,
+#                                     A0, 54, 06, 00, 00, 00, 00, 00, 00}
+
+###############################################################################
+# Default SE Options
+# No secure element 0x00
+# eSE               0x01
+# UICC              0x02
+# UICC2             0x04
+NXP_DEFAULT_SE=0x07
+
+###############################################################################
+#Enable SWP full power mode when phone is power off
+NXP_SWP_FULL_PWR_ON=0x00
+
+###############################################################################
+#### Select the CHIP ####
+#PN547C2            0x01
+#PN65T              0x02
+#PN548AD            0x03
+#PN66T              0x04
+#PN551              0x05
+#PN67T              0x06
+#PN553              0x07
+#PN80T              0x08
+NXP_NFC_CHIP=0x08
+
+###############################################################################
+# CE when Screen state is locked
+# This setting is for DEFAULT_AID_ROUTE,
+# DEFAULT_DESFIRE_ROUTE and DEFAULT_MIFARE_CLT_ROUTE
+# Disable           0x00
+# Enable            0x01
+NXP_CE_ROUTE_STRICT_DISABLE=0x01
+
+###############################################################################
+#Timeout in secs to get NFCEE Discover notification
+NXP_DEFAULT_NFCEE_DISC_TIMEOUT=20
+
+###############################################################################
+NXP_DEFAULT_NFCEE_TIMEOUT=20
+
+###############################################################################
+#Timeout in secs
+NXP_SWP_RD_START_TIMEOUT=0x0A
+
+###############################################################################
+#Timeout in secs
+NXP_SWP_RD_TAG_OP_TIMEOUT=0x01
+
+###############################################################################
+#Set the default AID route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_AID_ROUTE=0x00
+
+###############################################################################
+#Set the Mifare Desfire route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_DESFIRE_ROUTE=0x02
+
+###############################################################################
+#Set the Mifare CLT route Location :
+#This settings will be used when application does not set this parameter
+# host  0x00
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_MIFARE_CLT_ROUTE=0x02
+
+###############################################################################
+#Set the Felica CLT route Location :
+#This settings will be used when application does not set this parameter
+# eSE   0x01
+# UICC  0x02
+# UICC2 0x03
+DEFAULT_FELICA_CLT_ROUTE=0x01
+
+###############################################################################
+#Set the default AID Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_AID_PWR_STATE=0x19
+
+###############################################################################
+#Set the Mifare Desfire Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_DESFIRE_PWR_STATE=0x1B
+
+###############################################################################
+#Set the Mifare CLT Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_MIFARE_CLT_PWR_STATE=0x1B
+
+###############################################################################
+#Set the Felica CLT Power state :
+#This settings will be used when application does not set this parameter
+# bit pos 0 = Switch On
+# bit pos 1 = Switch Off
+# bit pos 2 = Battery Off
+# bit pos 3 = Screen Lock
+# bit pos 4 = Screen Off
+DEFAULT_FELICA_CLT_PWR_STATE=0x1B
+
+###############################################################################
+# AID Matching platform options
+# AID_MATCHING_L 0x01
+# AID_MATCHING_K 0x02
+AID_MATCHING_PLATFORM=0x01
+
+###############################################################################
+# P61 interface options
+# NFC 0x01
+# SPI 0x02
+NXP_P61_LS_DEFAULT_INTERFACE=0x01
+
+###############################################################################
+# P61 LTSM interface options
+# NFC 0x01
+# SPI 0x02
+NXP_P61_LTSM_DEFAULT_INTERFACE=0x01
+
+###############################################################################
+#CHINA_TIANJIN_RF_SETTING
+#Enable  0x01
+#Disable  0x00
+NXP_CHINA_TIANJIN_RF_ENABLED=0x01
+
+###############################################################################
+#SWP_SWITCH_TIMEOUT_SETTING
+# Allowed range of swp timeout setting is 0x00 to 0x3C [0 - 60].
+# Timeout in milliseconds, for example
+# No Timeout  0x00
+# 10 millisecond timeout 0x0A
+NXP_SWP_SWITCH_TIMEOUT=0x0A
+
+###############################################################################
+# P61 interface options for JCOP Download
+# NFC 0x01
+# SPI 0x02
+NXP_P61_JCOP_DEFAULT_INTERFACE=0x01
+
+###############################################################################
+# P61 JCOP OS download  options
+# FRAMEWORK API BY APPLICATION 0x00
+# AT BOOT_TIME 0x01
+NXP_JCOPDL_AT_BOOT_ENABLE=0x00
+
+###############################################################################
+# Loader service version
+# NFC service checks for LS version 2.0 or 2.1
+# LS2.0 0x20
+# LS2.1 0x21
+# LS2.2 0x22
+# AT NFC service intialization
+NXP_LOADER_SERVICE_VERSION=0x22
+
+###############################################################################
+#Timeout value  in milliseconds for NFCC standby mode.The range is between 5000
+#msec to 20000 msec and zero is to disable.
+NXP_NFCC_STANDBY_TIMEOUT=20000
+
+###############################################################################
+#Dynamic RSSI feature enable
+# Disable           0x00
+# Enable            0x01
+NXP_AGC_DEBUG_ENABLE=0x00
+
+###############################################################################
+#Virtual Mode ESE and Wired Mode ongoing delay Wired Mode
+# For Technology routing to ESE Technology Mask = 4
+# For ISO-DEP Protocol routing to ESE Mask      = 2
+# It can also take TECH|PROTO    = 6
+# To ignore the delay set mask to = 0
+NXP_ESE_WIRED_PRT_MASK=0x00
+
+###############################################################################
+#Virtual Mode UICC and Wired Mode  ongoing delay Wired Mode
+#For Technology routing to UICC Technology Mask = 4
+#For ISO-DEP Protocol routing to UICC set Mask  = 2
+#For Select AID Routing to UICC       set Mask  = 1
+#It can also take values TECH|PROTO|SELECT_AID  = 7 , 6 , 5 ,3 .To ignore delay
+#set mask = 0
+NXP_UICC_WIRED_PRT_MASK=0x00
+
+################################################################################
+#RF field true delay Wired Mode
+# delay wired mode = 1
+# allow wired mode = 0
+NXP_WIRED_MODE_RF_FIELD_ENABLE=0x00
+
+###############################################################################
+#Config to allow adding aids
+#NFC on/off is required after this config
+#1 = enabling adding aid  to NFCC routing table.
+#0 = disabling adding aid to NFCC routing table.
+NXP_ENABLE_ADD_AID=0x01
+
+###############################################################################
+# JCOP-3.3 continuous process timeout in msec and value should be in Hexadecimal
+# JCOP CP TIMEOUT
+NXP_CP_TIMEOUT={00, 77}
+
+###############################################################################
+# Enable/Disable checking default proto SE Id
+# Disable           0x00
+# Enable            0x01
+NXP_CHECK_DEFAULT_PROTO_SE_ID=0x01
+
+###############################################################################
+#NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE
+#Enable/Disable block number checks for china transit use case
+#Enable  0x01
+#Disable  0x00
+NXP_CN_TRANSIT_BLK_NUM_CHECK_ENABLE=0x01
+
+###############################################################################
+# Wired mode resume timeout vaule in wired mode resume feature enable
+# DWP resume time out in ms( 4 bytes hex value and LSB first)
+#example 1000 = 0x03E8
+#exmaple 2000 = 0x07D0
+#example 500 = 0x01F4
+NXP_WIREDMODE_RESUME_TIMEOUT={E8,03,00,00}
+###############################################################################
+# Power to eSE is controlled by DH or PMU depending on following configurations
+#define DH_PWR_CONTROL         1
+#define PMU_PWR_CONTROL        2
+NXP_ESE_POWER_DH_CONTROL=1
+
+###############################################################################
+# Timeout value in milliseconds for wired mode resume after RF field event timeout
+NXP_NFCC_RF_FIELD_EVENT_TIMEOUT=3000
+
+###############################################################################
+# NXP PMU Support configuration is sent if PMU_PWR_CONTROL is configured
+# External PMU available in phone ON and phone OFF case if NXP_ESE_POWER_EXT_PMU=1
+# External PMU available only in phone ON case if NXP_ESE_POWER_EXT_PMU=2
+NXP_ESE_POWER_EXT_PMU=2
+
+###############################################################################
+# Whether to allow wired mode in desfire and mifare CLT
+# Disable           0x00
+# Enable            0x01
+NXP_ALLOW_WIRED_IN_MIFARE_DESFIRE_CLT=0x00
+
+###############################################################################
+# Restrict routing to first matched rule only.
+# Blacklist enable   0x01
+# Blacklist disable  0x00
+NXP_PROP_BLACKLIST_ROUTING=0x00
+
+###############################################################################
+# Send DWP interface reset command as part of SE open
+# Disable           0x00
+# Enable            0x01
+NXP_DWP_INTF_RESET_ENABLE=0x01
+
+###############################################################################
+# Timeout value in milliseconds for JCOP OS download to complete
+OS_DOWNLOAD_TIMEOUT_VALUE=60000
+
+###############################################################################
+# Timeout value in milliseconds to send response for Felica command received
+NXP_HCEF_CMD_RSP_TIMEOUT_VALUE=5000
+
+###############################################################################
\ No newline at end of file