summaryrefslogtreecommitdiffstats
path: root/common/arm/ihevc_inter_pred_chroma_vert_w16inp_w16out.s
blob: 0c2ffbdd2cc7a679ba0ef1bd97528f961471729e (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
@/*****************************************************************************
@*
@* Copyright (C) 2012 Ittiam Systems Pvt Ltd, Bangalore
@*
@* Licensed under the Apache License, Version 2.0 (the "License");
@* you may not use this file except in compliance with the License.
@* You may obtain a copy of the License at:
@*
@* http://www.apache.org/licenses/LICENSE-2.0
@*
@* Unless required by applicable law or agreed to in writing, software
@* distributed under the License is distributed on an "AS IS" BASIS,
@* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
@* See the License for the specific language governing permissions and
@* limitations under the License.
@*
@*****************************************************************************/
@/**
@*******************************************************************************
@* @file
@*  ihevc_inter_pred_chroma_vert_neon_w16inp_w16out_neon.s
@*
@* @brief
@*  contains function definitions for inter prediction  interpolation.
@* functions are coded using neon  intrinsics and can be compiled using

@* rvct
@*
@* @author
@*  yogeswaran rs / parthiban
@*
@* @par list of functions:
@*
@*
@* @remarks
@*  none
@*
@*******************************************************************************
@*/
@/**
@/**
@*******************************************************************************
@*
@* @brief
@*    chroma interprediction filter for 16bit vertical input and output.
@*
@* @par description:
@*    applies a vertical filter with coefficients pointed to  by 'pi1_coeff' to
@*    the elements pointed by 'pu1_src' and  writes to the location pointed by
@*    'pu1_dst'  input is 16 bits  the filter output is downshifted by 6 and
@*    8192 is  subtracted to store it as a 16 bit number  the output is used as
@*    a input to weighted prediction   assumptions : the function is optimized
@*    considering the fact width and  height are multiple of 2.
@*
@* @param[in] pi2_src
@*  word16 pointer to the source
@*
@* @param[out] pi2_dst
@*  word16 pointer to the destination
@*
@* @param[in] src_strd
@*  integer source stride
@*
@* @param[in] dst_strd
@*  integer destination stride
@*
@* @param[in] pi1_coeff
@*  word8 pointer to the filter coefficients
@*
@* @param[in] ht
@*  integer height of the array
@*
@* @param[in] wd
@*  integer width of the array
@*
@* @returns
@*
@* @remarks
@*  none
@*
@*******************************************************************************
@*/
@void ihevc_inter_pred_chroma_vert_w16inp_w16out(word16 *pi2_src,
@                                                 word16 *pi2_dst,
@                                                 word32 src_strd,
@                                                 word32 dst_strd,
@                                                 word8 *pi1_coeff,
@                                                 word32 ht,
@                                                 word32 wd)
@**************variables vs registers*****************************************
@r0 => *pu1_src
@r1 => *pi2_dst
@r2 =>  src_strd
@r3 =>  dst_strd

.equ    coeff_offset,   104
.equ    ht_offset,      108
.equ    wd_offset,      112

.text
.align 4




.globl ihevc_inter_pred_chroma_vert_w16inp_w16out_a9q

.type ihevc_inter_pred_chroma_vert_w16inp_w16out_a9q, %function

ihevc_inter_pred_chroma_vert_w16inp_w16out_a9q:

    stmfd       sp!, {r4-r12, r14}          @stack stores the values of the arguments
    vpush        {d8 - d15}

    ldr         r4, [sp,#coeff_offset]                @loads pi1_coeff
    ldr         r6, [sp,#wd_offset]                @wd
    lsl         r2,r2,#1                    @src_strd = 2* src_strd
    ldr         r5,[sp,#ht_offset]                 @loads ht
    vld1.8      {d0},[r4]                   @loads pi1_coeff
    sub         r4,r0,r2                    @pu1_src - src_strd
    vmovl.s8    q0,d0                       @long the value

    tst         r6,#3                       @checks wd  == 2
    vdup.16     d12,d0[0]                   @coeff_0
    vdup.16     d13,d0[1]                   @coeff_1
    vdup.16     d14,d0[2]                   @coeff_2
    vdup.16     d15,d0[3]                   @coeff_3

    bgt         core_loop_ht_2              @jumps to loop handles wd 2

    tst         r5,#3                       @checks ht == mul of 4
    beq         core_loop_ht_4              @jumps to loop handles ht mul of 4

core_loop_ht_2:
    lsl         r7,r2,#1                    @2*src_strd
    lsl         r3,r3,#1                    @2*dst_strd
    lsl         r9,r6,#2                    @4*wd
    sub         r6,r3,r6,lsl #1             @2*dst_strd - 2*wd
    sub         r8,r7,r9                    @2*src_strd - 4*wd
    mov         r12,r9                      @4wd

inner_loop_ht_2:
    add         r0,r4,r2                    @increments pi2_src
    vld1.16     {d0},[r4]!                  @loads pu1_src
    vmull.s16   q0,d0,d12                   @vmull_s16(src_tmp1, coeff_0)
    subs        r12,r12,#8                  @2wd + 8
    vld1.16     {d2},[r0],r2                @loads pi2_src
    vmull.s16   q4,d2,d12                   @vmull_s16(src_tmp2, coeff_0)
    vld1.16     {d3},[r0],r2                @loads pi2_src
    vmlal.s16   q0,d2,d13
    vld1.16     {d6},[r0],r2
    vmlal.s16   q4,d3,d13
    vld1.16     {d2},[r0]
    add         r7,r1,r3                    @pu1_dst + dst_strd
    vmlal.s16   q0,d3,d14
    vmlal.s16   q4,d6,d14
    vmlal.s16   q0,d6,d15
    vmlal.s16   q4,d2,d15
    vqshrn.s32  d0,q0,#6                    @right shift
    vqshrn.s32  d30,q4,#6                   @right shift
    vst1.32     {d0},[r1]!                  @stores the loaded value
    vst1.32     {d30},[r7]                  @stores the loaded value
    bgt         inner_loop_ht_2             @inner loop -again

    @inner loop ends
    subs        r5,r5,#2                    @increments ht
    add         r1,r1,r6,lsl #1             @pu1_dst += 2*dst_strd - 2*wd
    mov         r12,r9                      @4wd
    add         r4,r4,r8                    @pi1_src_tmp1 += 2*src_strd - 4*wd
    bgt         inner_loop_ht_2             @loop again

    b           end_loops                   @jumps to end

core_loop_ht_4:
    lsl         r7,r2,#2                    @2*src_strd
    lsl         r10,r3,#2                   @2*dst_strd
    mov         r11,r6,lsr #1               @divide by 2
    sub         lr,r10,r6,lsl #1            @2*dst_strd - 2*wd
    sub         r8,r7,r6,lsl #2             @2*src_strd - 4*wd

    mul         r12,r5,r11                  @multiply height by width
    sub         r12,#4                      @subtract by one for epilog
    mov         r11,r6,lsl #1               @2*wd
    lsl         r3,r3,#1                    @2*dst_strd

prolog:
    add         r0,r4,r2                    @increments pi2_src
    vld1.16     {d0},[r4]!                  @loads pu1_src
    vld1.16     {d1},[r0],r2                @loads pi2_src
    subs        r11,r11,#4
    vld1.16     {d2},[r0],r2                @loads pi2_src
    vmull.s16   q15,d0,d12                  @vmull_s16(src_tmp1, coeff_0)
    vld1.16     {d3},[r0],r2
    vmlal.s16   q15,d1,d13
    vmlal.s16   q15,d2,d14
    add         r9,r1,r3                    @pu1_dst + dst_strd
    vmlal.s16   q15,d3,d15

    vld1.16     {d4},[r0],r2
    vmull.s16   q14,d1,d12                  @vmull_s16(src_tmp2, coeff_0)
    addle       r4,r4,r8
    movle       r11,r6,lsl #1
    vmlal.s16   q14,d2,d13
    vmlal.s16   q14,d3,d14
    vld1.s16    {d5},[r0],r2
    vmlal.s16   q14,d4,d15

    vqshrn.s32  d30,q15,#6                  @right shift

    vld1.s16    {d6},[r0],r2
    vmull.s16   q13,d2,d12                  @vmull_s16(src_tmp2, coeff_0)
    vmlal.s16   q13,d3,d13
    vmlal.s16   q13,d4,d14
    add         r0,r4,r2
    vld1.16     {d0},[r4]!                  @loads pu1_src
    vmlal.s16   q13,d5,d15

    vqshrn.s32  d28,q14,#6                  @right shift

    vld1.16     {d1},[r0],r2                @loads pi2_src
    vmull.s16   q12,d3,d12                  @vmull_s16(src_tmp2, coeff_0)
    vst1.32     {d30},[r1]!                 @stores the loaded value
    vmlal.s16   q12,d4,d13
    vld1.16     {d2},[r0],r2                @loads pi2_src
    vmlal.s16   q12,d5,d14
    vld1.16     {d3},[r0],r2
    vmlal.s16   q12,d6,d15
    addle       r1,r1,lr,lsl #1

    vqshrn.s32  d26,q13,#6                  @right shift
    subs        r12,r12,#4

    beq         epilog                      @jumps to epilog

kernel_4:
    vmull.s16   q15,d0,d12                  @vmull_s16(src_tmp1, coeff_0)
    subs        r11,r11,#4
    vmlal.s16   q15,d1,d13
    vst1.32     {d28},[r9],r3               @stores the loaded value
    vmlal.s16   q15,d2,d14
    vmlal.s16   q15,d3,d15

    vqshrn.s32  d24,q12,#6                  @right shift

    vld1.16     {d4},[r0],r2
    vmull.s16   q14,d1,d12                  @vmull_s16(src_tmp2, coeff_0)
    vmlal.s16   q14,d2,d13
    vmlal.s16   q14,d3,d14
    vmlal.s16   q14,d4,d15
    vst1.32     {d26},[r9],r3               @stores the loaded value
    addle       r4,r4,r8
    movle       r11,r6,lsl #1

    vqshrn.s32  d30,q15,#6                  @right shift

    vld1.s16    {d5},[r0],r2
    vmull.s16   q13,d2,d12                  @vmull_s16(src_tmp2, coeff_0)
    vld1.s16    {d6},[r0],r2
    vmlal.s16   q13,d3,d13
    vst1.32     {d24},[r9]                  @stores the loaded value
    add         r0,r4,r2
    vmlal.s16   q13,d4,d14
    vld1.16     {d0},[r4]!                  @loads pu1_src
    vmlal.s16   q13,d5,d15

    vqshrn.s32  d28,q14,#6                  @right shift

    vld1.16     {d1},[r0],r2                @loads pi2_src
    vmull.s16   q12,d3,d12                  @vmull_s16(src_tmp2, coeff_0)
    vld1.16     {d2},[r0],r2                @loads pi2_src
    vmlal.s16   q12,d4,d13
    add         r9,r1,r3                    @pu1_dst + dst_strd
    vld1.16     {d3},[r0],r2
    vmlal.s16   q12,d5,d14

    vst1.32     {d30},[r1]!                 @stores the loaded value
    vmlal.s16   q12,d6,d15

    vqshrn.s32  d26,q13,#6                  @right shift
    addle       r1,r1,lr,lsl #1

    subs        r12,r12,#4

    bgt         kernel_4                    @jumps to kernel_4

epilog:
    vmull.s16   q15,d0,d12                  @vmull_s16(src_tmp1, coeff_0)
    vst1.32     {d28},[r9],r3               @stores the loaded value
    vmlal.s16   q15,d1,d13
    vmlal.s16   q15,d2,d14
    vmlal.s16   q15,d3,d15

    vqshrn.s32  d24,q12,#6                  @right shift

    vmull.s16   q14,d1,d12                  @vmull_s16(src_tmp2, coeff_0)
    vld1.16     {d4},[r0],r2
    vmlal.s16   q14,d2,d13
    vst1.32     {d26},[r9],r3               @stores the loaded value
    vmlal.s16   q14,d3,d14
    vmlal.s16   q14,d4,d15

    vqshrn.s32  d30,q15,#6                  @right shift

    vmull.s16   q13,d2,d12                  @vmull_s16(src_tmp2, coeff_0)
    vld1.s16    {d5},[r0],r2
    vmlal.s16   q13,d3,d13
    vmlal.s16   q13,d4,d14
    vmlal.s16   q13,d5,d15

    vqshrn.s32  d28,q14,#6                  @right shift

    vst1.32     {d24},[r9]                  @stores the loaded value
    vmull.s16   q12,d3,d12                  @vmull_s16(src_tmp2, coeff_0)
    vmlal.s16   q12,d4,d13
    add         r9,r1,r3                    @pu1_dst + dst_strd
    vld1.s16    {d6},[r0],r2
    vmlal.s16   q12,d5,d14
    vmlal.s16   q12,d6,d15
    vst1.32     {d30},[r1]!                 @stores the loaded value

    vqshrn.s32  d26,q13,#6                  @right shift

    vst1.32     {d28},[r9],r3               @stores the loaded value

    vqshrn.s32  d24,q12,#6                  @right shift
    vst1.32     {d26},[r9],r3               @stores the loaded value

    vst1.32     {d24},[r9]                  @stores the loaded value

end_loops:
    vpop         {d8 - d15}
    ldmfd       sp!,{r4-r12,r15}            @reload the registers from sp