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* Dalvik is dead, long live Dalvik!Brian Carlstrom2014-08-0539-15689/+0
| | | | | | | | | | | | | | | | | | | | | | | croot cd dalvik repo start dalvik-is-dead-long-live-dalvik . repo sync -c . git rm -r README.txt git rm -r dexopt git rm -r tools/deadcode.py git rm -r tools/dex-preopt git rm -r tools/dexcheck git rm -r tools/gdbjithelper git rm -r unit-tests git rm -r vm git checkout HEAD vm/Common.h (needed by libdex) git checkout HEAD vm/DalvikVersion.h (needed by libdex) git checkout HEAD vm/Profile.h (needed by dmtracedump) git add Android.mk (after removing vm, dexopt, and unit-tests references) git commit -a -m 'Dalvik is dead, long live Dalvik!' Bug: 14298175 Change-Id: I9dd13053677629d13496d4238af4374452cda415
* Move dalvik off cacheflush so we can deprecate it.Elliott Hughes2014-02-122-11/+5
| | | | | Bug: 12965705 Change-Id: I805428e3103ff578d048ecbbc6ae30c0ead19ef9
* Initialize callTgt variableBernhard Rosenkränzer2013-12-311-1/+1
| | | | | | | | | | | | This silcences a clang build failure: dalvik/vm/compiler/codegen/arm/armv7-a-neon/../CodegenDriver.cpp:904:41: error: variable 'callTgt' is uninitialized when used here [-Werror,-Wuninitialized] LOAD_FUNC_ADDR(cUnit, r2, (int) callTgt); ^~~~~~~ Change-Id: Ic5b3bb492f19b842743bf7d6214c89301ff524e7 Signed-off-by: Bernhard Rosenkränzer <Bernhard.Rosenkranzer@linaro.org>
* Dalvik: Add hardware vfp support for OP_LONG_TO_DOUBLE in JITSerban Constantinescu2013-12-193-0/+43
| | | | | | | | | The following patch adds hardware vfp support for OP_LONG_TO_DOUBLE in the JIT. Previously this opcode was implemented using one of gcc's builtin helpers. Change-Id: I3c88b2a527dea99dcefdb34be6695e75993da73e Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Dalvik: Add sdiv support in the JITSerban Constantinescu2013-12-194-2/+88
| | | | | | | | | | | | | | | | | | | | This patch adds hardware divide support in the JIT side of dalvik. This operation is supported on new armv7 cpus such as A15 or A7. The following opcodes are enabled and will generate code based using SDIV instruction: OP_DIV_INT OP_DIV_INT_2ADDR OP_REM_INT OP_REM_INT_2ADDR OP_DIV_INT_LIT16 OP_DIV_INT_LIT8 OP_REM_INT_LIT16 OP_REM_INT_LIT8 Change-Id: I2b2f9f337f13b5c794df951c4929b6ca0ad583c4 Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* Merge commit 'b75a263239ff48c87b826f5d62a53c0efd22b507' into HEADThe Android Open Source Project2013-11-225-4/+30
|\ | | | | | | Change-Id: Ia37a6c18e09e6bbfab4beadc5ed86f92b766fe21
| * am bbd903de: am 28702c58: am ae2fb913: Merge "JIT: Use rsb and shift in easy ↵Elliott Hughes2013-06-175-4/+23
| |\ | | | | | | | | | | | | | | | | | | multiply." * commit 'bbd903dec7c25859849fa447aaeef365f20440d4': JIT: Use rsb and shift in easy multiply.
| * \ am 15139109: am 6529809b: Merge "JIT: Allow use of cbz/cbnz for conditional ↵Elliott Hughes2013-06-131-4/+2
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | branch gen." * commit '151391097e94585d4dd062098438e5c894b98d6d': JIT: Allow use of cbz/cbnz for conditional branch gen.
| * \ \ am de241376: am 91027c67: Merge "Remove unused compiler templates for armv7-a*"Elliott Hughes2013-06-054-6/+6
| |\ \ \ | | | | | | | | | | | | | | | | | | | | * commit 'de2413762e3626039cadf270479f30dea6307fe8': Remove unused compiler templates for armv7-a*
| * | | | JIT tuning; set cache size on command linebuzbee2013-05-235-4/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The tuning knobs for triggering trace compilation for the JIT had not been revisited for several years. In that time, the working set of some applications have significantly increased, leading to frequent cache overlows & flushes. This CL adds the ability to set the maximum size of the JIT's cache on the command line, and we expect to use different settings depending on device configuration (rule of thumb: 1K for each 1M for system RAM, with 2M limit). Additionally, the trace compilation trigger has been tightened to limit the compilation of cold traces. Change-Id: Ice22c5d9d46a93e465c57dd83f50ca3912f1672e
| * | | | am 6e2d46fd: am 03a938bc: Merge "Fix -Xjitthreshold (for real this time)."Elliott Hughes2013-03-014-4/+4
| |\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | * commit '6e2d46fd7488331181502a878959336966ac3776': Fix -Xjitthreshold (for real this time).
| * \ \ \ \ am 7f77254e: Merge "Fix -Xjitthreshold."Elliott Hughes2013-02-264-4/+12
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * commit '7f77254e7ba273c18bd77313c6074029d3f79f79': Fix -Xjitthreshold.
| * | | | | | Fix JIT bug related to immediate doublesbuzbee2013-02-111-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change 256211 (JIT: Performance Fix for const doubles) introduced a defect that can cause the JIT to use the wrong floating point double constant in traces in which the following conditions hold: o Two (or more) different 64-bit floating point constants are used. o The physical register holding the first constant is still live at the time the second constant is used. o The low 32 bits of the two constants are identical. In this situation, the load/copy optimization pass will incorrectly determine that the two constants are the same, delete the load of the second constant and re-use the first constant value. Note: this problem only occurs with 64-bit floating point literals. 64-bit long literals are unaffected. This CL works around the problem, and a subsequent CL will rework disambiguation of 64-bit immediates in a somewhat cleaner fashion. Change-Id: I33baf78402bab58d9b0ca46189f26491c2b2a751
| * | | | | | JIT: Performance fix for const doublesbuzbee2012-11-303-5/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some recent Arm processors take a performance hit when creating a floating point double by loading it as a pair of singles. Legacy code to support soft floating point doubles as a pair of core registers loaded double immediates in this way. With the CL, we handle double immediates as a single unit. Change-Id: I91aca9da6d4b38e180479dd8f75c82dbc7b4a526
* | | | | | | Dalvik: DMB Optimisations for TracingJITDavid Butcher2013-11-122-9/+9
| |_|_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Makes DMB domain ISH or ISHST instead of the implicit System. ISH (Inner Shareable) should be sufficient for all cores/clusters, but is not sufficient for GPU or other memory-mapped peripherals Change-Id: Id159228daba97bc3692d2eb1ee2786bae2ee34a7
* | | | | | JIT: Use rsb and shift in easy multiply.Anders O Nilsson2013-06-145-4/+23
| |_|_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For easy multiplication using reverse subtract (when lit is 2^n-1) use the barrel shifter for rsb. This improves arithmetic performance for code executing in Dalvik. E.g String.hashCode. Change-Id: Ifb086dcec344b30fd3e392ac21d508b43e820cdc Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | | | Merge "JIT: Allow use of cbz/cbnz for conditional branch gen."Elliott Hughes2013-06-131-4/+2
|\ \ \ \ \ | |_|_|_|/ |/| | | |
| * | | | JIT: Allow use of cbz/cbnz for conditional branch gen.Anders O Nilsson2013-04-181-4/+2
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimize conditional branch generation when comparing with zero for ARM JIT. When possible use cbz/cbnz instead of cmp+beq/cmp+bne. This improves performance for usecases involving code execution in Dalvik. Change-Id: I8f7c44c87eb73d4da00a48fd86220a62cb0515f5 Signed-off-by: Patrik Ryd <patrik.ryd@stericsson.com>
* | | | Merge "Remove unused compiler templates for armv7-a*"Elliott Hughes2013-06-054-6/+6
|\ \ \ \
| * | | | Remove unused compiler templates for armv7-a*You Kim2013-05-174-6/+6
| |/ / / | | | | | | | | | | | | Change-Id: I68e344c2f2689347d6eeb943030b7263a55cd0bd
* / / / Fix JIT bug related to immediate doublesbuzbee2013-04-261-1/+2
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change 256211 (JIT: Performance Fix for const doubles) introduced a defect that can cause the JIT to use the wrong floating point double constant in traces in which the following conditions hold: o Two (or more) different 64-bit floating point constants are used. o The physical register holding the first constant is still live at the time the second constant is used. o The low 32 bits of the two constants are identical. In this situation, the load/copy optimization pass will incorrectly determine that the two constants are the same, delete the load of the second constant and re-use the first constant value. Note: this problem only occurs with 64-bit floating point literals. 64-bit long literals are unaffected. This CL works around the problem, and a subsequent CL will rework disambiguation of 64-bit immediates in a somewhat cleaner fashion. (cherry-pick of c1757a6deab0ca0bfd42c38612d92b2f26c41dbe.) Change-Id: I795b4b753550d2745cbbdd83ae25f4a7088990f6
* | / Fix -Xjitthreshold (for real this time).Elliott Hughes2013-03-014-4/+4
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | My previous "fix" (c89d83e1c05979b68037ad15413fa4460a88e36f) had the conditions reversed, so you _had_ to use -Xjitthreshold to get a non-zero threshold, but when you did, you'd get the default instead of what you asked for! This was spotted by the jank tests. Bug: 8285558 Bug: https://code.google.com/p/android/issues/detail?id=52017 Change-Id: I28270f2573d46929eb10d30789fecf7d5a8cea75
* | Fix -Xjitthreshold.Elliott Hughes2013-02-254-4/+12
| | | | | | | | | | | | | | | | Previously, we'd always overwrite the user-supplied value because the architecture-specific default gets set so late. Bug: https://code.google.com/p/android/issues/detail?id=52017 Change-Id: I469bf9ce599820f5ce3dea346aa8f680deffb0c5
* | JIT: Performance fix for const doublesbuzbee2012-11-303-5/+65
|/ | | | | | | | | | | | | Some recent Arm processors take a performance hit when creating a floating point double by loading it as a pair of singles. Legacy code to support soft floating point doubles as a pair of core registers loaded double immediates in this way. With the CL, we handle double immediates as a single unit. (cherry-pick of c8129911e598ad0ca8d7b31012444ab6ce8bce45.) Change-Id: Ic1512e34bfd233a6f5ffd58ce843965adbbad875
* Don't disable inlining for ARM.Elliott Hughes2012-10-091-0/+10
| | | | | | | | | I think there was confusion here between method inlining and the method compiler. Just because the latter isn't yet functional doesn't mean we don't want the former for those targets that support it. Bug: 7179010 Change-Id: If0de856b93615f01dfc5e8977d5c97f550cec15f
* Use 0xde as the poison value after JIT code cache reset.Ben Cheng2012-09-171-2/+6
| | | | | | (cherry-pick of 60497bbcee68d98b2bdcb3fb64682b00d61b942d.) Change-Id: I4f8c1bac2ac3bdc1d931e91f3e2e8038fe4c2b5a
* Optimize those StrictMath routines that are identical to Math routines.Elliott Hughes2012-09-141-6/+16
| | | | | | | We can just use the existing Math intinsics. Bug: 7146208 Change-Id: I9e78d33cf65a5dcc5a7c0133e67bd9c3c1e43f23
* [X86] X86 trace JIT compiler supportDong-Yuan Chen2012-07-202-4/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a fully functional x86 trace JIT compiler for Dalvik VM. It is built on top of the existing x86 fast interpreter with bug fixes and needed extension to support trace JIT interface. The x86 trace JIT code generator was developed independent of the existing template-based code generator and thus does not share exactly the same infrastructure. Included in this patch are: * Deprecated and removed the x86-atom fast interpreter that is no longer functional since ICS. * Augmented x86 fast interpreter to provide interfaces for x86 trace JIT compiler. * Added x86 trace JIT code generator with full JDWP debugging support. * Method JIT and self-verification mode are not supported. The x86 code generator uses the x86 instruction encoder/decoder library from the Apache Harmony project. Additional wrapper extension and bug fixes were added to support the x86 trace JIT code generator. The x86 instruction encoder/decoder is embedded inside the x86 code generator under the libenc subdirectory. Change-Id: I241113681963a16c13a3562390813cbaaa6eedf0 Signed-off-by: Dong-Yuan Chen <dong-yuan.chen@intel.com> Signed-off-by: Yixin Shou <yixin.shou@intel.com> Signed-off-by: Johnnie Birch <johnnie.l.birch.jr@intel.com> Signed-off-by: Udayan <udayan.banerji@intel.com> Signed-off-by: Sushma Kyasaralli Thimmappa <sushma.kyasaralli.thimmappa@intel.com> Signed-off-by: Bijoy Jose <bijoy.a.jose@intel.com> Signed-off-by: Razvan A Lupusoru <razvan.a.lupusoru@intel.com> Signed-off-by: Tim Hartley <timothy.d.hartley@intel.com>
* Avoid sign extension in packed-switch.Elliott Hughes2012-07-172-14/+7
| | | | | | | | | | | | | | This code (at least in the ARM version) is trying to assign to r0 and r1 from C by returning a 64-bit result. The mistaken use of signed integers for pointers can lead to sign extension if the JIT code cache is at a sufficiently high address. Bug: 6799823 Bug: 6703991 (cherry-pick from 2d0c1c2dbe44458ebb199c47ce1047f266db5349.) Change-Id: I79e72228b60e195272d11899ac69bb4a76b7402f
* Missing zero-checks in JIT compilerMattias Petersson2012-07-101-1/+9
| | | | | | | | Zero-checks were not generated by the JIT compiler for some instructions. This caused crashes instead of the expected ArithmeticException. Change-Id: Ic8041741a7cccc1bd6b8c3c0723ba55a55af856b
* resolved conflicts for merge of 93a44a28 to jb-dev-plus-aospElliott Hughes2012-05-031-0/+7
|\ | | | | | | Change-Id: I9c1f2e37602bea86e70333d2b274665e99fcbd92
| * [MIPS] Dalvik fast interpreter support and JIT implementationRaghu Gandham2012-05-021-0/+7
| | | | | | | | | | | | | | | | Change-Id: I9bb4f6875b7061d3ffaee73f204026cb8ba3ed39 Signed-off-by: Raghu Gandham <raghu@mips.com> Signed-off-by: Chris Dearman <chris@mips.com> Signed-off-by: Douglas Leung <douglas@mips.com> Signed-off-by: Don Padgett <don@mips.com>
* | Fix an array out-of-bound read in the JIT compiler.Ben Cheng2012-04-131-4/+10
| | | | | | | | | | | | | | | | | | | | Without the fix the compiler is still safe since the offending memory access is a read, though the hoisted distance is non-deterministic. The easiest and safest fix is to unconditionally hoist a load when it can reach the scheduling barrier. BUG: 6300640 Change-Id: Ic83de6dd1e3f602bda6809bfe840db3a097a5176
* | Rename (IF_)LOGE(_IF) to (IF_)ALOGE(_IF) DO NOT MERGESteve Block2012-01-0812-53/+53
| | | | | | | | | | | | | | | | | | See https://android-git.corp.google.com/g/#/c/157220 Also fix an occurrence of LOGW missed in an earlier change. Bug: 5449033 Change-Id: I2e3b23839e6dcd09015d6402280e9300c75e3406
* | Remove unsupported experimental opcodes.Elliott Hughes2012-01-052-134/+41
| | | | | | | | | | | | | | External developers were starting to try to get themselves into trouble with this stuff... Change-Id: I2b03bfeaa8c98b6a994bc7924fc8dcf4e4d4f6cb
* | Rename (IF_)LOGD(_IF) to (IF_)ALOGD(_IF) DO NOT MERGESteve Block2012-01-034-54/+54
|/ | | | | | | See https://android-git.corp.google.com/g/156016 Bug: 5449033 Change-Id: Ic663376d1ad6a6cb14bf81405ad9afd247cf2f60
* Fix memory barriers (Issue 3338450)buzbee2011-09-271-1/+7
| | | | | | Add extra memory barrier on volatile stores. Change-Id: Id4a4750cdfc910eda2f0b44ead0af2a569b5735e
* Fix a use of uninitialized variable found by gcc-4.6. I don't think this is aDoug Kwan2011-06-261-1/+1
| | | | | | real problem as we will only see an undefined value if the list has no instructions other than NOPs. Change-Id: I055510831ca1c566e2daa2b4b2acbaa655fa735a
* Normalize the include guard style.Carl Shapiro2011-06-146-20/+20
| | | | | | | | | | An leading underscore followed by a capital letter is a reserved name space in C and C++. This change also moves any #include directives within the include guard in some of the compiler/codegen/arm header files. Change-Id: I9715e2c5301699d31886e61d0fe6e29483555a2a
* Use std::string rather than malloc/free for saneDirName.Elliott Hughes2011-06-072-2/+2
| | | | | | Also use std::vector instead of the cutils/array cruft. Change-Id: I273147335cafbac5d336955f53b0b29d015f0589
* Prefer printf format "%#x" over "0x%x".Dan Bornstein2011-05-264-16/+16
| | | | | | I exist to serve. Change-Id: I8e2880b20eefd466da8515d5b6b0c5cb75d56169
* Further conservation of newlines.Dan Bornstein2011-05-264-37/+37
| | | | | | Friends don't let friends end LOG() strings with newlines. Change-Id: I5a18c766c90c4ab5f03caa6acd601d34d91beb00
* am cf4a20cf: Interpreter/Debugger fix #4479968buzbee2011-05-252-4/+4
|\ | | | | | | | | * commit 'cf4a20cf0cbc53f03a5b16c7152bbb29907f7108': Interpreter/Debugger fix #4479968
| * Interpreter/Debugger fix #4479968buzbee2011-05-252-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This one was tricky to track down. The underlying problem arose with the consolidation of InterpState with Thread. Rather than having a state structure for each instance of the interpreter, we moved to a model that had a single thread-local struct shared by all interpreter instances running on that thread. A portion of interpreter state can't be shared - and thus was saved and restored on nested invocations of the interpreter. The bug here was that the storage for method return values was not included in the state that needed save/retore. In normal operation, it doesn't need to be saved - that storage isn't live across an invoke that could trigger a nested interpreter activation. However, when debugging, the debugger itself may hijack threads and create new interpreter instances for its own purposed - and there is a small window in which live retval can be trashed. The fix is simply to move retval into the InterpSave struct. Change-Id: Ib621824b799c5caa16fdfa8f5689a181159059df
* | am fe108f77: Fix a Thumb vs Thumb2 codegen bug.Ben Cheng2011-05-112-2/+62
|\| | | | | | | | | * commit 'fe108f779db4fb3bc720a92e69e58177983088c1': Fix a Thumb vs Thumb2 codegen bug.
| * Fix a Thumb vs Thumb2 codegen bug.Ben Cheng2011-05-112-2/+62
| | | | | | | | | | | | | | | | A Thumb2 pc-relative load is slipped into the codegen stream even though the selected platform is armv5te (eg the emulator). Bug: 4399358 Change-Id: I61dd6853cad6c82de43f384814c903dd9f3ae302
* | am 313d430d: Another single-stepping fix in JIT self-verification mode.Ben Cheng2011-05-111-2/+1
|\| | | | | | | | | * commit '313d430d5b3b96b45370ccddee52a6d88a799f35': Another single-stepping fix in JIT self-verification mode.
| * Another single-stepping fix in JIT self-verification mode.Ben Cheng2011-05-111-2/+1
| | | | | | | | | | | | | | | | | | | | The counted single stepping check should be based on the kSubModeCountedStep submode instead. Also since the NPC value is cleared when exceptions are thrown, we can single-step instructions that can throw as well. Change-Id: Idbc1307ae0956016ef76186aebc6e3b89b119d9d
* | Establish a subclass relationships among the field types.Carl Shapiro2011-05-061-5/+5
| | | | | | | | Change-Id: Id349b359489bb6b1bbb4ab78d29d85c0e6b33799
* | Establish a subclass relationship between ClassObject and Object.Carl Shapiro2011-05-064-11/+11
|/ | | | Change-Id: I9fb5d33f23ec7aeb2b9a3908d4125b34be0599ae
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