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-rw-r--r--vm/compiler/codegen/armv5te/Codegen.c6
-rw-r--r--vm/compiler/template/armv5te/footer.S9
-rw-r--r--vm/compiler/template/out/CompilerTemplateAsm-armv5te.S7
3 files changed, 15 insertions, 7 deletions
diff --git a/vm/compiler/codegen/armv5te/Codegen.c b/vm/compiler/codegen/armv5te/Codegen.c
index b4f7c739d..b272e4827 100644
--- a/vm/compiler/codegen/armv5te/Codegen.c
+++ b/vm/compiler/codegen/armv5te/Codegen.c
@@ -2861,7 +2861,8 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
*/
newLIR1(cUnit, ARMV5TE_16BIT_DATA, 0);
newLIR1(cUnit, ARMV5TE_16BIT_DATA, 0);
- cUnit->chainCellOffsetLIR = newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
+ cUnit->chainCellOffsetLIR =
+ (LIR *) newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
cUnit->headerSize = 6;
newLIR2(cUnit, ARMV5TE_MOV_RR_HL, r0, rpc & THUMB_REG_MASK);
newLIR2(cUnit, ARMV5TE_SUB_RI8, r0, 10);
@@ -2870,7 +2871,8 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit)
newLIR3(cUnit, ARMV5TE_STR_RRI5, r1, r0, 0);
} else {
/* Just reserve 2 bytes for the chain cell offset */
- cUnit->chainCellOffsetLIR = newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
+ cUnit->chainCellOffsetLIR =
+ (LIR *) newLIR1(cUnit, ARMV5TE_16BIT_DATA, CHAIN_CELL_OFFSET_TAG);
cUnit->headerSize = 2;
}
diff --git a/vm/compiler/template/armv5te/footer.S b/vm/compiler/template/armv5te/footer.S
index e961e298b..29073c37d 100644
--- a/vm/compiler/template/armv5te/footer.S
+++ b/vm/compiler/template/armv5te/footer.S
@@ -34,11 +34,12 @@
bne .LhandleException @ no, handle exception
bx r2
-/* FIXME - untested */
+/* NOTE - this path can be exercised if the JIT threshold is set to 5 */
.LhandleException:
- ldr rIBASE, .LdvmAsmInstructionStart
+ ldr r0, .LdvmMterpCommonExceptionThrown @ PIC way of getting &func
+ ldr rIBASE, .LdvmAsmInstructionStart @ same as above
ldr rPC, [r10, #offStackSaveArea_savedPc] @ reload rPC
- b dvmMterpCommonExceptionThrown
+ mov pc, r0 @ branch to dvmMterpCommonExceptionThrown
.align 2
.LdvmAsmInstructionStart:
@@ -47,6 +48,8 @@
.word dvmJitToInterpNoChain
.LdvmMterpStdBail:
.word dvmMterpStdBail
+.LdvmMterpCommonExceptionThrown:
+ .word dvmMterpCommonExceptionThrown
.L__aeabi_cdcmple:
.word __aeabi_cdcmple
.L__aeabi_cfcmple:
diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S b/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
index c1b47330f..083110002 100644
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv5te.S
@@ -1132,9 +1132,10 @@ dvmCompiler_TEMPLATE_CMPL_FLOAT_VFP:
/* FIXME - untested */
.LhandleException:
- ldr rIBASE, .LdvmAsmInstructionStart
+ ldr r0, .LdvmMterpCommonExceptionThrown @ PIC way of getting &func
+ ldr rIBASE, .LdvmAsmInstructionStart @ same as above
ldr rPC, [r10, #offStackSaveArea_savedPc] @ reload rPC
- b dvmMterpCommonExceptionThrown
+ mov pc, r0 @ branch to dvmMterpCommonExceptionThrown
.align 2
.LdvmAsmInstructionStart:
@@ -1143,6 +1144,8 @@ dvmCompiler_TEMPLATE_CMPL_FLOAT_VFP:
.word dvmJitToInterpNoChain
.LdvmMterpStdBail:
.word dvmMterpStdBail
+.LdvmMterpCommonExceptionThrown:
+ .word dvmMterpCommonExceptionThrown
.L__aeabi_cdcmple:
.word __aeabi_cdcmple
.L__aeabi_cfcmple: