Merge "Remove unused compiler templates for armv7-a*"

10 files changed, 10 insertions, 1004 deletions

diff --git a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.cpp b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.cpp
index 40ee04072..0b1e0cdeb 100644
--- a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.cpp
+++ b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.cpp
@@ -27,7 +27,7 @@ JitInstructionSetType dvmCompilerInstructionSet(void)
 
 /* First, declare dvmCompiler_TEMPLATE_XXX for each template */
 #define JIT_TEMPLATE(X) extern "C" void dvmCompiler_TEMPLATE_##X();
-#include "../../../template/armv5te-vfp/TemplateOpList.h"
+#include "../../../template/armv7-a-neon/TemplateOpList.h"
 #undef JIT_TEMPLATE
 
 /* Architecture-specific initializations and checks go here */
@@ -41,7 +41,7 @@ bool dvmCompilerArchVariantInit(void)
      */
 #define JIT_TEMPLATE(X) templateEntryOffsets[i++] = \
     (intptr_t) dvmCompiler_TEMPLATE_##X - (intptr_t) dvmCompilerTemplateStart;
-#include "../../../template/armv5te-vfp/TemplateOpList.h"
+#include "../../../template/armv7-a-neon/TemplateOpList.h"
 #undef JIT_TEMPLATE
 
     /* Target-specific configuration */
diff --git a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h
index 33e262cec..0cb82f654 100644
--- a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h
+++ b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h
@@ -20,7 +20,7 @@
 /* Create the TemplateOpcode enum */
 #define JIT_TEMPLATE(X) TEMPLATE_##X,
 typedef enum {
-#include "../../../template/armv5te-vfp/TemplateOpList.h"
+#include "../../../template/armv7-a-neon/TemplateOpList.h"
 /*
  * For example,
  *     TEMPLATE_CMP_LONG,
diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp b/vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp
index 40ee04072..c698f6267 100644
--- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp
+++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.cpp
@@ -27,7 +27,7 @@ JitInstructionSetType dvmCompilerInstructionSet(void)
 
 /* First, declare dvmCompiler_TEMPLATE_XXX for each template */
 #define JIT_TEMPLATE(X) extern "C" void dvmCompiler_TEMPLATE_##X();
-#include "../../../template/armv5te-vfp/TemplateOpList.h"
+#include "../../../template/armv7-a/TemplateOpList.h"
 #undef JIT_TEMPLATE
 
 /* Architecture-specific initializations and checks go here */
@@ -41,7 +41,7 @@ bool dvmCompilerArchVariantInit(void)
      */
 #define JIT_TEMPLATE(X) templateEntryOffsets[i++] = \
     (intptr_t) dvmCompiler_TEMPLATE_##X - (intptr_t) dvmCompilerTemplateStart;
-#include "../../../template/armv5te-vfp/TemplateOpList.h"
+#include "../../../template/armv7-a/TemplateOpList.h"
 #undef JIT_TEMPLATE
 
     /* Target-specific configuration */
diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.h b/vm/compiler/codegen/arm/armv7-a/ArchVariant.h
index b4f4eb7b7..8003f734f 100644
--- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.h
+++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.h
@@ -20,7 +20,7 @@
 /* Create the TemplateOpcode enum */
 #define JIT_TEMPLATE(X) TEMPLATE_##X,
 enum TemplateOpcode {
-#include "../../../template/armv5te-vfp/TemplateOpList.h"
+#include "../../../template/armv7-a/TemplateOpList.h"
 /*
  * For example,
  *     TEMPLATE_CMP_LONG,
diff --git a/vm/compiler/template/armv7-a-neon/TemplateOpList.h b/vm/compiler/template/armv7-a-neon/TemplateOpList.h
index 0365ba4d2..8d0f8d6f7 100644
--- a/vm/compiler/template/armv7-a-neon/TemplateOpList.h
+++ b/vm/compiler/template/armv7-a-neon/TemplateOpList.h
@@ -31,25 +31,6 @@ JIT_TEMPLATE(MUL_LONG)
 JIT_TEMPLATE(SHL_LONG)
 JIT_TEMPLATE(SHR_LONG)
 JIT_TEMPLATE(USHR_LONG)
-JIT_TEMPLATE(ADD_FLOAT_VFP)
-JIT_TEMPLATE(SUB_FLOAT_VFP)
-JIT_TEMPLATE(MUL_FLOAT_VFP)
-JIT_TEMPLATE(DIV_FLOAT_VFP)
-JIT_TEMPLATE(ADD_DOUBLE_VFP)
-JIT_TEMPLATE(SUB_DOUBLE_VFP)
-JIT_TEMPLATE(MUL_DOUBLE_VFP)
-JIT_TEMPLATE(DIV_DOUBLE_VFP)
-JIT_TEMPLATE(DOUBLE_TO_FLOAT_VFP)
-JIT_TEMPLATE(DOUBLE_TO_INT_VFP)
-JIT_TEMPLATE(FLOAT_TO_DOUBLE_VFP)
-JIT_TEMPLATE(FLOAT_TO_INT_VFP)
-JIT_TEMPLATE(INT_TO_DOUBLE_VFP)
-JIT_TEMPLATE(INT_TO_FLOAT_VFP)
-JIT_TEMPLATE(CMPG_DOUBLE_VFP)
-JIT_TEMPLATE(CMPL_DOUBLE_VFP)
-JIT_TEMPLATE(CMPG_FLOAT_VFP)
-JIT_TEMPLATE(CMPL_FLOAT_VFP)
-JIT_TEMPLATE(SQRT_DOUBLE_VFP)
 JIT_TEMPLATE(THROW_EXCEPTION_COMMON)
 JIT_TEMPLATE(MEM_OP_DECODE)
 JIT_TEMPLATE(STRING_COMPARETO)
diff --git a/vm/compiler/template/armv7-a/TemplateOpList.h b/vm/compiler/template/armv7-a/TemplateOpList.h
index 0365ba4d2..8d0f8d6f7 100644
--- a/vm/compiler/template/armv7-a/TemplateOpList.h
+++ b/vm/compiler/template/armv7-a/TemplateOpList.h
@@ -31,25 +31,6 @@ JIT_TEMPLATE(MUL_LONG)
 JIT_TEMPLATE(SHL_LONG)
 JIT_TEMPLATE(SHR_LONG)
 JIT_TEMPLATE(USHR_LONG)
-JIT_TEMPLATE(ADD_FLOAT_VFP)
-JIT_TEMPLATE(SUB_FLOAT_VFP)
-JIT_TEMPLATE(MUL_FLOAT_VFP)
-JIT_TEMPLATE(DIV_FLOAT_VFP)
-JIT_TEMPLATE(ADD_DOUBLE_VFP)
-JIT_TEMPLATE(SUB_DOUBLE_VFP)
-JIT_TEMPLATE(MUL_DOUBLE_VFP)
-JIT_TEMPLATE(DIV_DOUBLE_VFP)
-JIT_TEMPLATE(DOUBLE_TO_FLOAT_VFP)
-JIT_TEMPLATE(DOUBLE_TO_INT_VFP)
-JIT_TEMPLATE(FLOAT_TO_DOUBLE_VFP)
-JIT_TEMPLATE(FLOAT_TO_INT_VFP)
-JIT_TEMPLATE(INT_TO_DOUBLE_VFP)
-JIT_TEMPLATE(INT_TO_FLOAT_VFP)
-JIT_TEMPLATE(CMPG_DOUBLE_VFP)
-JIT_TEMPLATE(CMPL_DOUBLE_VFP)
-JIT_TEMPLATE(CMPG_FLOAT_VFP)
-JIT_TEMPLATE(CMPL_FLOAT_VFP)
-JIT_TEMPLATE(SQRT_DOUBLE_VFP)
 JIT_TEMPLATE(THROW_EXCEPTION_COMMON)
 JIT_TEMPLATE(MEM_OP_DECODE)
 JIT_TEMPLATE(STRING_COMPARETO)
diff --git a/vm/compiler/template/config-armv7-a b/vm/compiler/template/config-armv7-a
index 9d66e55df..6bc2e6de8 100644
--- a/vm/compiler/template/config-armv7-a
+++ b/vm/compiler/template/config-armv7-a
@@ -31,7 +31,7 @@ import armv5te-vfp/platform.S
 #import c/opcommon.c
 
 # opcode list; argument to op-start is default directory
-op-start armv5te-vfp
+op-start armv7-a
     op TEMPLATE_CMP_LONG armv5te
     op TEMPLATE_INVOKE_METHOD_CHAIN armv5te
     op TEMPLATE_INVOKE_METHOD_NATIVE armv5te
@@ -54,6 +54,7 @@ op-start armv5te-vfp
     op TEMPLATE_INVOKE_METHOD_NATIVE_PROF armv5te
     op TEMPLATE_INVOKE_METHOD_NO_OPT_PROF armv5te
     op TEMPLATE_RETURN_PROF armv5te
+    op TEMPLATE_MEM_OP_DECODE armv5te-vfp
 op-end
 
 # "helper" code for C; include if you use any of the C stubs (this generates
diff --git a/vm/compiler/template/config-armv7-a-neon b/vm/compiler/template/config-armv7-a-neon
index 9d66e55df..72bdf8694 100644
--- a/vm/compiler/template/config-armv7-a-neon
+++ b/vm/compiler/template/config-armv7-a-neon
@@ -31,7 +31,7 @@ import armv5te-vfp/platform.S
 #import c/opcommon.c
 
 # opcode list; argument to op-start is default directory
-op-start armv5te-vfp
+op-start armv7-a-neon
     op TEMPLATE_CMP_LONG armv5te
     op TEMPLATE_INVOKE_METHOD_CHAIN armv5te
     op TEMPLATE_INVOKE_METHOD_NATIVE armv5te
@@ -54,6 +54,7 @@ op-start armv5te-vfp
     op TEMPLATE_INVOKE_METHOD_NATIVE_PROF armv5te
     op TEMPLATE_INVOKE_METHOD_NO_OPT_PROF armv5te
     op TEMPLATE_RETURN_PROF armv5te
+    op TEMPLATE_MEM_OP_DECODE armv5te-vfp
 op-end
 
 # "helper" code for C; include if you use any of the C stubs (this generates
diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv7-a-neon.S b/vm/compiler/template/out/CompilerTemplateAsm-armv7-a-neon.S
index ae43d64a9..4b2c15ce6 100644
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv7-a-neon.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv7-a-neon.S
@@ -589,485 +589,6 @@ dvmCompiler_TEMPLATE_USHR_LONG:
 
 /* ------------------------------ */
     .balign 4
-    .global dvmCompiler_TEMPLATE_ADD_FLOAT_VFP
-dvmCompiler_TEMPLATE_ADD_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_ADD_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fadds   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_SUB_FLOAT_VFP
-dvmCompiler_TEMPLATE_SUB_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_SUB_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fsubs   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_MUL_FLOAT_VFP
-dvmCompiler_TEMPLATE_MUL_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_MUL_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fmuls   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DIV_FLOAT_VFP
-dvmCompiler_TEMPLATE_DIV_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_DIV_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fdivs   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_ADD_DOUBLE_VFP
-dvmCompiler_TEMPLATE_ADD_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_ADD_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     faddd   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_SUB_DOUBLE_VFP
-dvmCompiler_TEMPLATE_SUB_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_SUB_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     fsubd   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_MUL_DOUBLE_VFP
-dvmCompiler_TEMPLATE_MUL_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_MUL_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     fmuld   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DIV_DOUBLE_VFP
-dvmCompiler_TEMPLATE_DIV_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_DIV_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     fdivd   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DOUBLE_TO_FLOAT_VFP
-dvmCompiler_TEMPLATE_DOUBLE_TO_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_DOUBLE_TO_FLOAT_VFP.S */
-/* File: armv5te-vfp/funopNarrower.S */
-    /*
-     * Generic 64bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s0 = op d0".
-     *
-     * For: double-to-int, double-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    fldd    d0, [r1]                    @ d0<- vB
-    fcvtsd  s0, d0                              @ s0<- op d0
-    fsts    s0, [r0]                    @ vA<- s0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DOUBLE_TO_INT_VFP
-dvmCompiler_TEMPLATE_DOUBLE_TO_INT_VFP:
-/* File: armv5te-vfp/TEMPLATE_DOUBLE_TO_INT_VFP.S */
-/* File: armv5te-vfp/funopNarrower.S */
-    /*
-     * Generic 64bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s0 = op d0".
-     *
-     * For: double-to-int, double-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    fldd    d0, [r1]                    @ d0<- vB
-    ftosizd  s0, d0                              @ s0<- op d0
-    fsts    s0, [r0]                    @ vA<- s0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_FLOAT_TO_DOUBLE_VFP
-dvmCompiler_TEMPLATE_FLOAT_TO_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_FLOAT_TO_DOUBLE_VFP.S */
-/* File: armv5te-vfp/funopWider.S */
-    /*
-     * Generic 32bit-to-64bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "d0 = op s0".
-     *
-     * For: int-to-double, float-to-double
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    fcvtds  d0, s0                              @ d0<- op s0
-    fstd    d0, [r0]                    @ vA<- d0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_FLOAT_TO_INT_VFP
-dvmCompiler_TEMPLATE_FLOAT_TO_INT_VFP:
-/* File: armv5te-vfp/TEMPLATE_FLOAT_TO_INT_VFP.S */
-/* File: armv5te-vfp/funop.S */
-    /*
-     * Generic 32bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s1 = op s0".
-     *
-     * For: float-to-int, int-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    ftosizs s1, s0                              @ s1<- op s0
-    fsts    s1, [r0]                    @ vA<- s1
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_INT_TO_DOUBLE_VFP
-dvmCompiler_TEMPLATE_INT_TO_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_INT_TO_DOUBLE_VFP.S */
-/* File: armv5te-vfp/funopWider.S */
-    /*
-     * Generic 32bit-to-64bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "d0 = op s0".
-     *
-     * For: int-to-double, float-to-double
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    fsitod  d0, s0                              @ d0<- op s0
-    fstd    d0, [r0]                    @ vA<- d0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_INT_TO_FLOAT_VFP
-dvmCompiler_TEMPLATE_INT_TO_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_INT_TO_FLOAT_VFP.S */
-/* File: armv5te-vfp/funop.S */
-    /*
-     * Generic 32bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s1 = op s0".
-     *
-     * For: float-to-int, int-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    fsitos  s1, s0                              @ s1<- op s0
-    fsts    s1, [r0]                    @ vA<- s1
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPG_DOUBLE_VFP
-dvmCompiler_TEMPLATE_CMPG_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPG_DOUBLE_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else {
-     *         return 1;
-     *     }
-     * }
-     *
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    fldd    d0, [r0]                    @ d0<- vBB
-    fldd    d1, [r1]                    @ d1<- vCC
-    fcmpd  d0, d1                       @ compare (vBB, vCC)
-    mov     r0, #1                      @ r0<- 1 (default)
-    fmstat                              @ export status flags
-    mvnmi   r0, #0                      @ (less than) r0<- -1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPL_DOUBLE_VFP
-dvmCompiler_TEMPLATE_CMPL_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPL_DOUBLE_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else {
-     *         return -1;
-     *     }
-     * }
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    fldd    d0, [r0]                    @ d0<- vBB
-    fldd    d1, [r1]                    @ d1<- vCC
-    fcmped  d0, d1                      @ compare (vBB, vCC)
-    mvn     r0, #0                      @ r0<- -1 (default)
-    fmstat                              @ export status flags
-    movgt   r0, #1                      @ (greater than) r0<- 1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPG_FLOAT_VFP
-dvmCompiler_TEMPLATE_CMPG_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPG_FLOAT_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else {
-     *         return 1;
-     *     }
-     * }
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    flds    s0, [r0]                    @ d0<- vBB
-    flds    s1, [r1]                    @ d1<- vCC
-    fcmps  s0, s1                      @ compare (vBB, vCC)
-    mov     r0, #1                      @ r0<- 1 (default)
-    fmstat                              @ export status flags
-    mvnmi   r0, #0                      @ (less than) r0<- -1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPL_FLOAT_VFP
-dvmCompiler_TEMPLATE_CMPL_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPL_FLOAT_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else {
-     *         return -1;
-     *     }
-     * }
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    flds    s0, [r0]                    @ d0<- vBB
-    flds    s1, [r1]                    @ d1<- vCC
-    fcmps  s0, s1                      @ compare (vBB, vCC)
-    mvn     r0, #0                      @ r0<- -1 (default)
-    fmstat                              @ export status flags
-    movgt   r0, #1                      @ (greater than) r0<- 1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_SQRT_DOUBLE_VFP
-dvmCompiler_TEMPLATE_SQRT_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_SQRT_DOUBLE_VFP.S */
-    /*
-     * 64-bit floating point vfp sqrt operation.
-     * If the result is a NaN, bail out to library code to do
-     * the right thing.
-     *
-     * On entry:
-     *     r2 src addr of op1
-     * On exit:
-     *     r0,r1 = res
-     */
-    fldd    d0, [r2]
-    fsqrtd  d1, d0
-    fcmpd   d1, d1
-    fmstat
-    fmrrd   r0, r1, d1
-    bxeq    lr   @ Result OK - return
-    ldr     r2, .Lsqrt
-    fmrrd   r0, r1, d0   @ reload orig operand
-    bx      r2   @ tail call to sqrt library routine
-
-.Lsqrt:
-    .word   sqrt
-
-/* ------------------------------ */
-    .balign 4
     .global dvmCompiler_TEMPLATE_THROW_EXCEPTION_COMMON
 dvmCompiler_TEMPLATE_THROW_EXCEPTION_COMMON:
 /* File: armv5te/TEMPLATE_THROW_EXCEPTION_COMMON.S */
diff --git a/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S b/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S
index a0aad5380..9f85e1f66 100644
--- a/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S
+++ b/vm/compiler/template/out/CompilerTemplateAsm-armv7-a.S
@@ -589,485 +589,6 @@ dvmCompiler_TEMPLATE_USHR_LONG:
 
 /* ------------------------------ */
     .balign 4
-    .global dvmCompiler_TEMPLATE_ADD_FLOAT_VFP
-dvmCompiler_TEMPLATE_ADD_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_ADD_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fadds   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_SUB_FLOAT_VFP
-dvmCompiler_TEMPLATE_SUB_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_SUB_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fsubs   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_MUL_FLOAT_VFP
-dvmCompiler_TEMPLATE_MUL_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_MUL_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fmuls   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DIV_FLOAT_VFP
-dvmCompiler_TEMPLATE_DIV_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_DIV_FLOAT_VFP.S */
-/* File: armv5te-vfp/fbinop.S */
-    /*
-     * Generic 32-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     flds    s0,[r1]
-     flds    s1,[r2]
-     fdivs   s2, s0, s1
-     fsts    s2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_ADD_DOUBLE_VFP
-dvmCompiler_TEMPLATE_ADD_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_ADD_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     faddd   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_SUB_DOUBLE_VFP
-dvmCompiler_TEMPLATE_SUB_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_SUB_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     fsubd   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_MUL_DOUBLE_VFP
-dvmCompiler_TEMPLATE_MUL_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_MUL_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     fmuld   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DIV_DOUBLE_VFP
-dvmCompiler_TEMPLATE_DIV_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_DIV_DOUBLE_VFP.S */
-/* File: armv5te-vfp/fbinopWide.S */
-    /*
-     * Generic 64-bit floating point operation.  Provide an "instr" line that
-     * specifies an instruction that performs s2 = s0 op s1.
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = op1 address
-     *     r2 = op2 address
-     */
-     fldd    d0,[r1]
-     fldd    d1,[r2]
-     fdivd   d2, d0, d1
-     fstd    d2,[r0]
-     bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DOUBLE_TO_FLOAT_VFP
-dvmCompiler_TEMPLATE_DOUBLE_TO_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_DOUBLE_TO_FLOAT_VFP.S */
-/* File: armv5te-vfp/funopNarrower.S */
-    /*
-     * Generic 64bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s0 = op d0".
-     *
-     * For: double-to-int, double-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    fldd    d0, [r1]                    @ d0<- vB
-    fcvtsd  s0, d0                              @ s0<- op d0
-    fsts    s0, [r0]                    @ vA<- s0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_DOUBLE_TO_INT_VFP
-dvmCompiler_TEMPLATE_DOUBLE_TO_INT_VFP:
-/* File: armv5te-vfp/TEMPLATE_DOUBLE_TO_INT_VFP.S */
-/* File: armv5te-vfp/funopNarrower.S */
-    /*
-     * Generic 64bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s0 = op d0".
-     *
-     * For: double-to-int, double-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    fldd    d0, [r1]                    @ d0<- vB
-    ftosizd  s0, d0                              @ s0<- op d0
-    fsts    s0, [r0]                    @ vA<- s0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_FLOAT_TO_DOUBLE_VFP
-dvmCompiler_TEMPLATE_FLOAT_TO_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_FLOAT_TO_DOUBLE_VFP.S */
-/* File: armv5te-vfp/funopWider.S */
-    /*
-     * Generic 32bit-to-64bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "d0 = op s0".
-     *
-     * For: int-to-double, float-to-double
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    fcvtds  d0, s0                              @ d0<- op s0
-    fstd    d0, [r0]                    @ vA<- d0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_FLOAT_TO_INT_VFP
-dvmCompiler_TEMPLATE_FLOAT_TO_INT_VFP:
-/* File: armv5te-vfp/TEMPLATE_FLOAT_TO_INT_VFP.S */
-/* File: armv5te-vfp/funop.S */
-    /*
-     * Generic 32bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s1 = op s0".
-     *
-     * For: float-to-int, int-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    ftosizs s1, s0                              @ s1<- op s0
-    fsts    s1, [r0]                    @ vA<- s1
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_INT_TO_DOUBLE_VFP
-dvmCompiler_TEMPLATE_INT_TO_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_INT_TO_DOUBLE_VFP.S */
-/* File: armv5te-vfp/funopWider.S */
-    /*
-     * Generic 32bit-to-64bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "d0 = op s0".
-     *
-     * For: int-to-double, float-to-double
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    fsitod  d0, s0                              @ d0<- op s0
-    fstd    d0, [r0]                    @ vA<- d0
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_INT_TO_FLOAT_VFP
-dvmCompiler_TEMPLATE_INT_TO_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_INT_TO_FLOAT_VFP.S */
-/* File: armv5te-vfp/funop.S */
-    /*
-     * Generic 32bit-to-32bit floating point unary operation.  Provide an
-     * "instr" line that specifies an instruction that performs "s1 = op s0".
-     *
-     * For: float-to-int, int-to-float
-     *
-     * On entry:
-     *     r0 = target dalvik register address
-     *     r1 = src dalvik register address
-     */
-    /* unop vA, vB */
-    flds    s0, [r1]                    @ s0<- vB
-    fsitos  s1, s0                              @ s1<- op s0
-    fsts    s1, [r0]                    @ vA<- s1
-    bx      lr
-
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPG_DOUBLE_VFP
-dvmCompiler_TEMPLATE_CMPG_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPG_DOUBLE_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else {
-     *         return 1;
-     *     }
-     * }
-     *
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    fldd    d0, [r0]                    @ d0<- vBB
-    fldd    d1, [r1]                    @ d1<- vCC
-    fcmpd  d0, d1                       @ compare (vBB, vCC)
-    mov     r0, #1                      @ r0<- 1 (default)
-    fmstat                              @ export status flags
-    mvnmi   r0, #0                      @ (less than) r0<- -1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPL_DOUBLE_VFP
-dvmCompiler_TEMPLATE_CMPL_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPL_DOUBLE_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else {
-     *         return -1;
-     *     }
-     * }
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    fldd    d0, [r0]                    @ d0<- vBB
-    fldd    d1, [r1]                    @ d1<- vCC
-    fcmped  d0, d1                      @ compare (vBB, vCC)
-    mvn     r0, #0                      @ r0<- -1 (default)
-    fmstat                              @ export status flags
-    movgt   r0, #1                      @ (greater than) r0<- 1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPG_FLOAT_VFP
-dvmCompiler_TEMPLATE_CMPG_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPG_FLOAT_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else {
-     *         return 1;
-     *     }
-     * }
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    flds    s0, [r0]                    @ d0<- vBB
-    flds    s1, [r1]                    @ d1<- vCC
-    fcmps  s0, s1                      @ compare (vBB, vCC)
-    mov     r0, #1                      @ r0<- 1 (default)
-    fmstat                              @ export status flags
-    mvnmi   r0, #0                      @ (less than) r0<- -1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_CMPL_FLOAT_VFP
-dvmCompiler_TEMPLATE_CMPL_FLOAT_VFP:
-/* File: armv5te-vfp/TEMPLATE_CMPL_FLOAT_VFP.S */
-    /*
-     * Compare two floating-point values.  Puts 0, 1, or -1 into the
-     * destination register based on the results of the comparison.
-     *
-     * int compare(x, y) {
-     *     if (x == y) {
-     *         return 0;
-     *     } else if (x > y) {
-     *         return 1;
-     *     } else if (x < y) {
-     *         return -1;
-     *     } else {
-     *         return -1;
-     *     }
-     * }
-     * On entry:
-     *    r0 = &op1 [vBB]
-     *    r1 = &op2 [vCC]
-     */
-    /* op vAA, vBB, vCC */
-    flds    s0, [r0]                    @ d0<- vBB
-    flds    s1, [r1]                    @ d1<- vCC
-    fcmps  s0, s1                      @ compare (vBB, vCC)
-    mvn     r0, #0                      @ r0<- -1 (default)
-    fmstat                              @ export status flags
-    movgt   r0, #1                      @ (greater than) r0<- 1
-    moveq   r0, #0                      @ (equal) r0<- 0
-    bx      lr
-
-/* ------------------------------ */
-    .balign 4
-    .global dvmCompiler_TEMPLATE_SQRT_DOUBLE_VFP
-dvmCompiler_TEMPLATE_SQRT_DOUBLE_VFP:
-/* File: armv5te-vfp/TEMPLATE_SQRT_DOUBLE_VFP.S */
-    /*
-     * 64-bit floating point vfp sqrt operation.
-     * If the result is a NaN, bail out to library code to do
-     * the right thing.
-     *
-     * On entry:
-     *     r2 src addr of op1
-     * On exit:
-     *     r0,r1 = res
-     */
-    fldd    d0, [r2]
-    fsqrtd  d1, d0
-    fcmpd   d1, d1
-    fmstat
-    fmrrd   r0, r1, d1
-    bxeq    lr   @ Result OK - return
-    ldr     r2, .Lsqrt
-    fmrrd   r0, r1, d0   @ reload orig operand
-    bx      r2   @ tail call to sqrt library routine
-
-.Lsqrt:
-    .word   sqrt
-
-/* ------------------------------ */
-    .balign 4
     .global dvmCompiler_TEMPLATE_THROW_EXCEPTION_COMMON
 dvmCompiler_TEMPLATE_THROW_EXCEPTION_COMMON:
 /* File: armv5te/TEMPLATE_THROW_EXCEPTION_COMMON.S */