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| author | Dan Bornstein <danfuzz@android.com> | 2010-12-01 17:02:26 -0800 |
|---|---|---|
| committer | Dan Bornstein <danfuzz@android.com> | 2010-12-01 17:02:26 -0800 |
| commit | 9a1f81699cc05b58378ffb9aadb4e97677943791 (patch) | |
| tree | dc005d72c75a4e81a6a75ae4dd32370655ad0488 /vm/compiler | |
| parent | 5befcb64d815614a855199e19a0236ec3a01091c (diff) | |
| download | android_dalvik-9a1f81699cc05b58378ffb9aadb4e97677943791.tar.gz android_dalvik-9a1f81699cc05b58378ffb9aadb4e97677943791.tar.bz2 android_dalvik-9a1f81699cc05b58378ffb9aadb4e97677943791.zip | |
It's "opcode" not "opCode".
Similarly "Opcode" not "OpCode".
This appears to be the general worldwide consensus on the matter. Other
residents of my office didn't seem to mind one way or the other how it's
spelled in our code, but for whatever reason, it really bugged me.
Change-Id: Ia0b73d19c54aefc0f543a9c9451dda22ee876a59
Diffstat (limited to 'vm/compiler')
26 files changed, 551 insertions, 551 deletions
diff --git a/vm/compiler/Dataflow.c b/vm/compiler/Dataflow.c index 03cd1458f..dad52bf60 100644 --- a/vm/compiler/Dataflow.c +++ b/vm/compiler/Dataflow.c @@ -823,7 +823,7 @@ char *dvmCompilerGetDalvikDisassembly(DecodedInstruction *insn, char *note) { char buffer[256]; - int opcode = insn->opCode; + int opcode = insn->opcode; int dfAttributes = dvmCompilerDataFlowAttributes[opcode]; char *ret; @@ -948,7 +948,7 @@ void dvmCompilerFindLiveIn(CompilationUnit *cUnit, BasicBlock *bb) for (mir = bb->firstMIRInsn; mir; mir = mir->next) { int dfAttributes = - dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode]; + dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode]; DecodedInstruction *dInsn = &mir->dalvikInsn; if (dfAttributes & DF_HAS_USES) { @@ -1050,7 +1050,7 @@ void dvmCompilerDoSSAConversion(CompilationUnit *cUnit, BasicBlock *bb) mir->ssaRep = dvmCompilerNew(sizeof(SSARepresentation), true); int dfAttributes = - dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode]; + dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode]; int numUses = 0; @@ -1167,7 +1167,7 @@ void dvmCompilerDoConstantPropagation(CompilationUnit *cUnit, BasicBlock *bb) for (mir = bb->firstMIRInsn; mir; mir = mir->next) { int dfAttributes = - dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode]; + dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode]; DecodedInstruction *dInsn = &mir->dalvikInsn; @@ -1176,7 +1176,7 @@ void dvmCompilerDoConstantPropagation(CompilationUnit *cUnit, BasicBlock *bb) /* Handle instructions that set up constants directly */ if (dfAttributes & DF_SETS_CONST) { if (dfAttributes & DF_DA) { - switch (dInsn->opCode) { + switch (dInsn->opcode) { case OP_CONST_4: case OP_CONST_16: case OP_CONST: @@ -1190,7 +1190,7 @@ void dvmCompilerDoConstantPropagation(CompilationUnit *cUnit, BasicBlock *bb) break; } } else if (dfAttributes & DF_DA_WIDE) { - switch (dInsn->opCode) { + switch (dInsn->opcode) { case OP_CONST_WIDE_16: case OP_CONST_WIDE_32: setConstant(cUnit, mir->ssaRep->defs[0], dInsn->vB); @@ -1247,14 +1247,14 @@ void dvmCompilerFindInductionVariables(struct CompilationUnit *cUnit, /* If the bb doesn't have a phi it cannot contain an induction variable */ if (bb->firstMIRInsn == NULL || - bb->firstMIRInsn->dalvikInsn.opCode != kMirOpPhi) { + bb->firstMIRInsn->dalvikInsn.opcode != kMirOpPhi) { return; } /* Find basic induction variable first */ for (mir = bb->firstMIRInsn; mir; mir = mir->next) { int dfAttributes = - dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode]; + dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode]; if (!(dfAttributes & DF_IS_LINEAR)) continue; @@ -1266,14 +1266,14 @@ void dvmCompilerFindInductionVariables(struct CompilationUnit *cUnit, */ MIR *phi; for (phi = bb->firstMIRInsn; phi; phi = phi->next) { - if (phi->dalvikInsn.opCode != kMirOpPhi) break; + if (phi->dalvikInsn.opcode != kMirOpPhi) break; if (phi->ssaRep->defs[0] == mir->ssaRep->uses[0] && phi->ssaRep->uses[1] == mir->ssaRep->defs[0]) { bool deltaIsConstant = false; int deltaValue; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_INT: if (dvmIsBitSet(isConstantV, mir->ssaRep->uses[1])) { @@ -1319,7 +1319,7 @@ void dvmCompilerFindInductionVariables(struct CompilationUnit *cUnit, /* Find dependent induction variable now */ for (mir = bb->firstMIRInsn; mir; mir = mir->next) { int dfAttributes = - dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode]; + dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode]; if (!(dfAttributes & DF_IS_LINEAR)) continue; @@ -1340,7 +1340,7 @@ void dvmCompilerFindInductionVariables(struct CompilationUnit *cUnit, bool cIsConstant = false; int c = 0; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_INT: if (dvmIsBitSet(isConstantV, mir->ssaRep->uses[1])) { diff --git a/vm/compiler/Frontend.c b/vm/compiler/Frontend.c index 092412eec..901571954 100644 --- a/vm/compiler/Frontend.c +++ b/vm/compiler/Frontend.c @@ -27,7 +27,7 @@ static inline int parseInsn(const u2 *codePtr, DecodedInstruction *decInsn, bool printMe) { u2 instr = *codePtr; - OpCode opcode = dexOpCodeFromCodeUnit(instr); + Opcode opcode = dexOpcodeFromCodeUnit(instr); int insnWidth; // Don't parse instruction data @@ -59,7 +59,7 @@ static inline bool findBlockBoundary(const Method *caller, MIR *insn, unsigned int *target, bool *isInvoke, const Method **callee) { - switch (insn->dalvikInsn.opCode) { + switch (insn->dalvikInsn.opcode) { /* Target is not compile-time constant */ case OP_RETURN_VOID: case OP_RETURN: @@ -157,7 +157,7 @@ static inline bool findBlockBoundary(const Method *caller, MIR *insn, static inline bool isGoto(MIR *insn) { - switch (insn->dalvikInsn.opCode) { + switch (insn->dalvikInsn.opcode) { case OP_GOTO: case OP_GOTO_16: case OP_GOTO_32: @@ -172,7 +172,7 @@ static inline bool isGoto(MIR *insn) */ static inline bool isUnconditionalBranch(MIR *insn) { - switch (insn->dalvikInsn.opCode) { + switch (insn->dalvikInsn.opcode) { case OP_RETURN_VOID: case OP_RETURN: case OP_RETURN_WIDE: @@ -205,19 +205,19 @@ static int compareMethod(const CompilerMethodStats *m1, static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes, int offset) { - int flags = dexGetInstrFlags(dalvikInsn->opCode); - int dalvikOpCode = dalvikInsn->opCode; + int flags = dexGetInstrFlags(dalvikInsn->opcode); + int dalvikOpcode = dalvikInsn->opcode; if (flags & kInstrInvoke) { attributes &= ~METHOD_IS_LEAF; } if (!(flags & kInstrCanReturn)) { - if (!(dvmCompilerDataFlowAttributes[dalvikOpCode] & + if (!(dvmCompilerDataFlowAttributes[dalvikOpcode] & DF_IS_GETTER)) { attributes &= ~METHOD_IS_GETTER; } - if (!(dvmCompilerDataFlowAttributes[dalvikOpCode] & + if (!(dvmCompilerDataFlowAttributes[dalvikOpcode] & DF_IS_SETTER)) { attributes &= ~METHOD_IS_SETTER; } @@ -229,7 +229,7 @@ static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes, * otherwise. */ if (flags & kInstrCanReturn) { - if (dalvikOpCode == OP_RETURN_VOID) { + if (dalvikOpcode == OP_RETURN_VOID) { attributes &= ~METHOD_IS_GETTER; } else { @@ -241,7 +241,7 @@ static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes, attributes &= ~METHOD_IS_THROW_FREE; } - if (offset == 0 && dalvikOpCode == OP_RETURN_VOID) { + if (offset == 0 && dalvikOpcode == OP_RETURN_VOID) { attributes |= METHOD_IS_EMPTY; } @@ -250,7 +250,7 @@ static int analyzeInlineTarget(DecodedInstruction *dalvikInsn, int attributes, * If so, don't inline the callee as there is no stack frame for the * interpreter to single-step through the instruction. */ - if (SINGLE_STEP_OP(dalvikOpCode)) { + if (SINGLE_STEP_OP(dalvikOpcode)) { attributes &= ~(METHOD_IS_GETTER | METHOD_IS_SETTER); } @@ -569,7 +569,7 @@ bool dvmCompileTrace(JitTraceDescription *desc, int numMaxInsts, dvmCompilerAppendMIR(curBB, insn); cUnit.numInsts++; - int flags = dexGetInstrFlags(insn->dalvikInsn.opCode); + int flags = dexGetInstrFlags(insn->dalvikInsn.opcode); if (flags & kInstrInvoke) { assert(numInsts == 1); @@ -641,7 +641,7 @@ bool dvmCompileTrace(JitTraceDescription *desc, int numMaxInsts, /* Link the taken and fallthrough blocks */ BasicBlock *searchBB; - int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opCode); + int flags = dexGetInstrFlags(lastInsn->dalvikInsn.opcode); if (flags & kInstrInvoke) { cUnit.hasInvoke = true; @@ -737,8 +737,8 @@ bool dvmCompileTrace(JitTraceDescription *desc, int numMaxInsts, cUnit.hasLoop = true; } - if (lastInsn->dalvikInsn.opCode == OP_PACKED_SWITCH || - lastInsn->dalvikInsn.opCode == OP_SPARSE_SWITCH) { + if (lastInsn->dalvikInsn.opcode == OP_PACKED_SWITCH || + lastInsn->dalvikInsn.opcode == OP_SPARSE_SWITCH) { int i; const u2 *switchData = desc->method->insns + lastInsn->offset + lastInsn->dalvikInsn.vB; @@ -756,7 +756,7 @@ bool dvmCompileTrace(JitTraceDescription *desc, int numMaxInsts, } s4 *targets = (s4 *) (switchData + 2 + - (lastInsn->dalvikInsn.opCode == OP_PACKED_SWITCH ? + (lastInsn->dalvikInsn.opcode == OP_PACKED_SWITCH ? 2 : size * 2)); /* One chaining cell for the first MAX_CHAINED_SWITCH_CASES cases */ @@ -965,7 +965,7 @@ bool dvmCompileTrace(JitTraceDescription *desc, int numMaxInsts, bool dvmCompilerCanIncludeThisInstruction(const Method *method, const DecodedInstruction *insn) { - switch (insn->opCode) { + switch (insn->opcode) { case OP_NEW_INSTANCE: case OP_CHECK_CAST: { ClassObject *classPtr = (void*) @@ -1201,7 +1201,7 @@ bool dvmCompileMethod(CompilationUnit *cUnit, const Method *method, * aligned to 4-byte boundary (alignment instruction to be * inserted later. */ - if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opCode) + if (dexGetInstrFlags(curBB->lastMIRInsn->dalvikInsn.opcode) & kInstrInvoke) { newBB->isFallThroughFromInvoke = true; } diff --git a/vm/compiler/InlineTransformation.c b/vm/compiler/InlineTransformation.c index d67b1fb30..a632d6cbc 100644 --- a/vm/compiler/InlineTransformation.c +++ b/vm/compiler/InlineTransformation.c @@ -56,17 +56,17 @@ static void inlineGetter(CompilationUnit *cUnit, * by a move result. */ if ((moveResultMIR == NULL) || - (moveResultMIR->dalvikInsn.opCode != OP_MOVE_RESULT && - moveResultMIR->dalvikInsn.opCode != OP_MOVE_RESULT_OBJECT && - moveResultMIR->dalvikInsn.opCode != OP_MOVE_RESULT_WIDE)) { + (moveResultMIR->dalvikInsn.opcode != OP_MOVE_RESULT && + moveResultMIR->dalvikInsn.opcode != OP_MOVE_RESULT_OBJECT && + moveResultMIR->dalvikInsn.opcode != OP_MOVE_RESULT_WIDE)) { return; } - int dfFlags = dvmCompilerDataFlowAttributes[getterInsn.opCode]; + int dfFlags = dvmCompilerDataFlowAttributes[getterInsn.opcode]; /* Expecting vA to be the destination register */ if (dfFlags & (DF_UA | DF_UA_WIDE)) { - LOGE("opcode %d has DF_UA set (not expected)", getterInsn.opCode); + LOGE("opcode %d has DF_UA set (not expected)", getterInsn.opcode); dvmAbort(); } @@ -85,7 +85,7 @@ static void inlineGetter(CompilationUnit *cUnit, /* Now setup the Dalvik instruction with converted src/dst registers */ newGetterMIR->dalvikInsn = getterInsn; - newGetterMIR->width = dexGetInstrWidth(getterInsn.opCode); + newGetterMIR->width = dexGetInstrWidth(getterInsn.opcode); newGetterMIR->OptimizationFlags |= MIR_CALLEE; @@ -102,7 +102,7 @@ static void inlineGetter(CompilationUnit *cUnit, if (isPredicted) { MIR *invokeMIRSlow = dvmCompilerNew(sizeof(MIR), true); *invokeMIRSlow = *invokeMIR; - invokeMIR->dalvikInsn.opCode = kMirOpCheckInlinePrediction; + invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction; /* Use vC to denote the first argument (ie this) */ if (!isRange) { @@ -142,7 +142,7 @@ static void inlineSetter(CompilationUnit *cUnit, if (!dvmCompilerCanIncludeThisInstruction(calleeMethod, &setterInsn)) return; - int dfFlags = dvmCompilerDataFlowAttributes[setterInsn.opCode]; + int dfFlags = dvmCompilerDataFlowAttributes[setterInsn.opcode]; if (dfFlags & (DF_UA | DF_UA_WIDE)) { setterInsn.vA = convertRegId(&invokeMIR->dalvikInsn, calleeMethod, @@ -164,7 +164,7 @@ static void inlineSetter(CompilationUnit *cUnit, /* Now setup the Dalvik instruction with converted src/dst registers */ newSetterMIR->dalvikInsn = setterInsn; - newSetterMIR->width = dexGetInstrWidth(setterInsn.opCode); + newSetterMIR->width = dexGetInstrWidth(setterInsn.opcode); newSetterMIR->OptimizationFlags |= MIR_CALLEE; @@ -181,7 +181,7 @@ static void inlineSetter(CompilationUnit *cUnit, if (isPredicted) { MIR *invokeMIRSlow = dvmCompilerNew(sizeof(MIR), true); *invokeMIRSlow = *invokeMIR; - invokeMIR->dalvikInsn.opCode = kMirOpCheckInlinePrediction; + invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction; /* Use vC to denote the first argument (ie this) */ if (!isRange) { @@ -248,7 +248,7 @@ static void inlineEmptyVirtualCallee(CompilationUnit *cUnit, { MIR *invokeMIRSlow = dvmCompilerNew(sizeof(MIR), true); *invokeMIRSlow = *invokeMIR; - invokeMIR->dalvikInsn.opCode = kMirOpCheckInlinePrediction; + invokeMIR->dalvikInsn.opcode = kMirOpCheckInlinePrediction; dvmCompilerInsertMIRAfter(invokeBB, invokeMIR, invokeMIRSlow); invokeMIRSlow->OptimizationFlags |= MIR_INLINED_PRED; @@ -295,8 +295,8 @@ void dvmCompilerInlineMIR(CompilationUnit *cUnit) if (bb->blockType != kDalvikByteCode) continue; MIR *lastMIRInsn = bb->lastMIRInsn; - int opCode = lastMIRInsn->dalvikInsn.opCode; - int flags = dexGetInstrFlags(opCode); + int opcode = lastMIRInsn->dalvikInsn.opcode; + int flags = dexGetInstrFlags(opcode); /* No invoke - continue */ if ((flags & kInstrInvoke) == 0) @@ -306,12 +306,12 @@ void dvmCompilerInlineMIR(CompilationUnit *cUnit) * If the invoke itself is selected for single stepping, don't bother * to inline it. */ - if (SINGLE_STEP_OP(opCode)) + if (SINGLE_STEP_OP(opcode)) continue; const Method *calleeMethod; - switch (opCode) { + switch (opcode) { case OP_INVOKE_SUPER: case OP_INVOKE_DIRECT: case OP_INVOKE_STATIC: @@ -336,7 +336,7 @@ void dvmCompilerInlineMIR(CompilationUnit *cUnit) return; } - switch (opCode) { + switch (opcode) { case OP_INVOKE_VIRTUAL: case OP_INVOKE_VIRTUAL_QUICK: case OP_INVOKE_INTERFACE: diff --git a/vm/compiler/Loop.c b/vm/compiler/Loop.c index f3094505f..13e133cbf 100644 --- a/vm/compiler/Loop.c +++ b/vm/compiler/Loop.c @@ -58,7 +58,7 @@ static void handlePhiPlacement(CompilationUnit *cUnit) continue; } MIR *phi = dvmCompilerNew(sizeof(MIR), true); - phi->dalvikInsn.opCode = kMirOpPhi; + phi->dalvikInsn.opcode = kMirOpPhi; phi->dalvikInsn.vA = i; dvmCompilerPrependMIR(loopBody, phi); } @@ -72,7 +72,7 @@ static void fillPhiNodeContents(CompilationUnit *cUnit) MIR *mir; for (mir = loopBody->firstMIRInsn; mir; mir = mir->next) { - if (mir->dalvikInsn.opCode != kMirOpPhi) break; + if (mir->dalvikInsn.opcode != kMirOpPhi) break; int dalvikReg = mir->dalvikInsn.vA; mir->ssaRep->numUses = 2; @@ -185,7 +185,7 @@ static bool isLoopOptimizable(CompilationUnit *cUnit) } MIR *branch = loopBranch->lastMIRInsn; - OpCode opCode = branch->dalvikInsn.opCode; + Opcode opcode = branch->dalvikInsn.opcode; /* * If the instruction is not accessing the IV as the first operand, return @@ -208,7 +208,7 @@ static bool isLoopOptimizable(CompilationUnit *cUnit) * If the condition op is not > or >=, this is not an optimization * candidate. */ - if (opCode != OP_IF_GT && opCode != OP_IF_GE) { + if (opcode != OP_IF_GT && opcode != OP_IF_GE) { return false; } /* @@ -229,7 +229,7 @@ static bool isLoopOptimizable(CompilationUnit *cUnit) * If the condition op is not < or <=, this is not an optimization * candidate. */ - if (opCode == OP_IF_LT || opCode == OP_IF_LE) { + if (opcode == OP_IF_LT || opcode == OP_IF_LE) { /* * If the comparison is not between the BIV and a loop invariant, * return false. @@ -241,11 +241,11 @@ static bool isLoopOptimizable(CompilationUnit *cUnit) return false; } loopAnalysis->endConditionReg = DECODE_REG(endReg); - } else if (opCode != OP_IF_LTZ && opCode != OP_IF_LEZ) { + } else if (opcode != OP_IF_LTZ && opcode != OP_IF_LEZ) { return false; } } - loopAnalysis->loopBranchOpcode = opCode; + loopAnalysis->loopBranchOpcode = opcode; return true; } @@ -306,12 +306,12 @@ static bool doLoopBodyCodeMotion(CompilationUnit *cUnit) for (mir = loopBody->firstMIRInsn; mir; mir = mir->next) { DecodedInstruction *dInsn = &mir->dalvikInsn; int dfAttributes = - dvmCompilerDataFlowAttributes[mir->dalvikInsn.opCode]; + dvmCompilerDataFlowAttributes[mir->dalvikInsn.opcode]; /* Skip extended MIR instructions */ - if (dInsn->opCode >= kNumDalvikInstructions) continue; + if (dInsn->opcode >= kNumDalvikInstructions) continue; - int instrFlags = dexGetInstrFlags(dInsn->opCode); + int instrFlags = dexGetInstrFlags(dInsn->opcode); /* Instruction is clean */ if ((instrFlags & kInstrCanThrow) == 0) continue; @@ -403,7 +403,7 @@ static void genHoistedChecks(CompilationUnit *cUnit) dvmConvertSSARegToDalvik(cUnit, arrayAccessInfo->ivReg)); MIR *rangeCheckMIR = dvmCompilerNew(sizeof(MIR), true); - rangeCheckMIR->dalvikInsn.opCode = (loopAnalysis->isCountUpLoop) ? + rangeCheckMIR->dalvikInsn.opcode = (loopAnalysis->isCountUpLoop) ? kMirOpNullNRangeUpCheck : kMirOpNullNRangeDownCheck; rangeCheckMIR->dalvikInsn.vA = arrayReg; rangeCheckMIR->dalvikInsn.vB = idxReg; @@ -423,7 +423,7 @@ static void genHoistedChecks(CompilationUnit *cUnit) if (loopAnalysis->arrayAccessInfo->numUsed != 0) { if (loopAnalysis->isCountUpLoop) { MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true); - boundCheckMIR->dalvikInsn.opCode = kMirOpLowerBound; + boundCheckMIR->dalvikInsn.opcode = kMirOpLowerBound; boundCheckMIR->dalvikInsn.vA = idxReg; boundCheckMIR->dalvikInsn.vB = globalMinC; dvmCompilerAppendMIR(entry, boundCheckMIR); @@ -431,7 +431,7 @@ static void genHoistedChecks(CompilationUnit *cUnit) if (loopAnalysis->loopBranchOpcode == OP_IF_LT || loopAnalysis->loopBranchOpcode == OP_IF_LE) { MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true); - boundCheckMIR->dalvikInsn.opCode = kMirOpLowerBound; + boundCheckMIR->dalvikInsn.opcode = kMirOpLowerBound; boundCheckMIR->dalvikInsn.vA = loopAnalysis->endConditionReg; boundCheckMIR->dalvikInsn.vB = globalMinC; /* @@ -448,14 +448,14 @@ static void genHoistedChecks(CompilationUnit *cUnit) /* Array index will fall below 0 */ if (globalMinC < 0) { MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true); - boundCheckMIR->dalvikInsn.opCode = kMirOpPunt; + boundCheckMIR->dalvikInsn.opcode = kMirOpPunt; dvmCompilerAppendMIR(entry, boundCheckMIR); } } else if (loopAnalysis->loopBranchOpcode == OP_IF_LEZ) { /* Array index will fall below 0 */ if (globalMinC < -1) { MIR *boundCheckMIR = dvmCompilerNew(sizeof(MIR), true); - boundCheckMIR->dalvikInsn.opCode = kMirOpPunt; + boundCheckMIR->dalvikInsn.opcode = kMirOpPunt; dvmCompilerAppendMIR(entry, boundCheckMIR); } } else { diff --git a/vm/compiler/Loop.h b/vm/compiler/Loop.h index 0de2bafd6..8981dae68 100644 --- a/vm/compiler/Loop.h +++ b/vm/compiler/Loop.h @@ -27,7 +27,7 @@ typedef struct LoopAnalysis { int numBasicIV; // number of basic induction variables int ssaBIV; // basic IV in SSA name bool isCountUpLoop; // count up or down loop - OpCode loopBranchOpcode; // OP_IF_XXX for the loop back branch + Opcode loopBranchOpcode; // OP_IF_XXX for the loop back branch int endConditionReg; // vB in "vA op vB" LIR *branchToBody; // branch over to the body from entry LIR *branchToPCR; // branch over to the PCR cell diff --git a/vm/compiler/codegen/arm/ArchFactory.c b/vm/compiler/codegen/arm/ArchFactory.c index 1fe041218..581ba395c 100644 --- a/vm/compiler/codegen/arm/ArchFactory.c +++ b/vm/compiler/codegen/arm/ArchFactory.c @@ -89,7 +89,7 @@ static TGT_LIR *genBoundsCheck(CompilationUnit *cUnit, int rIndex, * Jump to the out-of-line handler in ARM mode to finish executing the * remaining of more complex instructions. */ -static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode) +static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpcode opcode) { /* * NOTE - In practice BLX only needs one operand, but since the assembler @@ -101,9 +101,9 @@ static void genDispatchToHandler(CompilationUnit *cUnit, TemplateOpCode opCode) */ dvmCompilerClobberHandlerRegs(cUnit); newLIR2(cUnit, kThumbBlx1, - (int) gDvmJit.codeCache + templateEntryOffsets[opCode], - (int) gDvmJit.codeCache + templateEntryOffsets[opCode]); + (int) gDvmJit.codeCache + templateEntryOffsets[opcode], + (int) gDvmJit.codeCache + templateEntryOffsets[opcode]); newLIR2(cUnit, kThumbBlx2, - (int) gDvmJit.codeCache + templateEntryOffsets[opCode], - (int) gDvmJit.codeCache + templateEntryOffsets[opCode]); + (int) gDvmJit.codeCache + templateEntryOffsets[opcode], + (int) gDvmJit.codeCache + templateEntryOffsets[opcode]); } diff --git a/vm/compiler/codegen/arm/ArchUtility.c b/vm/compiler/codegen/arm/ArchUtility.c index 764930092..0b76eb58b 100644 --- a/vm/compiler/codegen/arm/ArchUtility.c +++ b/vm/compiler/codegen/arm/ArchUtility.c @@ -283,7 +283,7 @@ void dvmDumpLIRInsn(LIR *arg, unsigned char *baseAddr) const bool dumpNop = false; /* Handle pseudo-ops individually, and all regular insns as a group */ - switch(lir->opCode) { + switch(lir->opcode) { case kArmChainingCellBottom: LOGD("-------- end of chaining cells (0x%04x)\n", offset); break; @@ -345,9 +345,9 @@ void dvmDumpLIRInsn(LIR *arg, unsigned char *baseAddr) if (lir->isNop && !dumpNop) { break; } - buildInsnString(EncodingMap[lir->opCode].name, lir, opName, + buildInsnString(EncodingMap[lir->opcode].name, lir, opName, baseAddr, 256); - buildInsnString(EncodingMap[lir->opCode].fmt, lir, buf, baseAddr, + buildInsnString(EncodingMap[lir->opcode].fmt, lir, buf, baseAddr, 256); LOGD("%p (%04x): %-8s%s%s\n", baseAddr + offset, offset, opName, buf, diff --git a/vm/compiler/codegen/arm/ArmLIR.h b/vm/compiler/codegen/arm/ArmLIR.h index 24f5240bd..213344cd8 100644 --- a/vm/compiler/codegen/arm/ArmLIR.h +++ b/vm/compiler/codegen/arm/ArmLIR.h @@ -306,14 +306,14 @@ typedef enum ArmConditionCode { kArmCondNv = 0xf, /* 1111 */ } ArmConditionCode; -#define isPseudoOpCode(opCode) ((int)(opCode) < 0) +#define isPseudoOpcode(opcode) ((int)(opcode) < 0) /* * The following enum defines the list of supported Thumb instructions by the * assembler. Their corresponding snippet positions will be defined in * Assemble.c. */ -typedef enum ArmOpCode { +typedef enum ArmOpcode { kArmChainingCellBottom = -18, kArmPseudoBarrier = -17, kArmPseudoExtended = -16, @@ -625,7 +625,7 @@ typedef enum ArmOpCode { kThumb2Dmb, /* dmb [1111001110111111100011110101] option[3-0] */ kArmLast, -} ArmOpCode; +} ArmOpcode; /* DMB option encodings */ typedef enum ArmOpDmbOptions { @@ -728,7 +728,7 @@ typedef struct ArmEncodingMap { int end; /* end for kFmtBitBlt, 1-bit slice end for FP regs */ int start; /* start for kFmtBitBlt, 4-bit slice end for FP regs */ } fieldLoc[4]; - ArmOpCode opCode; + ArmOpcode opcode; int flags; char *name; char* fmt; @@ -758,7 +758,7 @@ extern ArmEncodingMap EncodingMap[kArmLast]; */ typedef struct ArmLIR { LIR generic; - ArmOpCode opCode; + ArmOpcode opcode; int operands[4]; // [0..3] = [dest, src1, src2, extra] bool isNop; // LIR is optimized away bool branchInsertSV;// mark for insertion of branch before this instruction, diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c index 7ce04256f..42a8d3740 100644 --- a/vm/compiler/codegen/arm/Assemble.c +++ b/vm/compiler/codegen/arm/Assemble.c @@ -26,7 +26,7 @@ #define MAX_ASSEMBLER_RETRIES 10 /* - * opcode: ArmOpCode enum + * opcode: ArmOpcode enum * skeleton: pre-designated bit-pattern for this opcode * k0: key to applying ds/de * ds: dest start bit position @@ -930,8 +930,8 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, ArmLIR *lir; for (lir = (ArmLIR *) cUnit->firstLIRInsn; lir; lir = NEXT_LIR(lir)) { - if (lir->opCode < 0) { - if ((lir->opCode == kArmPseudoPseudoAlign4) && + if (lir->opcode < 0) { + if ((lir->opcode == kArmPseudoPseudoAlign4) && /* 1 means padding is needed */ (lir->operands[0] == 1)) { *bufferAddr++ = PADDING_MOV_R5_R5; @@ -943,10 +943,10 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, continue; } - if (lir->opCode == kThumbLdrPcRel || - lir->opCode == kThumb2LdrPcRel12 || - lir->opCode == kThumbAddPcRel || - ((lir->opCode == kThumb2Vldrs) && (lir->operands[1] == rpc))) { + if (lir->opcode == kThumbLdrPcRel || + lir->opcode == kThumb2LdrPcRel12 || + lir->opcode == kThumbAddPcRel || + ((lir->opcode == kThumb2Vldrs) && (lir->operands[1] == rpc))) { ArmLIR *lirTarget = (ArmLIR *) lir->generic.target; intptr_t pc = (lir->generic.offset + 4) & ~3; intptr_t target = lirTarget->generic.offset; @@ -955,18 +955,18 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, LOGE("PC-rel distance is not multiples of 4: %d\n", delta); dvmCompilerAbort(cUnit); } - if ((lir->opCode == kThumb2LdrPcRel12) && (delta > 4091)) { + if ((lir->opcode == kThumb2LdrPcRel12) && (delta > 4091)) { return kRetryHalve; } else if (delta > 1020) { return kRetryHalve; } - if (lir->opCode == kThumb2Vldrs) { + if (lir->opcode == kThumb2Vldrs) { lir->operands[2] = delta >> 2; } else { - lir->operands[1] = (lir->opCode == kThumb2LdrPcRel12) ? + lir->operands[1] = (lir->opcode == kThumb2LdrPcRel12) ? delta : delta >> 2; } - } else if (lir->opCode == kThumb2Cbnz || lir->opCode == kThumb2Cbz) { + } else if (lir->opcode == kThumb2Cbnz || lir->opcode == kThumb2Cbz) { ArmLIR *targetLIR = (ArmLIR *) lir->generic.target; intptr_t pc = lir->generic.offset + 4; intptr_t target = targetLIR->generic.offset; @@ -975,15 +975,15 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, /* Convert to cmp rx,#0 / b[eq/ne] tgt pair */ ArmLIR *newInst = dvmCompilerNew(sizeof(ArmLIR), true); /* Make new branch instruction and insert after */ - newInst->opCode = kThumbBCond; + newInst->opcode = kThumbBCond; newInst->operands[0] = 0; - newInst->operands[1] = (lir->opCode == kThumb2Cbz) ? + newInst->operands[1] = (lir->opcode == kThumb2Cbz) ? kArmCondEq : kArmCondNe; newInst->generic.target = lir->generic.target; dvmCompilerSetupResourceMasks(newInst); dvmCompilerInsertLIRAfter((LIR *)lir, (LIR *)newInst); /* Convert the cb[n]z to a cmp rx, #0 ] */ - lir->opCode = kThumbCmpRI8; + lir->opcode = kThumbCmpRI8; /* operand[0] is src1 in both cb[n]z & CmpRI8 */ lir->operands[1] = 0; lir->generic.target = 0; @@ -992,17 +992,17 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, } else { lir->operands[1] = delta >> 1; } - } else if (lir->opCode == kThumbBCond || - lir->opCode == kThumb2BCond) { + } else if (lir->opcode == kThumbBCond || + lir->opcode == kThumb2BCond) { ArmLIR *targetLIR = (ArmLIR *) lir->generic.target; intptr_t pc = lir->generic.offset + 4; intptr_t target = targetLIR->generic.offset; int delta = target - pc; - if ((lir->opCode == kThumbBCond) && (delta > 254 || delta < -256)) { + if ((lir->opcode == kThumbBCond) && (delta > 254 || delta < -256)) { return kRetryHalve; } lir->operands[0] = delta >> 1; - } else if (lir->opCode == kThumbBUncond) { + } else if (lir->opcode == kThumbBUncond) { ArmLIR *targetLIR = (ArmLIR *) lir->generic.target; intptr_t pc = lir->generic.offset + 4; intptr_t target = targetLIR->generic.offset; @@ -1012,8 +1012,8 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, dvmCompilerAbort(cUnit); } lir->operands[0] = delta >> 1; - } else if (lir->opCode == kThumbBlx1) { - assert(NEXT_LIR(lir)->opCode == kThumbBlx2); + } else if (lir->opcode == kThumbBlx1) { + assert(NEXT_LIR(lir)->opcode == kThumbBlx2); /* curPC is Thumb */ intptr_t curPC = (startAddr + lir->generic.offset + 4) & ~3; intptr_t target = lir->operands[1]; @@ -1029,7 +1029,7 @@ static AssemblerStatus assembleInstructions(CompilationUnit *cUnit, NEXT_LIR(lir)->operands[0] = (delta>> 1) & 0x7ff; } - ArmEncodingMap *encoder = &EncodingMap[lir->opCode]; + ArmEncodingMap *encoder = &EncodingMap[lir->opcode]; u4 bits = encoder->skeleton; int i; for (i = 0; i < 4; i++) { @@ -1218,10 +1218,10 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info) armLIR; armLIR = NEXT_LIR(armLIR)) { armLIR->generic.offset = offset; - if (armLIR->opCode >= 0 && !armLIR->isNop) { - armLIR->size = EncodingMap[armLIR->opCode].size * 2; + if (armLIR->opcode >= 0 && !armLIR->isNop) { + armLIR->size = EncodingMap[armLIR->opcode].size * 2; offset += armLIR->size; - } else if (armLIR->opCode == kArmPseudoPseudoAlign4) { + } else if (armLIR->opcode == kArmPseudoPseudoAlign4) { if (offset & 0x2) { offset += 2; armLIR->operands[0] = 1; @@ -1247,7 +1247,7 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info) ArmLIR *chainCellOffsetLIR = (ArmLIR *) cUnit->chainCellOffsetLIR; assert(chainCellOffsetLIR); assert(chainCellOffset < 0x10000); - assert(chainCellOffsetLIR->opCode == kArm16BitData && + assert(chainCellOffsetLIR->opcode == kArm16BitData && chainCellOffsetLIR->operands[0] == CHAIN_CELL_OFFSET_TAG); /* @@ -1369,7 +1369,7 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info) * Returns the skeleton bit pattern associated with an opcode. All * variable fields are zeroed. */ -static u4 getSkeleton(ArmOpCode op) +static u4 getSkeleton(ArmOpcode op) { return EncodingMap[op].skeleton; } diff --git a/vm/compiler/codegen/arm/CodegenCommon.c b/vm/compiler/codegen/arm/CodegenCommon.c index d14dd0640..05cead3e7 100644 --- a/vm/compiler/codegen/arm/CodegenCommon.c +++ b/vm/compiler/codegen/arm/CodegenCommon.c @@ -36,7 +36,7 @@ static void setMemRefType(ArmLIR *lir, bool isLoad, int memType) { u8 *maskPtr; u8 mask; - assert( EncodingMap[lir->opCode].flags & (IS_LOAD | IS_STORE)); + assert( EncodingMap[lir->opcode].flags & (IS_LOAD | IS_STORE)); if (isLoad) { maskPtr = &lir->useMask; mask = ENCODE_MEM_USE; @@ -108,15 +108,15 @@ static inline void setupRegMask(u8 *mask, int reg) */ static void setupResourceMasks(ArmLIR *lir) { - int opCode = lir->opCode; + int opcode = lir->opcode; int flags; - if (opCode <= 0) { + if (opcode <= 0) { lir->useMask = lir->defMask = 0; return; } - flags = EncodingMap[lir->opCode].flags; + flags = EncodingMap[lir->opcode].flags; /* Set up the mask for resources that are updated */ if (flags & (IS_LOAD | IS_STORE)) { @@ -202,35 +202,35 @@ static void setupResourceMasks(ArmLIR *lir) * The following are building blocks to construct low-level IRs with 0 - 4 * operands. */ -static ArmLIR *newLIR0(CompilationUnit *cUnit, ArmOpCode opCode) +static ArmLIR *newLIR0(CompilationUnit *cUnit, ArmOpcode opcode) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - assert(isPseudoOpCode(opCode) || (EncodingMap[opCode].flags & NO_OPERAND)); - insn->opCode = opCode; + assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & NO_OPERAND)); + insn->opcode = opcode; setupResourceMasks(insn); dvmCompilerAppendLIR(cUnit, (LIR *) insn); return insn; } -static ArmLIR *newLIR1(CompilationUnit *cUnit, ArmOpCode opCode, +static ArmLIR *newLIR1(CompilationUnit *cUnit, ArmOpcode opcode, int dest) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - assert(isPseudoOpCode(opCode) || (EncodingMap[opCode].flags & IS_UNARY_OP)); - insn->opCode = opCode; + assert(isPseudoOpcode(opcode) || (EncodingMap[opcode].flags & IS_UNARY_OP)); + insn->opcode = opcode; insn->operands[0] = dest; setupResourceMasks(insn); dvmCompilerAppendLIR(cUnit, (LIR *) insn); return insn; } -static ArmLIR *newLIR2(CompilationUnit *cUnit, ArmOpCode opCode, +static ArmLIR *newLIR2(CompilationUnit *cUnit, ArmOpcode opcode, int dest, int src1) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - assert(isPseudoOpCode(opCode) || - (EncodingMap[opCode].flags & IS_BINARY_OP)); - insn->opCode = opCode; + assert(isPseudoOpcode(opcode) || + (EncodingMap[opcode].flags & IS_BINARY_OP)); + insn->opcode = opcode; insn->operands[0] = dest; insn->operands[1] = src1; setupResourceMasks(insn); @@ -238,16 +238,16 @@ static ArmLIR *newLIR2(CompilationUnit *cUnit, ArmOpCode opCode, return insn; } -static ArmLIR *newLIR3(CompilationUnit *cUnit, ArmOpCode opCode, +static ArmLIR *newLIR3(CompilationUnit *cUnit, ArmOpcode opcode, int dest, int src1, int src2) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - if (!(EncodingMap[opCode].flags & IS_TERTIARY_OP)) { - LOGE("Bad LIR3: %s[%d]",EncodingMap[opCode].name,opCode); + if (!(EncodingMap[opcode].flags & IS_TERTIARY_OP)) { + LOGE("Bad LIR3: %s[%d]",EncodingMap[opcode].name,opcode); } - assert(isPseudoOpCode(opCode) || - (EncodingMap[opCode].flags & IS_TERTIARY_OP)); - insn->opCode = opCode; + assert(isPseudoOpcode(opcode) || + (EncodingMap[opcode].flags & IS_TERTIARY_OP)); + insn->opcode = opcode; insn->operands[0] = dest; insn->operands[1] = src1; insn->operands[2] = src2; @@ -257,13 +257,13 @@ static ArmLIR *newLIR3(CompilationUnit *cUnit, ArmOpCode opCode, } #if defined(_ARMV7_A) || defined(_ARMV7_A_NEON) -static ArmLIR *newLIR4(CompilationUnit *cUnit, ArmOpCode opCode, +static ArmLIR *newLIR4(CompilationUnit *cUnit, ArmOpcode opcode, int dest, int src1, int src2, int info) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - assert(isPseudoOpCode(opCode) || - (EncodingMap[opCode].flags & IS_QUAD_OP)); - insn->opCode = opCode; + assert(isPseudoOpcode(opcode) || + (EncodingMap[opcode].flags & IS_QUAD_OP)); + insn->opcode = opcode; insn->operands[0] = dest; insn->operands[1] = src1; insn->operands[2] = src2; @@ -283,9 +283,9 @@ static RegLocation inlinedTarget(CompilationUnit *cUnit, MIR *mir, bool fpHint) { if (mir->next && - ((mir->next->dalvikInsn.opCode == OP_MOVE_RESULT) || - (mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_OBJECT))) { - mir->next->dalvikInsn.opCode = OP_NOP; + ((mir->next->dalvikInsn.opcode == OP_MOVE_RESULT) || + (mir->next->dalvikInsn.opcode == OP_MOVE_RESULT_OBJECT))) { + mir->next->dalvikInsn.opcode = OP_NOP; return dvmCompilerGetDest(cUnit, mir->next, 0); } else { RegLocation res = LOC_DALVIK_RETURN_VAL; @@ -338,8 +338,8 @@ static RegLocation inlinedTargetWide(CompilationUnit *cUnit, MIR *mir, bool fpHint) { if (mir->next && - (mir->next->dalvikInsn.opCode == OP_MOVE_RESULT_WIDE)) { - mir->next->dalvikInsn.opCode = OP_NOP; + (mir->next->dalvikInsn.opcode == OP_MOVE_RESULT_WIDE)) { + mir->next->dalvikInsn.opcode = OP_NOP; return dvmCompilerGetDestWide(cUnit, mir->next, 0, 1); } else { RegLocation res = LOC_DALVIK_RETURN_VAL_WIDE; @@ -372,7 +372,7 @@ static ArmLIR *genCheckCommon(CompilationUnit *cUnit, int dOffset, if (pcrLabel == NULL) { int dPC = (int) (cUnit->method->insns + dOffset); pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = dOffset; /* Insert the place holder to the growable list */ diff --git a/vm/compiler/codegen/arm/CodegenDriver.c b/vm/compiler/codegen/arm/CodegenDriver.c index b52420fcc..9892f56ca 100644 --- a/vm/compiler/codegen/arm/CodegenDriver.c +++ b/vm/compiler/codegen/arm/CodegenDriver.c @@ -85,7 +85,7 @@ static bool genArithOpFloatPortable(CompilationUnit *cUnit, MIR *mir, RegLocation rlResult; void* funct; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_FLOAT_2ADDR: case OP_ADD_FLOAT: funct = (void*) __aeabi_fadd; @@ -131,7 +131,7 @@ static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir, RegLocation rlResult; void* funct; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_DOUBLE_2ADDR: case OP_ADD_DOUBLE: funct = (void*) __aeabi_dadd; @@ -172,9 +172,9 @@ static bool genArithOpDoublePortable(CompilationUnit *cUnit, MIR *mir, static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; - switch (opCode) { + switch (opcode) { case OP_INT_TO_FLOAT: return genConversionCall(cUnit, mir, (void*)__aeabi_i2f, 1, 1); case OP_FLOAT_TO_INT: @@ -202,11 +202,11 @@ static bool genConversionPortable(CompilationUnit *cUnit, MIR *mir) } #if defined(WITH_SELF_VERIFICATION) -static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpCode opCode, +static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpcode opcode, int dest, int src1) { ArmLIR *insn = dvmCompilerNew(sizeof(ArmLIR), true); - insn->opCode = opCode; + insn->opcode = opcode; insn->operands[0] = dest; insn->operands[1] = src1; setupResourceMasks(insn); @@ -216,7 +216,7 @@ static void selfVerificationBranchInsert(LIR *currentLIR, ArmOpCode opCode, static void selfVerificationBranchInsertPass(CompilationUnit *cUnit) { ArmLIR *thisLIR; - TemplateOpCode opCode = TEMPLATE_MEM_OP_DECODE; + TemplateOpcode opcode = TEMPLATE_MEM_OP_DECODE; for (thisLIR = (ArmLIR *) cUnit->firstLIRInsn; thisLIR != (ArmLIR *) cUnit->lastLIRInsn; @@ -224,11 +224,11 @@ static void selfVerificationBranchInsertPass(CompilationUnit *cUnit) if (thisLIR->branchInsertSV) { /* Branch to mem op decode template */ selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx1, - (int) gDvmJit.codeCache + templateEntryOffsets[opCode], - (int) gDvmJit.codeCache + templateEntryOffsets[opCode]); + (int) gDvmJit.codeCache + templateEntryOffsets[opcode], + (int) gDvmJit.codeCache + templateEntryOffsets[opcode]); selfVerificationBranchInsert((LIR *) thisLIR, kThumbBlx2, - (int) gDvmJit.codeCache + templateEntryOffsets[opCode], - (int) gDvmJit.codeCache + templateEntryOffsets[opCode]); + (int) gDvmJit.codeCache + templateEntryOffsets[opcode], + (int) gDvmJit.codeCache + templateEntryOffsets[opcode]); } } } @@ -593,7 +593,7 @@ static bool genShiftOpLong(CompilationUnit *cUnit, MIR *mir, loadValueDirectWideFixed(cUnit, rlSrc1, r0, r1); loadValueDirect(cUnit, rlShift, r2); - switch( mir->dalvikInsn.opCode) { + switch( mir->dalvikInsn.opcode) { case OP_SHL_LONG: case OP_SHL_LONG_2ADDR: genDispatchToHandler(cUnit, TEMPLATE_SHL_LONG); @@ -625,7 +625,7 @@ static bool genArithOpLong(CompilationUnit *cUnit, MIR *mir, void *callTgt; int retReg = r0; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_NOT_LONG: rlSrc2 = loadValueWide(cUnit, rlSrc2, kCoreReg); rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true); @@ -725,7 +725,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, RegLocation rlResult; bool shiftOp = false; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_NEG_INT: op = kOpNeg; unary = true; @@ -790,7 +790,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, break; default: LOGE("Invalid word arith op: 0x%x(%d)", - mir->dalvikInsn.opCode, mir->dalvikInsn.opCode); + mir->dalvikInsn.opcode, mir->dalvikInsn.opcode); dvmCompilerAbort(cUnit); } if (!callOut) { @@ -837,7 +837,7 @@ static bool genArithOpInt(CompilationUnit *cUnit, MIR *mir, static bool genArithOp(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; RegLocation rlDest; RegLocation rlSrc1; RegLocation rlSrc2; @@ -860,34 +860,34 @@ static bool genArithOp(CompilationUnit *cUnit, MIR *mir) rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1); } - if ((opCode >= OP_ADD_LONG_2ADDR) && (opCode <= OP_XOR_LONG_2ADDR)) { + if ((opcode >= OP_ADD_LONG_2ADDR) && (opcode <= OP_XOR_LONG_2ADDR)) { return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_LONG) && (opCode <= OP_XOR_LONG)) { + if ((opcode >= OP_ADD_LONG) && (opcode <= OP_XOR_LONG)) { return genArithOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_SHL_LONG_2ADDR) && (opCode <= OP_USHR_LONG_2ADDR)) { + if ((opcode >= OP_SHL_LONG_2ADDR) && (opcode <= OP_USHR_LONG_2ADDR)) { return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_SHL_LONG) && (opCode <= OP_USHR_LONG)) { + if ((opcode >= OP_SHL_LONG) && (opcode <= OP_USHR_LONG)) { return genShiftOpLong(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_INT_2ADDR) && (opCode <= OP_USHR_INT_2ADDR)) { + if ((opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_USHR_INT_2ADDR)) { return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_INT) && (opCode <= OP_USHR_INT)) { + if ((opcode >= OP_ADD_INT) && (opcode <= OP_USHR_INT)) { return genArithOpInt(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_FLOAT_2ADDR) && (opCode <= OP_REM_FLOAT_2ADDR)) { + if ((opcode >= OP_ADD_FLOAT_2ADDR) && (opcode <= OP_REM_FLOAT_2ADDR)) { return genArithOpFloat(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_FLOAT) && (opCode <= OP_REM_FLOAT)) { + if ((opcode >= OP_ADD_FLOAT) && (opcode <= OP_REM_FLOAT)) { return genArithOpFloat(cUnit, mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_DOUBLE_2ADDR) && (opCode <= OP_REM_DOUBLE_2ADDR)) { + if ((opcode >= OP_ADD_DOUBLE_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) { return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2); } - if ((opCode >= OP_ADD_DOUBLE) && (opCode <= OP_REM_DOUBLE)) { + if ((opcode >= OP_ADD_DOUBLE) && (opcode <= OP_REM_DOUBLE)) { return genArithOpDouble(cUnit,mir, rlDest, rlSrc1, rlSrc2); } return true; @@ -913,7 +913,7 @@ static void genReturnCommon(CompilationUnit *cUnit, MIR *mir) ArmLIR *branch = genUnconditionalBranch(cUnit, NULL); /* Set up the place holder to reconstruct this Dalvik PC */ ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = mir->offset; /* Insert the place holder to the growable list */ @@ -1157,7 +1157,7 @@ static void genInvokeVirtualCommon(CompilationUnit *cUnit, MIR *mir, if (pcrLabel == NULL) { int dPC = (int) (cUnit->method->insns + mir->offset); pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = mir->offset; /* Insert the place holder to the growable list */ @@ -1233,12 +1233,12 @@ static void genPuntToInterp(CompilationUnit *cUnit, unsigned int offset) */ static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir) { - int flags = dexGetInstrFlags(mir->dalvikInsn.opCode); + int flags = dexGetInstrFlags(mir->dalvikInsn.opcode); int flagsToCheck = kInstrCanBranch | kInstrCanSwitch | kInstrCanReturn | kInstrCanThrow; //If already optimized out, just ignore - if (mir->dalvikInsn.opCode == OP_NOP) + if (mir->dalvikInsn.opcode == OP_NOP) return; //Ugly, but necessary. Flush all Dalvik regs so Interp can find them @@ -1273,7 +1273,7 @@ static void genInterpSingleStep(CompilationUnit *cUnit, MIR *mir) */ static void genMonitorPortable(CompilationUnit *cUnit, MIR *mir) { - bool isEnter = (mir->dalvikInsn.opCode == OP_MONITOR_ENTER); + bool isEnter = (mir->dalvikInsn.opcode == OP_MONITOR_ENTER); genExportPC(cUnit, mir); dvmCompilerFlushAllRegs(cUnit); /* Send everything to home location */ RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); @@ -1323,12 +1323,12 @@ static bool handleFmt10t_Fmt20t_Fmt30t(CompilationUnit *cUnit, MIR *mir, static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; - if ((dalvikOpCode >= OP_UNUSED_3E) && (dalvikOpCode <= OP_UNUSED_43)) { - LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode); + Opcode dalvikOpcode = mir->dalvikInsn.opcode; + if ((dalvikOpcode >= OP_UNUSED_3E) && (dalvikOpcode <= OP_UNUSED_43)) { + LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode); return true; } - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_RETURN_VOID_BARRIER: dvmCompilerGenMemBarrier(cUnit, kST); // Intentional fallthrough @@ -1339,7 +1339,7 @@ static bool handleFmt10x(CompilationUnit *cUnit, MIR *mir) case OP_UNUSED_79: case OP_UNUSED_7A: case OP_UNUSED_FF: - LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpCode); + LOGE("Codegen: got unused opcode 0x%x\n",dalvikOpcode); return true; case OP_NOP: break; @@ -1359,7 +1359,7 @@ static bool handleFmt11n_Fmt31i(CompilationUnit *cUnit, MIR *mir) rlDest = dvmCompilerGetDest(cUnit, mir, 0); } - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CONST: case OP_CONST_4: { rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true); @@ -1394,7 +1394,7 @@ static bool handleFmt21h(CompilationUnit *cUnit, MIR *mir) } rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true); - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CONST_HIGH16: { loadConstantNoClobber(cUnit, rlResult.lowReg, mir->dalvikInsn.vB << 16); @@ -1426,7 +1426,7 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) RegLocation rlDest; RegLocation rlSrc; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CONST_STRING_JUMBO: case OP_CONST_STRING: { void *strPtr = (void*) @@ -1479,8 +1479,8 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) dvmAbort(); } - isVolatile = (mir->dalvikInsn.opCode == OP_SGET_VOLATILE) || - (mir->dalvikInsn.opCode == OP_SGET_OBJECT_VOLATILE) || + isVolatile = (mir->dalvikInsn.opcode == OP_SGET_VOLATILE) || + (mir->dalvikInsn.opcode == OP_SGET_OBJECT_VOLATILE) || dvmIsVolatileField(fieldPtr); rlDest = dvmCompilerGetDest(cUnit, mir, 0); @@ -1539,12 +1539,12 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) void *fieldPtr = (void*) (method->clazz->pDvmDex->pResFields[mir->dalvikInsn.vB]); - isVolatile = (mir->dalvikInsn.opCode == OP_SPUT_VOLATILE) || - (mir->dalvikInsn.opCode == OP_SPUT_OBJECT_VOLATILE) || + isVolatile = (mir->dalvikInsn.opcode == OP_SPUT_VOLATILE) || + (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE) || dvmIsVolatileField(fieldPtr); - isSputObject = (mir->dalvikInsn.opCode == OP_SPUT_OBJECT) || - (mir->dalvikInsn.opCode == OP_SPUT_OBJECT_VOLATILE); + isSputObject = (mir->dalvikInsn.opcode == OP_SPUT_OBJECT) || + (mir->dalvikInsn.opcode == OP_SPUT_OBJECT_VOLATILE); if (fieldPtr == NULL) { LOGE("Unexpected null static field"); @@ -1718,9 +1718,9 @@ static bool handleFmt21c_Fmt31c(CompilationUnit *cUnit, MIR *mir) */ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; RegLocation rlResult; - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_MOVE_EXCEPTION: { int offset = offsetof(InterpState, self); int exOffset = offsetof(Thread, exception); @@ -1793,12 +1793,12 @@ static bool handleFmt11x(CompilationUnit *cUnit, MIR *mir) static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; RegLocation rlDest; RegLocation rlSrc; RegLocation rlResult; - if ( (opCode >= OP_ADD_INT_2ADDR) && (opCode <= OP_REM_DOUBLE_2ADDR)) { + if ( (opcode >= OP_ADD_INT_2ADDR) && (opcode <= OP_REM_DOUBLE_2ADDR)) { return genArithOp( cUnit, mir ); } @@ -1811,7 +1811,7 @@ static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir) else rlDest = dvmCompilerGetDest(cUnit, mir, 0); - switch (opCode) { + switch (opcode) { case OP_DOUBLE_TO_INT: case OP_INT_TO_FLOAT: case OP_FLOAT_TO_INT: @@ -1894,18 +1894,18 @@ static bool handleFmt12x(CompilationUnit *cUnit, MIR *mir) static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; RegLocation rlDest; RegLocation rlResult; int BBBB = mir->dalvikInsn.vB; - if (dalvikOpCode == OP_CONST_WIDE_16) { + if (dalvikOpcode == OP_CONST_WIDE_16) { rlDest = dvmCompilerGetDestWide(cUnit, mir, 0, 1); rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true); loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB); //TUNING: do high separately to avoid load dependency opRegRegImm(cUnit, kOpAsr, rlResult.highReg, rlResult.lowReg, 31); storeValueWide(cUnit, rlDest, rlResult); - } else if (dalvikOpCode == OP_CONST_16) { + } else if (dalvikOpcode == OP_CONST_16) { rlDest = dvmCompilerGetDest(cUnit, mir, 0); rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kAnyReg, true); loadConstantNoClobber(cUnit, rlResult.lowReg, BBBB); @@ -1919,14 +1919,14 @@ static bool handleFmt21s(CompilationUnit *cUnit, MIR *mir) static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, ArmLIR *labelList) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; ArmConditionCode cond; RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); rlSrc = loadValue(cUnit, rlSrc, kCoreReg); opRegImm(cUnit, kOpCmp, rlSrc.lowReg, 0); //TUNING: break this out to allow use of Thumb2 CB[N]Z - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_IF_EQZ: cond = kArmCondEq; break; @@ -1947,7 +1947,7 @@ static bool handleFmt21t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, break; default: cond = 0; - LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpCode); + LOGE("Unexpected opcode (%d) for Fmt21t\n", dalvikOpcode); dvmCompilerAbort(cUnit); } genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]); @@ -1984,7 +1984,7 @@ static int lowestSetBit(unsigned int x) { // Returns true if it added instructions to 'cUnit' to divide 'rlSrc' by 'lit' // and store the result in 'rlDest'. -static bool handleEasyDivide(CompilationUnit *cUnit, OpCode dalvikOpCode, +static bool handleEasyDivide(CompilationUnit *cUnit, Opcode dalvikOpcode, RegLocation rlSrc, RegLocation rlDest, int lit) { if (lit < 2 || !isPowerOfTwo(lit)) { @@ -1995,7 +1995,7 @@ static bool handleEasyDivide(CompilationUnit *cUnit, OpCode dalvikOpCode, // Avoid special cases. return false; } - bool div = (dalvikOpCode == OP_DIV_INT_LIT8 || dalvikOpCode == OP_DIV_INT_LIT16); + bool div = (dalvikOpcode == OP_DIV_INT_LIT8 || dalvikOpcode == OP_DIV_INT_LIT16); rlSrc = loadValue(cUnit, rlSrc, kCoreReg); RegLocation rlResult = dvmCompilerEvalLoc(cUnit, rlDest, kCoreReg, true); if (div) { @@ -2080,7 +2080,7 @@ static bool handleEasyMultiply(CompilationUnit *cUnit, static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); RegLocation rlDest = dvmCompilerGetDest(cUnit, mir, 0); RegLocation rlResult; @@ -2089,7 +2089,7 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) int shiftOp = false; bool isDiv = false; - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_RSUB_INT_LIT8: case OP_RSUB_INT: { int tReg; @@ -2154,14 +2154,14 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) genInterpSingleStep(cUnit, mir); return false; } - if (handleEasyDivide(cUnit, dalvikOpCode, rlSrc, rlDest, lit)) { + if (handleEasyDivide(cUnit, dalvikOpcode, rlSrc, rlDest, lit)) { return false; } dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */ loadValueDirectFixed(cUnit, rlSrc, r0); dvmCompilerClobber(cUnit, r0); - if ((dalvikOpCode == OP_DIV_INT_LIT8) || - (dalvikOpCode == OP_DIV_INT_LIT16)) { + if ((dalvikOpcode == OP_DIV_INT_LIT8) || + (dalvikOpcode == OP_DIV_INT_LIT16)) { LOAD_FUNC_ADDR(cUnit, r2, (int)__aeabi_idiv); isDiv = true; } else { @@ -2195,10 +2195,10 @@ static bool handleFmt22b_Fmt22s(CompilationUnit *cUnit, MIR *mir) static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; int fieldOffset = -1; bool isVolatile = false; - switch (dalvikOpCode) { + switch (dalvikOpcode) { /* * Wide volatiles currently handled via single step. * Add them here if generating in-line code. @@ -2240,7 +2240,7 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) break; } - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_NEW_ARRAY: { // Generates a call - use explicit registers RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); @@ -2373,9 +2373,9 @@ static bool handleFmt22c(CompilationUnit *cUnit, MIR *mir) static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; int fieldOffset = mir->dalvikInsn.vC; - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_IGET_QUICK: case OP_IGET_OBJECT_QUICK: genIGet(cUnit, mir, kWord, fieldOffset, false); @@ -2403,7 +2403,7 @@ static bool handleFmt22cs(CompilationUnit *cUnit, MIR *mir) static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, ArmLIR *labelList) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; + Opcode dalvikOpcode = mir->dalvikInsn.opcode; ArmConditionCode cond; RegLocation rlSrc1 = dvmCompilerGetSrc(cUnit, mir, 0); RegLocation rlSrc2 = dvmCompilerGetSrc(cUnit, mir, 1); @@ -2412,7 +2412,7 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, rlSrc2 = loadValue(cUnit, rlSrc2, kCoreReg); opRegReg(cUnit, kOpCmp, rlSrc1.lowReg, rlSrc2.lowReg); - switch (dalvikOpCode) { + switch (dalvikOpcode) { case OP_IF_EQ: cond = kArmCondEq; break; @@ -2433,7 +2433,7 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, break; default: cond = 0; - LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpCode); + LOGE("Unexpected opcode (%d) for Fmt22t\n", dalvikOpcode); dvmCompilerAbort(cUnit); } genConditionalBranch(cUnit, cond, &labelList[bb->taken->id]); @@ -2444,9 +2444,9 @@ static bool handleFmt22t(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; - switch (opCode) { + switch (opcode) { case OP_MOVE_16: case OP_MOVE_OBJECT_16: case OP_MOVE_FROM16: @@ -2469,12 +2469,12 @@ static bool handleFmt22x_Fmt32x(CompilationUnit *cUnit, MIR *mir) static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; RegLocation rlSrc1; RegLocation rlSrc2; RegLocation rlDest; - if ( (opCode >= OP_ADD_INT) && (opCode <= OP_REM_DOUBLE)) { + if ( (opcode >= OP_ADD_INT) && (opcode <= OP_REM_DOUBLE)) { return genArithOp( cUnit, mir ); } @@ -2509,7 +2509,7 @@ static bool handleFmt23x(CompilationUnit *cUnit, MIR *mir) } - switch (opCode) { + switch (opcode) { case OP_CMPL_FLOAT: case OP_CMPG_FLOAT: case OP_CMPL_DOUBLE: @@ -2692,8 +2692,8 @@ static s8 findSparseSwitchIndex(const u2* switchData, int testVal, int pc) static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir) { - OpCode dalvikOpCode = mir->dalvikInsn.opCode; - switch (dalvikOpCode) { + Opcode dalvikOpcode = mir->dalvikInsn.opcode; + switch (dalvikOpcode) { case OP_FILL_ARRAY_DATA: { RegLocation rlSrc = dvmCompilerGetSrc(cUnit, mir, 0); // Making a call - use explicit registers @@ -2726,7 +2726,7 @@ static bool handleFmt31t(CompilationUnit *cUnit, MIR *mir) dvmCompilerFlushAllRegs(cUnit); /* Everything to home location */ loadValueDirectFixed(cUnit, rlSrc, r1); dvmCompilerLockAllTemps(cUnit); - if (dalvikOpCode == OP_PACKED_SWITCH) { + if (dalvikOpcode == OP_PACKED_SWITCH) { LOAD_FUNC_ADDR(cUnit, r4PC, (int)findPackedSwitchIndex); } else { LOAD_FUNC_ADDR(cUnit, r4PC, (int)findSparseSwitchIndex); @@ -2793,7 +2793,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, retChainingCell = &labelList[bb->fallThrough->id]; DecodedInstruction *dInsn = &mir->dalvikInsn; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { /* * calleeMethod = this->clazz->vtable[ * method->clazz->pDvmDex->pResMethods[BBBB]->methodIndex @@ -2815,7 +2815,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList); } - if (mir->dalvikInsn.opCode == OP_INVOKE_VIRTUAL) + if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -2838,7 +2838,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, cUnit->method->clazz->pDvmDex-> pResMethods[dInsn->vB]->methodIndex]); - if (mir->dalvikInsn.opCode == OP_INVOKE_SUPER) + if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -2858,7 +2858,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, assert(calleeMethod == cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]); - if (mir->dalvikInsn.opCode == OP_INVOKE_DIRECT) + if (mir->dalvikInsn.opcode == OP_INVOKE_DIRECT) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -2878,7 +2878,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, assert(calleeMethod == cUnit->method->clazz->pDvmDex->pResMethods[dInsn->vB]); - if (mir->dalvikInsn.opCode == OP_INVOKE_STATIC) + if (mir->dalvikInsn.opcode == OP_INVOKE_STATIC) genProcessArgsNoRange(cUnit, mir, dInsn, NULL /* no null check */); else @@ -2976,7 +2976,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList); } - if (mir->dalvikInsn.opCode == OP_INVOKE_INTERFACE) + if (mir->dalvikInsn.opcode == OP_INVOKE_INTERFACE) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -3009,7 +3009,7 @@ static bool handleFmt35c_3rc(CompilationUnit *cUnit, MIR *mir, BasicBlock *bb, if (pcrLabel == NULL) { int dPC = (int) (cUnit->method->insns + mir->offset); pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = dPC; pcrLabel->operands[1] = mir->offset; /* Insert the place holder to the growable list */ @@ -3136,7 +3136,7 @@ static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, return false; DecodedInstruction *dInsn = &mir->dalvikInsn; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { /* calleeMethod = this->clazz->vtable[BBBB] */ case OP_INVOKE_VIRTUAL_QUICK_RANGE: case OP_INVOKE_VIRTUAL_QUICK: { @@ -3151,7 +3151,7 @@ static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, genLandingPadForMispredictedCallee(cUnit, mir, bb, labelList); } - if (mir->dalvikInsn.opCode == OP_INVOKE_VIRTUAL_QUICK) + if (mir->dalvikInsn.opcode == OP_INVOKE_VIRTUAL_QUICK) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -3170,7 +3170,7 @@ static bool handleFmt35ms_3rms(CompilationUnit *cUnit, MIR *mir, assert(calleeMethod == cUnit->method->clazz->super->vtable[dInsn->vB]); - if (mir->dalvikInsn.opCode == OP_INVOKE_SUPER_QUICK) + if (mir->dalvikInsn.opcode == OP_INVOKE_SUPER_QUICK) genProcessArgsNoRange(cUnit, mir, dInsn, &pcrLabel); else genProcessArgsRange(cUnit, mir, dInsn, &pcrLabel); @@ -3366,7 +3366,7 @@ static bool genInlinedLongDoubleConversion(CompilationUnit *cUnit, MIR *mir) static bool handleExecuteInline(CompilationUnit *cUnit, MIR *mir) { DecodedInstruction *dInsn = &mir->dalvikInsn; - switch( mir->dalvikInsn.opCode) { + switch( mir->dalvikInsn.opcode) { case OP_EXECUTE_INLINE_RANGE: case OP_EXECUTE_INLINE: { unsigned int i; @@ -3831,13 +3831,13 @@ static void genValidationForPredictedInline(CompilationUnit *cUnit, MIR *mir) /* Extended MIR instructions like PHI */ static void handleExtendedMIR(CompilationUnit *cUnit, MIR *mir) { - int opOffset = mir->dalvikInsn.opCode - kMirOpFirst; + int opOffset = mir->dalvikInsn.opcode - kMirOpFirst; char *msg = dvmCompilerNew(strlen(extendedMIROpNames[opOffset]) + 1, false); strcpy(msg, extendedMIROpNames[opOffset]); newLIR1(cUnit, kArmPseudoExtended, (int) msg); - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case kMirOpPhi: { char *ssaString = dvmCompilerGetSSAString(cUnit, mir->ssaRep); newLIR1(cUnit, kArmPseudoSSARep, (int) ssaString); @@ -3881,7 +3881,7 @@ static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry, { /* Set up the place holder to reconstruct this Dalvik PC */ ArmLIR *pcrLabel = dvmCompilerNew(sizeof(ArmLIR), true); - pcrLabel->opCode = kArmPseudoPCReconstructionCell; + pcrLabel->opcode = kArmPseudoPCReconstructionCell; pcrLabel->operands[0] = (int) (cUnit->method->insns + entry->startOffset); pcrLabel->operands[1] = entry->startOffset; @@ -3893,13 +3893,13 @@ static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry, * other branch to the PCR cell to punt. */ ArmLIR *branchToBody = dvmCompilerNew(sizeof(ArmLIR), true); - branchToBody->opCode = kThumbBUncond; + branchToBody->opcode = kThumbBUncond; branchToBody->generic.target = (LIR *) bodyLabel; setupResourceMasks(branchToBody); cUnit->loopAnalysis->branchToBody = (LIR *) branchToBody; ArmLIR *branchToPCR = dvmCompilerNew(sizeof(ArmLIR), true); - branchToPCR->opCode = kThumbBUncond; + branchToPCR->opcode = kThumbBUncond; branchToPCR->generic.target = (LIR *) pcrLabel; setupResourceMasks(branchToPCR); cUnit->loopAnalysis->branchToPCR = (LIR *) branchToPCR; @@ -3909,7 +3909,7 @@ static void setupLoopEntryBlock(CompilationUnit *cUnit, BasicBlock *entry, static bool selfVerificationPuntOps(MIR *mir) { DecodedInstruction *decInsn = &mir->dalvikInsn; - OpCode op = decInsn->opCode; + Opcode op = decInsn->opcode; /* * All opcodes that can throw exceptions and use the @@ -3995,7 +3995,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) } if (blockList[i]->blockType == kTraceEntryBlock) { - labelList[i].opCode = kArmPseudoEntryBlock; + labelList[i].opcode = kArmPseudoEntryBlock; if (blockList[i]->firstMIRInsn == NULL) { continue; } else { @@ -4003,10 +4003,10 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) &labelList[blockList[i]->fallThrough->id]); } } else if (blockList[i]->blockType == kTraceExitBlock) { - labelList[i].opCode = kArmPseudoExitBlock; + labelList[i].opcode = kArmPseudoExitBlock; goto gen_fallthrough; } else if (blockList[i]->blockType == kDalvikByteCode) { - labelList[i].opCode = kArmPseudoNormalBlockLabel; + labelList[i].opcode = kArmPseudoNormalBlockLabel; /* Reset the register state */ dvmCompilerResetRegPool(cUnit); dvmCompilerClobberAllRegs(cUnit); @@ -4014,13 +4014,13 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) } else { switch (blockList[i]->blockType) { case kChainingCellNormal: - labelList[i].opCode = kArmPseudoChainingCellNormal; + labelList[i].opcode = kArmPseudoChainingCellNormal; /* handle the codegen later */ dvmInsertGrowableList( &chainingListByType[kChainingCellNormal], (void *) i); break; case kChainingCellInvokeSingleton: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellInvokeSingleton; labelList[i].operands[0] = (int) blockList[i]->containingMethod; @@ -4030,7 +4030,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) (void *) i); break; case kChainingCellInvokePredicted: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellInvokePredicted; /* handle the codegen later */ dvmInsertGrowableList( @@ -4038,7 +4038,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) (void *) i); break; case kChainingCellHot: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellHot; /* handle the codegen later */ dvmInsertGrowableList( @@ -4047,13 +4047,13 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) break; case kPCReconstruction: /* Make sure exception handling block is next */ - labelList[i].opCode = + labelList[i].opcode = kArmPseudoPCReconstructionBlockLabel; assert (i == cUnit->numBlocks - 2); handlePCReconstruction(cUnit, &labelList[i+1]); break; case kExceptionHandling: - labelList[i].opCode = kArmPseudoEHBlockLabel; + labelList[i].opcode = kArmPseudoEHBlockLabel; if (cUnit->pcReconstructionList.numUsed) { loadWordDisp(cUnit, rGLUE, offsetof(InterpState, jitToInterpEntries.dvmJitToInterpPunt), @@ -4063,7 +4063,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) break; #if defined(WITH_SELF_VERIFICATION) || defined(WITH_JIT_TUNING) case kChainingCellBackwardBranch: - labelList[i].opCode = + labelList[i].opcode = kArmPseudoChainingCellBackwardBranch; /* handle the codegen later */ dvmInsertGrowableList( @@ -4090,14 +4090,14 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) dvmCompilerResetDefTracking(cUnit); } - if (mir->dalvikInsn.opCode >= kMirOpFirst) { + if (mir->dalvikInsn.opcode >= kMirOpFirst) { handleExtendedMIR(cUnit, mir); continue; } - OpCode dalvikOpCode = mir->dalvikInsn.opCode; - InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpCode); + Opcode dalvikOpcode = mir->dalvikInsn.opcode; + InstructionFormat dalvikFormat = dexGetInstrFormat(dalvikOpcode); char *note; if (mir->OptimizationFlags & MIR_INLINED) { note = " (I)"; @@ -4131,7 +4131,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) * Debugging: screen the opcode first to see if it is in the * do[-not]-compile list */ - bool singleStepMe = SINGLE_STEP_OP(dalvikOpCode); + bool singleStepMe = SINGLE_STEP_OP(dalvikOpcode); #if defined(WITH_SELF_VERIFICATION) if (singleStepMe == false) { singleStepMe = selfVerificationPuntOps(mir); @@ -4141,7 +4141,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) notHandled = false; genInterpSingleStep(cUnit, mir); } else { - opcodeCoverage[dalvikOpCode]++; + opcodeCoverage[dalvikOpcode]++; switch (dalvikFormat) { case kFmt10t: case kFmt20t: @@ -4228,7 +4228,7 @@ void dvmCompilerMIR2LIR(CompilationUnit *cUnit) if (notHandled) { LOGE("%#06x: Opcode 0x%x (%s) / Fmt %d not handled\n", mir->offset, - dalvikOpCode, dexGetOpcodeName(dalvikOpCode), + dalvikOpcode, dexGetOpcodeName(dalvikOpcode), dalvikFormat); dvmCompilerAbort(cUnit); break; @@ -4426,9 +4426,9 @@ bool dvmCompilerArchInit() int i; for (i = 0; i < kArmLast; i++) { - if (EncodingMap[i].opCode != i) { + if (EncodingMap[i].opcode != i) { LOGE("Encoding order for %s is wrong: expecting %d, seeing %d", - EncodingMap[i].name, i, EncodingMap[i].opCode); + EncodingMap[i].name, i, EncodingMap[i].opcode); dvmAbort(); // OK to dvmAbort - build error } } diff --git a/vm/compiler/codegen/arm/FP/Thumb2VFP.c b/vm/compiler/codegen/arm/FP/Thumb2VFP.c index b5bcf994e..f0a51986e 100644 --- a/vm/compiler/codegen/arm/FP/Thumb2VFP.c +++ b/vm/compiler/codegen/arm/FP/Thumb2VFP.c @@ -25,7 +25,7 @@ static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, * Don't attempt to optimize register usage since these opcodes call out to * the handlers. */ - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_FLOAT_2ADDR: case OP_ADD_FLOAT: op = kThumb2Vadds; @@ -66,7 +66,7 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir, int op = kThumbBkpt; RegLocation rlResult; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_DOUBLE_2ADDR: case OP_ADD_DOUBLE: op = kThumb2Vaddd; @@ -109,7 +109,7 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir, static bool genConversion(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; int op = kThumbBkpt; bool longSrc = false; bool longDest = false; @@ -118,7 +118,7 @@ static bool genConversion(CompilationUnit *cUnit, MIR *mir) RegLocation rlDest; RegLocation rlResult; - switch (opCode) { + switch (opcode) { case OP_INT_TO_FLOAT: longSrc = false; longDest = false; @@ -213,7 +213,7 @@ static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest, int defaultResult; RegLocation rlResult; - switch(mir->dalvikInsn.opCode) { + switch(mir->dalvikInsn.opcode) { case OP_CMPL_FLOAT: isDouble = false; defaultResult = -1; diff --git a/vm/compiler/codegen/arm/FP/ThumbPortableFP.c b/vm/compiler/codegen/arm/FP/ThumbPortableFP.c index 957b4d41f..ef288ac67 100644 --- a/vm/compiler/codegen/arm/FP/ThumbPortableFP.c +++ b/vm/compiler/codegen/arm/FP/ThumbPortableFP.c @@ -57,7 +57,7 @@ static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest, * Don't attempt to optimize register usage since these opcodes call out to * the handlers. */ - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_CMPL_FLOAT: loadValueDirectFixed(cUnit, rlSrc1, r0); loadValueDirectFixed(cUnit, rlSrc2, r1); diff --git a/vm/compiler/codegen/arm/FP/ThumbVFP.c b/vm/compiler/codegen/arm/FP/ThumbVFP.c index db940b053..9bfcd5555 100644 --- a/vm/compiler/codegen/arm/FP/ThumbVFP.c +++ b/vm/compiler/codegen/arm/FP/ThumbVFP.c @@ -65,28 +65,28 @@ static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2) { - TemplateOpCode opCode; + TemplateOpcode opcode; /* * Don't attempt to optimize register usage since these opcodes call out to * the handlers. */ - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_FLOAT_2ADDR: case OP_ADD_FLOAT: - opCode = TEMPLATE_ADD_FLOAT_VFP; + opcode = TEMPLATE_ADD_FLOAT_VFP; break; case OP_SUB_FLOAT_2ADDR: case OP_SUB_FLOAT: - opCode = TEMPLATE_SUB_FLOAT_VFP; + opcode = TEMPLATE_SUB_FLOAT_VFP; break; case OP_DIV_FLOAT_2ADDR: case OP_DIV_FLOAT: - opCode = TEMPLATE_DIV_FLOAT_VFP; + opcode = TEMPLATE_DIV_FLOAT_VFP; break; case OP_MUL_FLOAT_2ADDR: case OP_MUL_FLOAT: - opCode = TEMPLATE_MUL_FLOAT_VFP; + opcode = TEMPLATE_MUL_FLOAT_VFP; break; case OP_REM_FLOAT_2ADDR: case OP_REM_FLOAT: @@ -99,7 +99,7 @@ static bool genArithOpFloat(CompilationUnit *cUnit, MIR *mir, loadValueAddressDirect(cUnit, rlDest, r0); loadValueAddressDirect(cUnit, rlSrc1, r1); loadValueAddressDirect(cUnit, rlSrc2, r2); - genDispatchToHandler(cUnit, opCode); + genDispatchToHandler(cUnit, opcode); rlDest = dvmCompilerUpdateLoc(cUnit, rlDest); if (rlDest.location == kLocPhysReg) { dvmCompilerClobber(cUnit, rlDest.lowReg); @@ -111,24 +111,24 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2) { - TemplateOpCode opCode; + TemplateOpcode opcode; - switch (mir->dalvikInsn.opCode) { + switch (mir->dalvikInsn.opcode) { case OP_ADD_DOUBLE_2ADDR: case OP_ADD_DOUBLE: - opCode = TEMPLATE_ADD_DOUBLE_VFP; + opcode = TEMPLATE_ADD_DOUBLE_VFP; break; case OP_SUB_DOUBLE_2ADDR: case OP_SUB_DOUBLE: - opCode = TEMPLATE_SUB_DOUBLE_VFP; + opcode = TEMPLATE_SUB_DOUBLE_VFP; break; case OP_DIV_DOUBLE_2ADDR: case OP_DIV_DOUBLE: - opCode = TEMPLATE_DIV_DOUBLE_VFP; + opcode = TEMPLATE_DIV_DOUBLE_VFP; break; case OP_MUL_DOUBLE_2ADDR: case OP_MUL_DOUBLE: - opCode = TEMPLATE_MUL_DOUBLE_VFP; + opcode = TEMPLATE_MUL_DOUBLE_VFP; break; case OP_REM_DOUBLE_2ADDR: case OP_REM_DOUBLE: @@ -142,7 +142,7 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir, loadValueAddressDirect(cUnit, rlDest, r0); loadValueAddressDirect(cUnit, rlSrc1, r1); loadValueAddressDirect(cUnit, rlSrc2, r2); - genDispatchToHandler(cUnit, opCode); + genDispatchToHandler(cUnit, opcode); rlDest = dvmCompilerUpdateLocWide(cUnit, rlDest); if (rlDest.location == kLocPhysReg) { dvmCompilerClobber(cUnit, rlDest.lowReg); @@ -153,13 +153,13 @@ static bool genArithOpDouble(CompilationUnit *cUnit, MIR *mir, static bool genConversion(CompilationUnit *cUnit, MIR *mir) { - OpCode opCode = mir->dalvikInsn.opCode; + Opcode opcode = mir->dalvikInsn.opcode; bool longSrc = false; bool longDest = false; RegLocation rlSrc; RegLocation rlDest; - TemplateOpCode template; - switch (opCode) { + TemplateOpcode template; + switch (opcode) { case OP_INT_TO_FLOAT: longSrc = false; longDest = false; @@ -226,11 +226,11 @@ static bool genConversion(CompilationUnit *cUnit, MIR *mir) static bool genCmpFP(CompilationUnit *cUnit, MIR *mir, RegLocation rlDest, RegLocation rlSrc1, RegLocation rlSrc2) { - TemplateOpCode template; + TemplateOpcode template; RegLocation rlResult = dvmCompilerGetReturn(cUnit); bool wide = true; - switch(mir->dalvikInsn.opCode) { + switch(mir->dalvikInsn.opcode) { case OP_CMPL_FLOAT: template = TEMPLATE_CMPL_FLOAT_VFP; wide = false; diff --git a/vm/compiler/codegen/arm/GlobalOptimizations.c b/vm/compiler/codegen/arm/GlobalOptimizations.c index 1cfa32b3a..c1e69c3e3 100644 --- a/vm/compiler/codegen/arm/GlobalOptimizations.c +++ b/vm/compiler/codegen/arm/GlobalOptimizations.c @@ -31,7 +31,7 @@ static void applyRedundantBranchElimination(CompilationUnit *cUnit) thisLIR = NEXT_LIR(thisLIR)) { /* Branch to the next instruction */ - if (thisLIR->opCode == kThumbBUncond) { + if (thisLIR->opcode == kThumbBUncond) { ArmLIR *nextLIR = thisLIR; while (true) { @@ -48,7 +48,7 @@ static void applyRedundantBranchElimination(CompilationUnit *cUnit) /* * Found real useful stuff between the branch and the target */ - if (!isPseudoOpCode(nextLIR->opCode)) + if (!isPseudoOpcode(nextLIR->opcode)) break; } } diff --git a/vm/compiler/codegen/arm/LocalOptimizations.c b/vm/compiler/codegen/arm/LocalOptimizations.c index 724fdb7ad..33e1e4188 100644 --- a/vm/compiler/codegen/arm/LocalOptimizations.c +++ b/vm/compiler/codegen/arm/LocalOptimizations.c @@ -165,7 +165,7 @@ static void applyLoadStoreElimination(CompilationUnit *cUnit, /* * Saw a real instruction that the store can be sunk after */ - if (!isPseudoOpCode(checkLIR->opCode)) { + if (!isPseudoOpcode(checkLIR->opcode)) { sinkDistance++; } } @@ -196,7 +196,7 @@ static void applyLoadHoisting(CompilationUnit *cUnit, continue; } - if (firstLoad && (EncodingMap[thisLIR->opCode].flags & IS_LOAD)) { + if (firstLoad && (EncodingMap[thisLIR->opcode].flags & IS_LOAD)) { /* * Ensure nothing will be hoisted in front of this load because * it's result will likely be needed soon. @@ -388,7 +388,7 @@ static void applyLoadHoisting(CompilationUnit *cUnit, * Saw a real instruction that hosting the load is * beneficial */ - if (!isPseudoOpCode(checkLIR->opCode)) { + if (!isPseudoOpcode(checkLIR->opcode)) { hoistDistance++; } } @@ -491,7 +491,7 @@ static void applyLoadHoisting(CompilationUnit *cUnit, * Saw a real instruction that hosting the load is * beneficial */ - if (!isPseudoOpCode(checkLIR->opCode)) { + if (!isPseudoOpcode(checkLIR->opcode)) { hoistDistance++; } } diff --git a/vm/compiler/codegen/arm/Thumb/Factory.c b/vm/compiler/codegen/arm/Thumb/Factory.c index e18aa75fe..af255a939 100644 --- a/vm/compiler/codegen/arm/Thumb/Factory.c +++ b/vm/compiler/codegen/arm/Thumb/Factory.c @@ -74,7 +74,7 @@ static ArmLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, dataTarget = addWordData(cUnit, value, false); } ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true); - loadPcRel->opCode = kThumbLdrPcRel; + loadPcRel->opcode = kThumbLdrPcRel; loadPcRel->generic.target = (LIR *) dataTarget; loadPcRel->operands[0] = tDest; setupResourceMasks(loadPcRel); @@ -121,16 +121,16 @@ static ArmLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value) static ArmLIR *opNone(CompilationUnit *cUnit, OpKind op) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpUncondBr: - opCode = kThumbBUncond; + opcode = kThumbBUncond; break; default: LOGE("Jit: bad case in opNone"); dvmCompilerAbort(cUnit); } - return newLIR0(cUnit, opCode); + return newLIR0(cUnit, opcode); } static ArmLIR *opCondBranch(CompilationUnit *cUnit, ArmConditionCode cc) @@ -140,33 +140,33 @@ static ArmLIR *opCondBranch(CompilationUnit *cUnit, ArmConditionCode cc) static ArmLIR *opImm(CompilationUnit *cUnit, OpKind op, int value) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpPush: - opCode = kThumbPush; + opcode = kThumbPush; break; case kOpPop: - opCode = kThumbPop; + opcode = kThumbPop; break; default: LOGE("Jit: bad case in opCondBranch"); dvmCompilerAbort(cUnit); } - return newLIR1(cUnit, opCode, value); + return newLIR1(cUnit, opcode, value); } static ArmLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpBlx: - opCode = kThumbBlxR; + opcode = kThumbBlxR; break; default: LOGE("Jit: bad case in opReg"); dvmCompilerAbort(cUnit); } - return newLIR1(cUnit, opCode, rDestSrc); + return newLIR1(cUnit, opcode, rDestSrc); } static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, @@ -176,36 +176,36 @@ static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, bool neg = (value < 0); int absValue = (neg) ? -value : value; bool shortForm = (absValue & 0xff) == absValue; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpAdd: if ( !neg && (rDestSrc1 == 13) && (value <= 508)) { /* sp */ assert((value & 0x3) == 0); return newLIR1(cUnit, kThumbAddSpI7, value >> 2); } else if (shortForm) { - opCode = (neg) ? kThumbSubRI8 : kThumbAddRI8; + opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; } else - opCode = kThumbAddRRR; + opcode = kThumbAddRRR; break; case kOpSub: if (!neg && (rDestSrc1 == 13) && (value <= 508)) { /* sp */ assert((value & 0x3) == 0); return newLIR1(cUnit, kThumbSubSpI7, value >> 2); } else if (shortForm) { - opCode = (neg) ? kThumbAddRI8 : kThumbSubRI8; + opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; } else - opCode = kThumbSubRRR; + opcode = kThumbSubRRR; break; case kOpCmp: if (neg) shortForm = false; if (LOWREG(rDestSrc1) && shortForm) { - opCode = kThumbCmpRI8; + opcode = kThumbCmpRI8; } else if (LOWREG(rDestSrc1)) { - opCode = kThumbCmpRR; + opcode = kThumbCmpRR; } else { shortForm = false; - opCode = kThumbCmpHL; + opcode = kThumbCmpHL; } break; default: @@ -214,14 +214,14 @@ static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, break; } if (shortForm) - res = newLIR2(cUnit, opCode, rDestSrc1, absValue); + res = newLIR2(cUnit, opcode, rDestSrc1, absValue); else { int rScratch = dvmCompilerAllocTemp(cUnit); res = loadConstant(cUnit, rScratch, value); if (op == kOpCmp) - newLIR2(cUnit, opCode, rDestSrc1, rScratch); + newLIR2(cUnit, opcode, rDestSrc1, rScratch); else - newLIR3(cUnit, opCode, rDestSrc1, rDestSrc1, rScratch); + newLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rScratch); } return res; } @@ -229,13 +229,13 @@ static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int rSrc2) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpAdd: - opCode = kThumbAddRRR; + opcode = kThumbAddRRR; break; case kOpSub: - opCode = kThumbSubRRR; + opcode = kThumbSubRRR; break; default: if (rDest == rSrc1) { @@ -251,7 +251,7 @@ static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest, } break; } - return newLIR3(cUnit, opCode, rDest, rSrc1, rSrc2); + return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2); } static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, @@ -260,7 +260,7 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, ArmLIR *res; bool neg = (value < 0); int absValue = (neg) ? -value : value; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool shortForm = (absValue & 0x7) == absValue; switch(op) { case kOpAdd: @@ -269,52 +269,52 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, if ((rSrc1 == 13) && (value <= 1020)) { /* sp */ assert((value & 0x3) == 0); shortForm = true; - opCode = kThumbAddSpRel; + opcode = kThumbAddSpRel; value >>= 2; } else if ((rSrc1 == 15) && (value <= 1020)) { /* pc */ assert((value & 0x3) == 0); shortForm = true; - opCode = kThumbAddPcRel; + opcode = kThumbAddPcRel; value >>= 2; } else if (shortForm) { - opCode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; + opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; } else if ((absValue > 0) && (absValue <= (255 + 7))) { /* Two shots - 1st handle the 7 */ - opCode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; - res = newLIR3(cUnit, opCode, rDest, rSrc1, 7); - opCode = (neg) ? kThumbSubRI8 : kThumbAddRI8; - newLIR2(cUnit, opCode, rDest, absValue - 7); + opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; + res = newLIR3(cUnit, opcode, rDest, rSrc1, 7); + opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; + newLIR2(cUnit, opcode, rDest, absValue - 7); return res; } else - opCode = kThumbAddRRR; + opcode = kThumbAddRRR; break; case kOpSub: if (rDest == rSrc1) return opRegImm(cUnit, op, rDest, value); if (shortForm) { - opCode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; + opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; } else if ((absValue > 0) && (absValue <= (255 + 7))) { /* Two shots - 1st handle the 7 */ - opCode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; - res = newLIR3(cUnit, opCode, rDest, rSrc1, 7); - opCode = (neg) ? kThumbAddRI8 : kThumbSubRI8; - newLIR2(cUnit, opCode, rDest, absValue - 7); + opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; + res = newLIR3(cUnit, opcode, rDest, rSrc1, 7); + opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; + newLIR2(cUnit, opcode, rDest, absValue - 7); return res; } else - opCode = kThumbSubRRR; + opcode = kThumbSubRRR; break; case kOpLsl: shortForm = (!neg && value <= 31); - opCode = kThumbLslRRI5; + opcode = kThumbLslRRI5; break; case kOpLsr: shortForm = (!neg && value <= 31); - opCode = kThumbLsrRRI5; + opcode = kThumbLsrRRI5; break; case kOpAsr: shortForm = (!neg && value <= 31); - opCode = kThumbAsrRRI5; + opcode = kThumbAsrRRI5; break; case kOpMul: case kOpAnd: @@ -335,15 +335,15 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, break; } if (shortForm) - res = newLIR3(cUnit, opCode, rDest, rSrc1, absValue); + res = newLIR3(cUnit, opcode, rDest, rSrc1, absValue); else { if (rDest != rSrc1) { res = loadConstant(cUnit, rDest, value); - newLIR3(cUnit, opCode, rDest, rSrc1, rDest); + newLIR3(cUnit, opcode, rDest, rSrc1, rDest); } else { int rScratch = dvmCompilerAllocTemp(cUnit); res = loadConstant(cUnit, rScratch, value); - newLIR3(cUnit, opCode, rDest, rSrc1, rScratch); + newLIR3(cUnit, opcode, rDest, rSrc1, rScratch); } } return res; @@ -353,65 +353,65 @@ static ArmLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2) { ArmLIR *res; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpAdc: - opCode = kThumbAdcRR; + opcode = kThumbAdcRR; break; case kOpAnd: - opCode = kThumbAndRR; + opcode = kThumbAndRR; break; case kOpBic: - opCode = kThumbBicRR; + opcode = kThumbBicRR; break; case kOpCmn: - opCode = kThumbCmnRR; + opcode = kThumbCmnRR; break; case kOpCmp: - opCode = kThumbCmpRR; + opcode = kThumbCmpRR; break; case kOpXor: - opCode = kThumbEorRR; + opcode = kThumbEorRR; break; case kOpMov: if (LOWREG(rDestSrc1) && LOWREG(rSrc2)) - opCode = kThumbMovRR; + opcode = kThumbMovRR; else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2)) - opCode = kThumbMovRR_H2H; + opcode = kThumbMovRR_H2H; else if (LOWREG(rDestSrc1)) - opCode = kThumbMovRR_H2L; + opcode = kThumbMovRR_H2L; else - opCode = kThumbMovRR_L2H; + opcode = kThumbMovRR_L2H; break; case kOpMul: - opCode = kThumbMul; + opcode = kThumbMul; break; case kOpMvn: - opCode = kThumbMvn; + opcode = kThumbMvn; break; case kOpNeg: - opCode = kThumbNeg; + opcode = kThumbNeg; break; case kOpOr: - opCode = kThumbOrr; + opcode = kThumbOrr; break; case kOpSbc: - opCode = kThumbSbc; + opcode = kThumbSbc; break; case kOpTst: - opCode = kThumbTst; + opcode = kThumbTst; break; case kOpLsl: - opCode = kThumbLslRR; + opcode = kThumbLslRR; break; case kOpLsr: - opCode = kThumbLsrRR; + opcode = kThumbLsrRR; break; case kOpAsr: - opCode = kThumbAsrRR; + opcode = kThumbAsrRR; break; case kOpRor: - opCode = kThumbRorRR; + opcode = kThumbRorRR; case kOpAdd: case kOpSub: return opRegRegReg(cUnit, op, rDestSrc1, rDestSrc1, rSrc2); @@ -432,7 +432,7 @@ static ArmLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, dvmCompilerAbort(cUnit); break; } - return newLIR2(cUnit, opCode, rDestSrc1, rSrc2); + return newLIR2(cUnit, opcode, rDestSrc1, rSrc2); } static ArmLIR *loadConstantValueWide(CompilationUnit *cUnit, int rDestLo, @@ -450,7 +450,7 @@ static ArmLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase, { ArmLIR *first = NULL; ArmLIR *res; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; int rNewIndex = rIndex; if (scale) { // Scale the index, but can't trash the original. @@ -459,25 +459,25 @@ static ArmLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase, } switch (size) { case kWord: - opCode = kThumbLdrRRR; + opcode = kThumbLdrRRR; break; case kUnsignedHalf: - opCode = kThumbLdrhRRR; + opcode = kThumbLdrhRRR; break; case kSignedHalf: - opCode = kThumbLdrshRRR; + opcode = kThumbLdrshRRR; break; case kUnsignedByte: - opCode = kThumbLdrbRRR; + opcode = kThumbLdrbRRR; break; case kSignedByte: - opCode = kThumbLdrsbRRR; + opcode = kThumbLdrsbRRR; break; default: LOGE("Jit: bad case in loadBaseIndexed"); dvmCompilerAbort(cUnit); } - res = newLIR3(cUnit, opCode, rDest, rBase, rNewIndex); + res = newLIR3(cUnit, opcode, rDest, rBase, rNewIndex); #if defined(WITH_SELF_VERIFICATION) if (cUnit->heapMemOp) res->branchInsertSV = true; @@ -493,7 +493,7 @@ static ArmLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase, { ArmLIR *first = NULL; ArmLIR *res; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; int rNewIndex = rIndex; if (scale) { rNewIndex = dvmCompilerAllocTemp(cUnit); @@ -501,21 +501,21 @@ static ArmLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase, } switch (size) { case kWord: - opCode = kThumbStrRRR; + opcode = kThumbStrRRR; break; case kUnsignedHalf: case kSignedHalf: - opCode = kThumbStrhRRR; + opcode = kThumbStrhRRR; break; case kUnsignedByte: case kSignedByte: - opCode = kThumbStrbRRR; + opcode = kThumbStrbRRR; break; default: LOGE("Jit: bad case in storeBaseIndexed"); dvmCompilerAbort(cUnit); } - res = newLIR3(cUnit, opCode, rSrc, rBase, rNewIndex); + res = newLIR3(cUnit, opcode, rSrc, rBase, rNewIndex); #if defined(WITH_SELF_VERIFICATION) if (cUnit->heapMemOp) res->branchInsertSV = true; @@ -566,7 +566,7 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, ArmLIR *res; ArmLIR *load = NULL; ArmLIR *load2 = NULL; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool shortForm = false; int encodedDisp = displacement; bool pair = false; @@ -579,9 +579,9 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, assert((displacement & 0x3) == 0); shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrRRI5; + opcode = kThumbLdrRRI5; } else { - opCode = kThumbLdrRRR; + opcode = kThumbLdrRRR; } break; case kWord: @@ -589,19 +589,19 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, (displacement <= 1020) && (displacement >= 0)) { shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrPcRel; + opcode = kThumbLdrPcRel; } else if (LOWREG(rDest) && (rBase == r13) && (displacement <= 1020) && (displacement >= 0)) { shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrSpRel; + opcode = kThumbLdrSpRel; } else if (displacement < 128 && displacement >= 0) { assert((displacement & 0x3) == 0); shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrRRI5; + opcode = kThumbLdrRRI5; } else { - opCode = kThumbLdrRRR; + opcode = kThumbLdrRRR; } break; case kUnsignedHalf: @@ -609,33 +609,33 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, assert((displacement & 0x1) == 0); shortForm = true; encodedDisp >>= 1; - opCode = kThumbLdrhRRI5; + opcode = kThumbLdrhRRI5; } else { - opCode = kThumbLdrhRRR; + opcode = kThumbLdrhRRR; } break; case kSignedHalf: - opCode = kThumbLdrshRRR; + opcode = kThumbLdrshRRR; break; case kUnsignedByte: if (displacement < 32 && displacement >= 0) { shortForm = true; - opCode = kThumbLdrbRRI5; + opcode = kThumbLdrbRRI5; } else { - opCode = kThumbLdrbRRR; + opcode = kThumbLdrbRRR; } break; case kSignedByte: - opCode = kThumbLdrsbRRR; + opcode = kThumbLdrsbRRR; break; default: LOGE("Jit: bad case in loadBaseIndexedBody"); dvmCompilerAbort(cUnit); } if (shortForm) { - load = res = newLIR3(cUnit, opCode, rDest, rBase, encodedDisp); + load = res = newLIR3(cUnit, opcode, rDest, rBase, encodedDisp); if (pair) { - load2 = newLIR3(cUnit, opCode, rDestHi, rBase, encodedDisp+1); + load2 = newLIR3(cUnit, opcode, rDestHi, rBase, encodedDisp+1); } } else { if (pair) { @@ -648,7 +648,7 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, int rTmp = (rBase == rDest) ? dvmCompilerAllocFreeTemp(cUnit) : rDest; res = loadConstant(cUnit, rTmp, displacement); - load = newLIR3(cUnit, opCode, rDest, rBase, rTmp); + load = newLIR3(cUnit, opcode, rDest, rBase, rTmp); if (rBase == rFP) annotateDalvikRegAccess(load, displacement >> 2, true /* isLoad */); @@ -696,7 +696,7 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, ArmLIR *res; ArmLIR *store = NULL; ArmLIR *store2 = NULL; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool shortForm = false; int encodedDisp = displacement; bool pair = false; @@ -710,9 +710,9 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, pair = true; shortForm = true; encodedDisp >>= 2; - opCode = kThumbStrRRI5; + opcode = kThumbStrRRI5; } else { - opCode = kThumbStrRRR; + opcode = kThumbStrRRR; } break; case kWord: @@ -720,9 +720,9 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, assert((displacement & 0x3) == 0); shortForm = true; encodedDisp >>= 2; - opCode = kThumbStrRRI5; + opcode = kThumbStrRRI5; } else { - opCode = kThumbStrRRR; + opcode = kThumbStrRRR; } break; case kUnsignedHalf: @@ -731,18 +731,18 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, assert((displacement & 0x1) == 0); shortForm = true; encodedDisp >>= 1; - opCode = kThumbStrhRRI5; + opcode = kThumbStrhRRI5; } else { - opCode = kThumbStrhRRR; + opcode = kThumbStrhRRR; } break; case kUnsignedByte: case kSignedByte: if (displacement < 32 && displacement >= 0) { shortForm = true; - opCode = kThumbStrbRRI5; + opcode = kThumbStrbRRI5; } else { - opCode = kThumbStrbRRR; + opcode = kThumbStrbRRR; } break; default: @@ -750,9 +750,9 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, dvmCompilerAbort(cUnit); } if (shortForm) { - store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp); + store = res = newLIR3(cUnit, opcode, rSrc, rBase, encodedDisp); if (pair) { - store2 = newLIR3(cUnit, opCode, rSrcHi, rBase, encodedDisp + 1); + store2 = newLIR3(cUnit, opcode, rSrcHi, rBase, encodedDisp + 1); } } else { int rScratch = dvmCompilerAllocTemp(cUnit); @@ -762,7 +762,7 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, store2 = newLIR3(cUnit, kThumbStrRRI5, rSrcHi, rScratch, 1); } else { res = loadConstant(cUnit, rScratch, displacement); - store = newLIR3(cUnit, opCode, rSrc, rBase, rScratch); + store = newLIR3(cUnit, opcode, rSrc, rBase, rScratch); } dvmCompilerFreeTemp(cUnit, rScratch); } @@ -818,20 +818,20 @@ static void loadPair(CompilationUnit *cUnit, int base, int lowReg, int highReg) static ArmLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) { ArmLIR* res; - ArmOpCode opCode; + ArmOpcode opcode; res = dvmCompilerNew(sizeof(ArmLIR), true); if (LOWREG(rDest) && LOWREG(rSrc)) - opCode = kThumbMovRR; + opcode = kThumbMovRR; else if (!LOWREG(rDest) && !LOWREG(rSrc)) - opCode = kThumbMovRR_H2H; + opcode = kThumbMovRR_H2H; else if (LOWREG(rDest)) - opCode = kThumbMovRR_H2L; + opcode = kThumbMovRR_H2L; else - opCode = kThumbMovRR_L2H; + opcode = kThumbMovRR_L2H; res->operands[0] = rDest; res->operands[1] = rSrc; - res->opCode = opCode; + res->opcode = opcode; setupResourceMasks(res); if (rDest == rSrc) { res->isNop = true; diff --git a/vm/compiler/codegen/arm/Thumb2/Factory.c b/vm/compiler/codegen/arm/Thumb2/Factory.c index 5074e425b..141c925fa 100644 --- a/vm/compiler/codegen/arm/Thumb2/Factory.c +++ b/vm/compiler/codegen/arm/Thumb2/Factory.c @@ -61,7 +61,7 @@ static ArmLIR *loadFPConstantValue(CompilationUnit *cUnit, int rDest, dataTarget = addWordData(cUnit, value, false); } ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true); - loadPcRel->opCode = kThumb2Vldrs; + loadPcRel->opcode = kThumb2Vldrs; loadPcRel->generic.target = (LIR *) dataTarget; loadPcRel->operands[0] = rDest; loadPcRel->operands[1] = rpc; @@ -171,7 +171,7 @@ static ArmLIR *loadConstantNoClobber(CompilationUnit *cUnit, int rDest, dataTarget = addWordData(cUnit, value, false); } ArmLIR *loadPcRel = dvmCompilerNew(sizeof(ArmLIR), true); - loadPcRel->opCode = kThumb2LdrPcRel12; + loadPcRel->opcode = kThumb2LdrPcRel12; loadPcRel->generic.target = (LIR *) dataTarget; loadPcRel->operands[0] = rDest; setupResourceMasks(loadPcRel); @@ -214,15 +214,15 @@ static ArmLIR *loadConstant(CompilationUnit *cUnit, int rDest, int value) static ArmLIR *opNone(CompilationUnit *cUnit, OpKind op) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpUncondBr: - opCode = kThumbBUncond; + opcode = kThumbBUncond; break; default: assert(0); } - return newLIR0(cUnit, opCode); + return newLIR0(cUnit, opcode); } static ArmLIR *opCondBranch(CompilationUnit *cUnit, ArmConditionCode cc) @@ -232,119 +232,119 @@ static ArmLIR *opCondBranch(CompilationUnit *cUnit, ArmConditionCode cc) static ArmLIR *opImm(CompilationUnit *cUnit, OpKind op, int value) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpPush: - opCode = ((value & 0xff00) != 0) ? kThumb2Push : kThumbPush; + opcode = ((value & 0xff00) != 0) ? kThumb2Push : kThumbPush; break; case kOpPop: - opCode = ((value & 0xff00) != 0) ? kThumb2Pop : kThumbPop; + opcode = ((value & 0xff00) != 0) ? kThumb2Pop : kThumbPop; break; default: assert(0); } - return newLIR1(cUnit, opCode, value); + return newLIR1(cUnit, opcode, value); } static ArmLIR *opReg(CompilationUnit *cUnit, OpKind op, int rDestSrc) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpBlx: - opCode = kThumbBlxR; + opcode = kThumbBlxR; break; default: assert(0); } - return newLIR1(cUnit, opCode, rDestSrc); + return newLIR1(cUnit, opcode, rDestSrc); } static ArmLIR *opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1, int rSrc2, int shift) { bool thumbForm = ((shift == 0) && LOWREG(rDestSrc1) && LOWREG(rSrc2)); - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpAdc: - opCode = (thumbForm) ? kThumbAdcRR : kThumb2AdcRRR; + opcode = (thumbForm) ? kThumbAdcRR : kThumb2AdcRRR; break; case kOpAnd: - opCode = (thumbForm) ? kThumbAndRR : kThumb2AndRRR; + opcode = (thumbForm) ? kThumbAndRR : kThumb2AndRRR; break; case kOpBic: - opCode = (thumbForm) ? kThumbBicRR : kThumb2BicRRR; + opcode = (thumbForm) ? kThumbBicRR : kThumb2BicRRR; break; case kOpCmn: assert(shift == 0); - opCode = (thumbForm) ? kThumbCmnRR : kThumb2CmnRR; + opcode = (thumbForm) ? kThumbCmnRR : kThumb2CmnRR; break; case kOpCmp: if (thumbForm) - opCode = kThumbCmpRR; + opcode = kThumbCmpRR; else if ((shift == 0) && !LOWREG(rDestSrc1) && !LOWREG(rSrc2)) - opCode = kThumbCmpHH; + opcode = kThumbCmpHH; else if ((shift == 0) && LOWREG(rDestSrc1)) - opCode = kThumbCmpLH; + opcode = kThumbCmpLH; else if (shift == 0) - opCode = kThumbCmpHL; + opcode = kThumbCmpHL; else - opCode = kThumb2CmpRR; + opcode = kThumb2CmpRR; break; case kOpXor: - opCode = (thumbForm) ? kThumbEorRR : kThumb2EorRRR; + opcode = (thumbForm) ? kThumbEorRR : kThumb2EorRRR; break; case kOpMov: assert(shift == 0); if (LOWREG(rDestSrc1) && LOWREG(rSrc2)) - opCode = kThumbMovRR; + opcode = kThumbMovRR; else if (!LOWREG(rDestSrc1) && !LOWREG(rSrc2)) - opCode = kThumbMovRR_H2H; + opcode = kThumbMovRR_H2H; else if (LOWREG(rDestSrc1)) - opCode = kThumbMovRR_H2L; + opcode = kThumbMovRR_H2L; else - opCode = kThumbMovRR_L2H; + opcode = kThumbMovRR_L2H; break; case kOpMul: assert(shift == 0); - opCode = (thumbForm) ? kThumbMul : kThumb2MulRRR; + opcode = (thumbForm) ? kThumbMul : kThumb2MulRRR; break; case kOpMvn: - opCode = (thumbForm) ? kThumbMvn : kThumb2MnvRR; + opcode = (thumbForm) ? kThumbMvn : kThumb2MnvRR; break; case kOpNeg: assert(shift == 0); - opCode = (thumbForm) ? kThumbNeg : kThumb2NegRR; + opcode = (thumbForm) ? kThumbNeg : kThumb2NegRR; break; case kOpOr: - opCode = (thumbForm) ? kThumbOrr : kThumb2OrrRRR; + opcode = (thumbForm) ? kThumbOrr : kThumb2OrrRRR; break; case kOpSbc: - opCode = (thumbForm) ? kThumbSbc : kThumb2SbcRRR; + opcode = (thumbForm) ? kThumbSbc : kThumb2SbcRRR; break; case kOpTst: - opCode = (thumbForm) ? kThumbTst : kThumb2TstRR; + opcode = (thumbForm) ? kThumbTst : kThumb2TstRR; break; case kOpLsl: assert(shift == 0); - opCode = (thumbForm) ? kThumbLslRR : kThumb2LslRRR; + opcode = (thumbForm) ? kThumbLslRR : kThumb2LslRRR; break; case kOpLsr: assert(shift == 0); - opCode = (thumbForm) ? kThumbLsrRR : kThumb2LsrRRR; + opcode = (thumbForm) ? kThumbLsrRR : kThumb2LsrRRR; break; case kOpAsr: assert(shift == 0); - opCode = (thumbForm) ? kThumbAsrRR : kThumb2AsrRRR; + opcode = (thumbForm) ? kThumbAsrRR : kThumb2AsrRRR; break; case kOpRor: assert(shift == 0); - opCode = (thumbForm) ? kThumbRorRR : kThumb2RorRRR; + opcode = (thumbForm) ? kThumbRorRR : kThumb2RorRRR; break; case kOpAdd: - opCode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR; + opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR; break; case kOpSub: - opCode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR; + opcode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR; break; case kOp2Byte: assert(shift == 0); @@ -359,16 +359,16 @@ static ArmLIR *opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1, assert(0); break; } - assert(opCode >= 0); - if (EncodingMap[opCode].flags & IS_BINARY_OP) - return newLIR2(cUnit, opCode, rDestSrc1, rSrc2); - else if (EncodingMap[opCode].flags & IS_TERTIARY_OP) { - if (EncodingMap[opCode].fieldLoc[2].kind == kFmtShift) - return newLIR3(cUnit, opCode, rDestSrc1, rSrc2, shift); + assert(opcode >= 0); + if (EncodingMap[opcode].flags & IS_BINARY_OP) + return newLIR2(cUnit, opcode, rDestSrc1, rSrc2); + else if (EncodingMap[opcode].flags & IS_TERTIARY_OP) { + if (EncodingMap[opcode].fieldLoc[2].kind == kFmtShift) + return newLIR3(cUnit, opcode, rDestSrc1, rSrc2, shift); else - return newLIR3(cUnit, opCode, rDestSrc1, rDestSrc1, rSrc2); - } else if (EncodingMap[opCode].flags & IS_QUAD_OP) - return newLIR4(cUnit, opCode, rDestSrc1, rDestSrc1, rSrc2, shift); + return newLIR3(cUnit, opcode, rDestSrc1, rDestSrc1, rSrc2); + } else if (EncodingMap[opcode].flags & IS_QUAD_OP) + return newLIR4(cUnit, opcode, rDestSrc1, rDestSrc1, rSrc2, shift); else { assert(0); return NULL; @@ -384,64 +384,64 @@ static ArmLIR *opRegReg(CompilationUnit *cUnit, OpKind op, int rDestSrc1, static ArmLIR *opRegRegRegShift(CompilationUnit *cUnit, OpKind op, int rDest, int rSrc1, int rSrc2, int shift) { - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool thumbForm = (shift == 0) && LOWREG(rDest) && LOWREG(rSrc1) && LOWREG(rSrc2); switch (op) { case kOpAdd: - opCode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR; + opcode = (thumbForm) ? kThumbAddRRR : kThumb2AddRRR; break; case kOpSub: - opCode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR; + opcode = (thumbForm) ? kThumbSubRRR : kThumb2SubRRR; break; case kOpAdc: - opCode = kThumb2AdcRRR; + opcode = kThumb2AdcRRR; break; case kOpAnd: - opCode = kThumb2AndRRR; + opcode = kThumb2AndRRR; break; case kOpBic: - opCode = kThumb2BicRRR; + opcode = kThumb2BicRRR; break; case kOpXor: - opCode = kThumb2EorRRR; + opcode = kThumb2EorRRR; break; case kOpMul: assert(shift == 0); - opCode = kThumb2MulRRR; + opcode = kThumb2MulRRR; break; case kOpOr: - opCode = kThumb2OrrRRR; + opcode = kThumb2OrrRRR; break; case kOpSbc: - opCode = kThumb2SbcRRR; + opcode = kThumb2SbcRRR; break; case kOpLsl: assert(shift == 0); - opCode = kThumb2LslRRR; + opcode = kThumb2LslRRR; break; case kOpLsr: assert(shift == 0); - opCode = kThumb2LsrRRR; + opcode = kThumb2LsrRRR; break; case kOpAsr: assert(shift == 0); - opCode = kThumb2AsrRRR; + opcode = kThumb2AsrRRR; break; case kOpRor: assert(shift == 0); - opCode = kThumb2RorRRR; + opcode = kThumb2RorRRR; break; default: assert(0); break; } - assert(opCode >= 0); - if (EncodingMap[opCode].flags & IS_QUAD_OP) - return newLIR4(cUnit, opCode, rDest, rSrc1, rSrc2, shift); + assert(opcode >= 0); + if (EncodingMap[opcode].flags & IS_QUAD_OP) + return newLIR4(cUnit, opcode, rDest, rSrc1, rSrc2, shift); else { - assert(EncodingMap[opCode].flags & IS_TERTIARY_OP); - return newLIR3(cUnit, opCode, rDest, rSrc1, rSrc2); + assert(EncodingMap[opcode].flags & IS_TERTIARY_OP); + return newLIR3(cUnit, opcode, rDest, rSrc1, rSrc2); } } @@ -457,8 +457,8 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, ArmLIR *res; bool neg = (value < 0); int absValue = (neg) ? -value : value; - ArmOpCode opCode = kThumbBkpt; - ArmOpCode altOpCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; + ArmOpcode altOpcode = kThumbBkpt; bool allLowRegs = (LOWREG(rDest) && LOWREG(rSrc1)); int modImm = modifiedImmediate(value); int modImmNeg = modifiedImmediate(-value); @@ -491,56 +491,56 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, return newLIR3(cUnit, kThumbAddPcRel, rDest, rSrc1, value >> 2); } - opCode = kThumb2AddRRI8; - altOpCode = kThumb2AddRRR; + opcode = kThumb2AddRRI8; + altOpcode = kThumb2AddRRR; // Note: intentional fallthrough case kOpSub: if (allLowRegs && ((absValue & 0x7) == absValue)) { if (op == kOpAdd) - opCode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; + opcode = (neg) ? kThumbSubRRI3 : kThumbAddRRI3; else - opCode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; - return newLIR3(cUnit, opCode, rDest, rSrc1, absValue); + opcode = (neg) ? kThumbAddRRI3 : kThumbSubRRI3; + return newLIR3(cUnit, opcode, rDest, rSrc1, absValue); } else if ((absValue & 0xff) == absValue) { if (op == kOpAdd) - opCode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12; + opcode = (neg) ? kThumb2SubRRI12 : kThumb2AddRRI12; else - opCode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12; - return newLIR3(cUnit, opCode, rDest, rSrc1, absValue); + opcode = (neg) ? kThumb2AddRRI12 : kThumb2SubRRI12; + return newLIR3(cUnit, opcode, rDest, rSrc1, absValue); } if (modImmNeg >= 0) { op = (op == kOpAdd) ? kOpSub : kOpAdd; modImm = modImmNeg; } if (op == kOpSub) { - opCode = kThumb2SubRRI8; - altOpCode = kThumb2SubRRR; + opcode = kThumb2SubRRI8; + altOpcode = kThumb2SubRRR; } break; case kOpAdc: - opCode = kThumb2AdcRRI8; - altOpCode = kThumb2AdcRRR; + opcode = kThumb2AdcRRI8; + altOpcode = kThumb2AdcRRR; break; case kOpSbc: - opCode = kThumb2SbcRRI8; - altOpCode = kThumb2SbcRRR; + opcode = kThumb2SbcRRI8; + altOpcode = kThumb2SbcRRR; break; case kOpOr: - opCode = kThumb2OrrRRI8; - altOpCode = kThumb2OrrRRR; + opcode = kThumb2OrrRRI8; + altOpcode = kThumb2OrrRRR; break; case kOpAnd: - opCode = kThumb2AndRRI8; - altOpCode = kThumb2AndRRR; + opcode = kThumb2AndRRI8; + altOpcode = kThumb2AndRRR; break; case kOpXor: - opCode = kThumb2EorRRI8; - altOpCode = kThumb2EorRRR; + opcode = kThumb2EorRRI8; + altOpcode = kThumb2EorRRR; break; case kOpMul: //TUNING: power of 2, shift & add modImm = -1; - altOpCode = kThumb2MulRRR; + altOpcode = kThumb2MulRRR; break; case kOpCmp: { int modImm = modifiedImmediate(value); @@ -560,14 +560,14 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest, } if (modImm >= 0) { - return newLIR3(cUnit, opCode, rDest, rSrc1, modImm); + return newLIR3(cUnit, opcode, rDest, rSrc1, modImm); } else { int rScratch = dvmCompilerAllocTemp(cUnit); loadConstant(cUnit, rScratch, value); - if (EncodingMap[altOpCode].flags & IS_QUAD_OP) - res = newLIR4(cUnit, altOpCode, rDest, rSrc1, rScratch, 0); + if (EncodingMap[altOpcode].flags & IS_QUAD_OP) + res = newLIR4(cUnit, altOpcode, rDest, rSrc1, rScratch, 0); else - res = newLIR3(cUnit, altOpCode, rDest, rSrc1, rScratch); + res = newLIR3(cUnit, altOpcode, rDest, rSrc1, rScratch); dvmCompilerFreeTemp(cUnit, rScratch); return res; } @@ -580,14 +580,14 @@ static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, bool neg = (value < 0); int absValue = (neg) ? -value : value; bool shortForm = (((absValue & 0xff) == absValue) && LOWREG(rDestSrc1)); - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; switch (op) { case kOpAdd: if ( !neg && (rDestSrc1 == 13) && (value <= 508)) { /* sp */ assert((value & 0x3) == 0); return newLIR1(cUnit, kThumbAddSpI7, value >> 2); } else if (shortForm) { - opCode = (neg) ? kThumbSubRI8 : kThumbAddRI8; + opcode = (neg) ? kThumbSubRI8 : kThumbAddRI8; } break; case kOpSub: @@ -595,17 +595,17 @@ static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, assert((value & 0x3) == 0); return newLIR1(cUnit, kThumbSubSpI7, value >> 2); } else if (shortForm) { - opCode = (neg) ? kThumbAddRI8 : kThumbSubRI8; + opcode = (neg) ? kThumbAddRI8 : kThumbSubRI8; } break; case kOpCmp: if (LOWREG(rDestSrc1) && shortForm) - opCode = (shortForm) ? kThumbCmpRI8 : kThumbCmpRR; + opcode = (shortForm) ? kThumbCmpRI8 : kThumbCmpRR; else if (LOWREG(rDestSrc1)) - opCode = kThumbCmpRR; + opcode = kThumbCmpRR; else { shortForm = false; - opCode = kThumbCmpHL; + opcode = kThumbCmpHL; } break; default: @@ -614,7 +614,7 @@ static ArmLIR *opRegImm(CompilationUnit *cUnit, OpKind op, int rDestSrc1, break; } if (shortForm) - return newLIR2(cUnit, opCode, rDestSrc1, absValue); + return newLIR2(cUnit, opcode, rDestSrc1, absValue); else { return opRegRegImm(cUnit, op, rDestSrc1, rDestSrc1, value); } @@ -678,14 +678,14 @@ static ArmLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase, { bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rDest); ArmLIR *load; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool thumbForm = (allLowRegs && (scale == 0)); int regPtr; if (FPREG(rDest)) { assert(SINGLEREG(rDest)); assert((size == kWord) || (size == kSingle)); - opCode = kThumb2Vldrs; + opcode = kThumb2Vldrs; size = kSingle; } else { if (size == kSingle) @@ -701,34 +701,34 @@ static ArmLIR *loadBaseIndexed(CompilationUnit *cUnit, int rBase, } else { opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex); } - load = newLIR3(cUnit, opCode, rDest, regPtr, 0); + load = newLIR3(cUnit, opcode, rDest, regPtr, 0); #if defined(WITH_SELF_VERIFICATION) if (cUnit->heapMemOp) load->branchInsertSV = true; #endif return load; case kWord: - opCode = (thumbForm) ? kThumbLdrRRR : kThumb2LdrRRR; + opcode = (thumbForm) ? kThumbLdrRRR : kThumb2LdrRRR; break; case kUnsignedHalf: - opCode = (thumbForm) ? kThumbLdrhRRR : kThumb2LdrhRRR; + opcode = (thumbForm) ? kThumbLdrhRRR : kThumb2LdrhRRR; break; case kSignedHalf: - opCode = (thumbForm) ? kThumbLdrshRRR : kThumb2LdrshRRR; + opcode = (thumbForm) ? kThumbLdrshRRR : kThumb2LdrshRRR; break; case kUnsignedByte: - opCode = (thumbForm) ? kThumbLdrbRRR : kThumb2LdrbRRR; + opcode = (thumbForm) ? kThumbLdrbRRR : kThumb2LdrbRRR; break; case kSignedByte: - opCode = (thumbForm) ? kThumbLdrsbRRR : kThumb2LdrsbRRR; + opcode = (thumbForm) ? kThumbLdrsbRRR : kThumb2LdrsbRRR; break; default: assert(0); } if (thumbForm) - load = newLIR3(cUnit, opCode, rDest, rBase, rIndex); + load = newLIR3(cUnit, opcode, rDest, rBase, rIndex); else - load = newLIR4(cUnit, opCode, rDest, rBase, rIndex, scale); + load = newLIR4(cUnit, opcode, rDest, rBase, rIndex, scale); #if defined(WITH_SELF_VERIFICATION) if (cUnit->heapMemOp) @@ -742,14 +742,14 @@ static ArmLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase, { bool allLowRegs = LOWREG(rBase) && LOWREG(rIndex) && LOWREG(rSrc); ArmLIR *store; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool thumbForm = (allLowRegs && (scale == 0)); int regPtr; if (FPREG(rSrc)) { assert(SINGLEREG(rSrc)); assert((size == kWord) || (size == kSingle)); - opCode = kThumb2Vstrs; + opcode = kThumb2Vstrs; size = kSingle; } else { if (size == kSingle) @@ -765,30 +765,30 @@ static ArmLIR *storeBaseIndexed(CompilationUnit *cUnit, int rBase, } else { opRegRegReg(cUnit, kOpAdd, regPtr, rBase, rIndex); } - store = newLIR3(cUnit, opCode, rSrc, regPtr, 0); + store = newLIR3(cUnit, opcode, rSrc, regPtr, 0); #if defined(WITH_SELF_VERIFICATION) if (cUnit->heapMemOp) store->branchInsertSV = true; #endif return store; case kWord: - opCode = (thumbForm) ? kThumbStrRRR : kThumb2StrRRR; + opcode = (thumbForm) ? kThumbStrRRR : kThumb2StrRRR; break; case kUnsignedHalf: case kSignedHalf: - opCode = (thumbForm) ? kThumbStrhRRR : kThumb2StrhRRR; + opcode = (thumbForm) ? kThumbStrhRRR : kThumb2StrhRRR; break; case kUnsignedByte: case kSignedByte: - opCode = (thumbForm) ? kThumbStrbRRR : kThumb2StrbRRR; + opcode = (thumbForm) ? kThumbStrbRRR : kThumb2StrbRRR; break; default: assert(0); } if (thumbForm) - store = newLIR3(cUnit, opCode, rSrc, rBase, rIndex); + store = newLIR3(cUnit, opcode, rSrc, rBase, rIndex); else - store = newLIR4(cUnit, opCode, rSrc, rBase, rIndex, scale); + store = newLIR4(cUnit, opcode, rSrc, rBase, rIndex, scale); #if defined(WITH_SELF_VERIFICATION) if (cUnit->heapMemOp) @@ -807,7 +807,7 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, OpSize size, int sReg) { ArmLIR *res, *load; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool shortForm = false; bool thumb2Form = (displacement < 4092 && displacement >= 0); bool allLowRegs = (LOWREG(rBase) && LOWREG(rDest)); @@ -821,7 +821,7 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, assert(FPREG(rDestHi)); rDest = S2D(rDest, rDestHi); } - opCode = kThumb2Vldrd; + opcode = kThumb2Vldrd; if (displacement <= 1020) { shortForm = true; encodedDisp >>= 2; @@ -837,7 +837,7 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, case kSingle: case kWord: if (FPREG(rDest)) { - opCode = kThumb2Vldrs; + opcode = kThumb2Vldrs; if (displacement <= 1020) { shortForm = true; encodedDisp >>= 2; @@ -848,20 +848,20 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, (displacement <= 1020) && (displacement >= 0)) { shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrPcRel; + opcode = kThumbLdrPcRel; } else if (LOWREG(rDest) && (rBase == r13) && (displacement <= 1020) && (displacement >= 0)) { shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrSpRel; + opcode = kThumbLdrSpRel; } else if (allLowRegs && displacement < 128 && displacement >= 0) { assert((displacement & 0x3) == 0); shortForm = true; encodedDisp >>= 2; - opCode = kThumbLdrRRI5; + opcode = kThumbLdrRRI5; } else if (thumb2Form) { shortForm = true; - opCode = kThumb2LdrRRI12; + opcode = kThumb2LdrRRI12; } break; case kUnsignedHalf: @@ -869,31 +869,31 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, assert((displacement & 0x1) == 0); shortForm = true; encodedDisp >>= 1; - opCode = kThumbLdrhRRI5; + opcode = kThumbLdrhRRI5; } else if (displacement < 4092 && displacement >= 0) { shortForm = true; - opCode = kThumb2LdrhRRI12; + opcode = kThumb2LdrhRRI12; } break; case kSignedHalf: if (thumb2Form) { shortForm = true; - opCode = kThumb2LdrshRRI12; + opcode = kThumb2LdrshRRI12; } break; case kUnsignedByte: if (allLowRegs && displacement < 32 && displacement >= 0) { shortForm = true; - opCode = kThumbLdrbRRI5; + opcode = kThumbLdrbRRI5; } else if (thumb2Form) { shortForm = true; - opCode = kThumb2LdrbRRI12; + opcode = kThumb2LdrbRRI12; } break; case kSignedByte: if (thumb2Form) { shortForm = true; - opCode = kThumb2LdrsbRRI12; + opcode = kThumb2LdrsbRRI12; } break; default: @@ -901,7 +901,7 @@ static ArmLIR *loadBaseDispBody(CompilationUnit *cUnit, MIR *mir, int rBase, } if (shortForm) { - load = res = newLIR3(cUnit, opCode, rDest, rBase, encodedDisp); + load = res = newLIR3(cUnit, opcode, rDest, rBase, encodedDisp); } else { int regOffset = dvmCompilerAllocTemp(cUnit); res = loadConstant(cUnit, regOffset, encodedDisp); @@ -941,7 +941,7 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, OpSize size) { ArmLIR *res, *store; - ArmOpCode opCode = kThumbBkpt; + ArmOpcode opcode = kThumbBkpt; bool shortForm = false; bool thumb2Form = (displacement < 4092 && displacement >= 0); bool allLowRegs = (LOWREG(rBase) && LOWREG(rSrc)); @@ -961,7 +961,7 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, assert(FPREG(rSrcHi)); rSrc = S2D(rSrc, rSrcHi); } - opCode = kThumb2Vstrd; + opcode = kThumb2Vstrd; if (displacement <= 1020) { shortForm = true; encodedDisp >>= 2; @@ -971,7 +971,7 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, case kWord: if (FPREG(rSrc)) { assert(SINGLEREG(rSrc)); - opCode = kThumb2Vstrs; + opcode = kThumb2Vstrs; if (displacement <= 1020) { shortForm = true; encodedDisp >>= 2; @@ -982,10 +982,10 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, assert((displacement & 0x3) == 0); shortForm = true; encodedDisp >>= 2; - opCode = kThumbStrRRI5; + opcode = kThumbStrRRI5; } else if (thumb2Form) { shortForm = true; - opCode = kThumb2StrRRI12; + opcode = kThumb2StrRRI12; } break; case kUnsignedHalf: @@ -994,27 +994,27 @@ static ArmLIR *storeBaseDispBody(CompilationUnit *cUnit, int rBase, assert((displacement & 0x1) == 0); shortForm = true; encodedDisp >>= 1; - opCode = kThumbStrhRRI5; + opcode = kThumbStrhRRI5; } else if (thumb2Form) { shortForm = true; - opCode = kThumb2StrhRRI12; + opcode = kThumb2StrhRRI12; } break; case kUnsignedByte: case kSignedByte: if (allLowRegs && displacement < 32 && displacement >= 0) { shortForm = true; - opCode = kThumbStrbRRI5; + opcode = kThumbStrbRRI5; } else if (thumb2Form) { shortForm = true; - opCode = kThumb2StrbRRI12; + opcode = kThumb2StrbRRI12; } break; default: assert(0); } if (shortForm) { - store = res = newLIR3(cUnit, opCode, rSrc, rBase, encodedDisp); + store = res = newLIR3(cUnit, opcode, rSrc, rBase, encodedDisp); } else { int rScratch = dvmCompilerAllocTemp(cUnit); res = loadConstant(cUnit, rScratch, encodedDisp); @@ -1129,13 +1129,13 @@ static ArmLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) } else { assert(DOUBLEREG(rDest) == DOUBLEREG(rSrc)); if (DOUBLEREG(rDest)) { - res->opCode = kThumb2Vmovd; + res->opcode = kThumb2Vmovd; } else { if (SINGLEREG(rDest)) { - res->opCode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr; + res->opcode = SINGLEREG(rSrc) ? kThumb2Vmovs : kThumb2Fmsr; } else { assert(SINGLEREG(rSrc)); - res->opCode = kThumb2Fmrs; + res->opcode = kThumb2Fmrs; } } res->operands[0] = rDest; @@ -1148,22 +1148,22 @@ static ArmLIR *fpRegCopy(CompilationUnit *cUnit, int rDest, int rSrc) static ArmLIR* genRegCopyNoInsert(CompilationUnit *cUnit, int rDest, int rSrc) { ArmLIR* res; - ArmOpCode opCode; + ArmOpcode opcode; if (FPREG(rDest) || FPREG(rSrc)) return fpRegCopy(cUnit, rDest, rSrc); res = dvmCompilerNew(sizeof(ArmLIR), true); if (LOWREG(rDest) && LOWREG(rSrc)) - opCode = kThumbMovRR; + opcode = kThumbMovRR; else if (!LOWREG(rDest) && !LOWREG(rSrc)) - opCode = kThumbMovRR_H2H; + opcode = kThumbMovRR_H2H; else if (LOWREG(rDest)) - opCode = kThumbMovRR_H2L; + opcode = kThumbMovRR_H2L; else - opCode = kThumbMovRR_L2H; + opcode = kThumbMovRR_L2H; res->operands[0] = rDest; res->operands[1] = rSrc; - res->opCode = opCode; + res->opcode = opcode; setupResourceMasks(res); if (rDest == rSrc) { res->isNop = true; diff --git a/vm/compiler/codegen/arm/Thumb2/Gen.c b/vm/compiler/codegen/arm/Thumb2/Gen.c index 3d689c966..f1f6df3f3 100644 --- a/vm/compiler/codegen/arm/Thumb2/Gen.c +++ b/vm/compiler/codegen/arm/Thumb2/Gen.c @@ -301,7 +301,7 @@ static void genMonitorExit(CompilationUnit *cUnit, MIR *mir) static void genMonitor(CompilationUnit *cUnit, MIR *mir) { - if (mir->dalvikInsn.opCode == OP_MONITOR_ENTER) + if (mir->dalvikInsn.opcode == OP_MONITOR_ENTER) genMonitorEnter(cUnit, mir); else genMonitorExit(cUnit, mir); diff --git a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h index 9f862e840..fa0121057 100644 --- a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h +++ b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.h @@ -28,7 +28,7 @@ typedef enum { * ... */ TEMPLATE_LAST_MARK, -} TemplateOpCode; +} TemplateOpcode; #undef JIT_TEMPLATE #endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */ diff --git a/vm/compiler/codegen/arm/armv5te/ArchVariant.h b/vm/compiler/codegen/arm/armv5te/ArchVariant.h index 6420df719..4cc4fa643 100644 --- a/vm/compiler/codegen/arm/armv5te/ArchVariant.h +++ b/vm/compiler/codegen/arm/armv5te/ArchVariant.h @@ -28,7 +28,7 @@ typedef enum { * ... */ TEMPLATE_LAST_MARK, -} TemplateOpCode; +} TemplateOpcode; #undef JIT_TEMPLATE #endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_ARCHVARIANT_H */ diff --git a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h index 9f862e840..fa0121057 100644 --- a/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h +++ b/vm/compiler/codegen/arm/armv7-a-neon/ArchVariant.h @@ -28,7 +28,7 @@ typedef enum { * ... */ TEMPLATE_LAST_MARK, -} TemplateOpCode; +} TemplateOpcode; #undef JIT_TEMPLATE #endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */ diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.h b/vm/compiler/codegen/arm/armv7-a/ArchVariant.h index 9f862e840..fa0121057 100644 --- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.h +++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.h @@ -28,7 +28,7 @@ typedef enum { * ... */ TEMPLATE_LAST_MARK, -} TemplateOpCode; +} TemplateOpcode; #undef JIT_TEMPLATE #endif /* _DALVIK_VM_COMPILER_CODEGEN_ARM_ARMV5TE_VFP_ARCHVARIANT_H */ diff --git a/vm/compiler/codegen/x86/X86LIR.h b/vm/compiler/codegen/x86/X86LIR.h index 969c37194..62ac44733 100644 --- a/vm/compiler/codegen/x86/X86LIR.h +++ b/vm/compiler/codegen/x86/X86LIR.h @@ -134,7 +134,7 @@ typedef enum OpKind { typedef struct X86LIR { LIR generic; - //X86OpCode opCode; + //X86Opcode opcode; int operands[4]; // [0..3] = [dest, src1, src2, extra] bool isNop; // LIR is optimized away bool branchInsertSV;// mark for insertion of branch before this instruction, diff --git a/vm/compiler/codegen/x86/ia32/ArchVariant.h b/vm/compiler/codegen/x86/ia32/ArchVariant.h index ac4293f0f..e4eebf3b4 100644 --- a/vm/compiler/codegen/x86/ia32/ArchVariant.h +++ b/vm/compiler/codegen/x86/ia32/ArchVariant.h @@ -28,7 +28,7 @@ typedef enum { * ... */ TEMPLATE_LAST_MARK, -} TemplateOpCode; +} TemplateOpcode; #undef JIT_TEMPLATE #endif /* _DALVIK_VM_COMPILER_CODEGEN_X86_IA32_ARCHVARIANT_H */ diff --git a/vm/compiler/template/gen-template.py b/vm/compiler/template/gen-template.py index 2474ee2e0..addb21e08 100755 --- a/vm/compiler/template/gen-template.py +++ b/vm/compiler/template/gen-template.py @@ -212,7 +212,7 @@ def emitAsmHeader(outfp, dict): # with overflow here. outfp.write(" .balign 4\n") # Emit a label so that gdb will say the right thing. We prepend an - # underscore so the symbol name doesn't clash with the OpCode enum. + # underscore so the symbol name doesn't clash with the Opcode enum. template_name = "dvmCompiler_%(opcode)s" % dict outfp.write(" .global %s\n" % template_name); outfp.write("%s:\n" % template_name); |