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author | Ben Cheng <bccheng@android.com> | 2010-02-04 16:15:59 -0800 |
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committer | Ben Cheng <bccheng@android.com> | 2010-02-05 16:16:16 -0800 |
commit | 7b133ef7c84e68c3c4042176d830ea5b52e84139 (patch) | |
tree | c2a658e55e4a6140efa5781079fff65a6a829da7 /vm/compiler | |
parent | dbcc7c432976ca3f71dc866b4f8125fdeecd7134 (diff) | |
download | android_dalvik-7b133ef7c84e68c3c4042176d830ea5b52e84139.tar.gz android_dalvik-7b133ef7c84e68c3c4042176d830ea5b52e84139.tar.bz2 android_dalvik-7b133ef7c84e68c3c4042176d830ea5b52e84139.zip |
Enable JIT parameters to be initialized in an architecture dependent way.
The search for optimial value is still ongoing. The current settings are:
v5 v7
JIT profile table 512 2048
JIT code cache 512K 1M
JIT threshold 200 40
Diffstat (limited to 'vm/compiler')
-rw-r--r-- | vm/compiler/Compiler.c | 2 | ||||
-rw-r--r-- | vm/compiler/Compiler.h | 1 | ||||
-rw-r--r-- | vm/compiler/codegen/arm/Assemble.c | 4 | ||||
-rw-r--r-- | vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c | 1 | ||||
-rw-r--r-- | vm/compiler/codegen/arm/armv5te/ArchVariant.c | 1 | ||||
-rw-r--r-- | vm/compiler/codegen/arm/armv7-a/ArchVariant.c | 2 |
6 files changed, 6 insertions, 5 deletions
diff --git a/vm/compiler/Compiler.c b/vm/compiler/Compiler.c index 2fafd4e79..1d521986c 100644 --- a/vm/compiler/Compiler.c +++ b/vm/compiler/Compiler.c @@ -126,7 +126,7 @@ bool dvmCompilerSetupCodeCache(void) extern void dmvCompilerTemplateEnd(void); /* Allocate the code cache */ - gDvmJit.codeCache = mmap(0, CODE_CACHE_SIZE, + gDvmJit.codeCache = mmap(0, gDvmJit.codeCacheSize, PROT_READ | PROT_WRITE | PROT_EXEC, MAP_PRIVATE | MAP_ANON, -1, 0); if (gDvmJit.codeCache == MAP_FAILED) { diff --git a/vm/compiler/Compiler.h b/vm/compiler/Compiler.h index 153e84568..ccc91ddb2 100644 --- a/vm/compiler/Compiler.h +++ b/vm/compiler/Compiler.h @@ -19,7 +19,6 @@ #ifndef _DALVIK_VM_COMPILER #define _DALVIK_VM_COMPILER -#define CODE_CACHE_SIZE 1024*1024 #define MAX_JIT_RUN_LEN 64 #define COMPILER_WORK_QUEUE_SIZE 100 #define COMPILER_IC_PATCH_QUEUE_SIZE 64 diff --git a/vm/compiler/codegen/arm/Assemble.c b/vm/compiler/codegen/arm/Assemble.c index 826a3d24d..fd7c76b11 100644 --- a/vm/compiler/codegen/arm/Assemble.c +++ b/vm/compiler/codegen/arm/Assemble.c @@ -1216,7 +1216,7 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info) cUnit->totalSize = offset; - if (gDvmJit.codeCacheByteUsed + cUnit->totalSize > CODE_CACHE_SIZE) { + if (gDvmJit.codeCacheByteUsed + cUnit->totalSize > gDvmJit.codeCacheSize) { gDvmJit.codeCacheFull = true; cUnit->baseAddr = NULL; return; @@ -1504,7 +1504,7 @@ void dvmCompilerPatchInlineCache(void) /* Initialize the min/max address range */ minAddr = (PredictedChainingCell *) - ((char *) gDvmJit.codeCache + CODE_CACHE_SIZE); + ((char *) gDvmJit.codeCache + gDvmJit.codeCacheSize); maxAddr = (PredictedChainingCell *) gDvmJit.codeCache; for (i = 0; i < gDvmJit.compilerICPatchIndex; i++) { diff --git a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c index 9a602f69b..b5706f530 100644 --- a/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c +++ b/vm/compiler/codegen/arm/armv5te-vfp/ArchVariant.c @@ -52,6 +52,7 @@ bool dvmCompilerArchVariantInit(void) gDvmJit.jitTableSize = 1 << 9; // 512 gDvmJit.jitTableMask = gDvmJit.jitTableSize - 1; gDvmJit.threshold = 200; + gDvmJit.codeCacheSize = 512*1024; #if defined(WITH_SELF_VERIFICATION) /* Force into blocking mode */ diff --git a/vm/compiler/codegen/arm/armv5te/ArchVariant.c b/vm/compiler/codegen/arm/armv5te/ArchVariant.c index 2d080e44d..1311510ed 100644 --- a/vm/compiler/codegen/arm/armv5te/ArchVariant.c +++ b/vm/compiler/codegen/arm/armv5te/ArchVariant.c @@ -52,6 +52,7 @@ bool dvmCompilerArchVariantInit(void) gDvmJit.jitTableSize = 1 << 9; // 512 gDvmJit.jitTableMask = gDvmJit.jitTableSize - 1; gDvmJit.threshold = 200; + gDvmJit.codeCacheSize = 512*1024; #if defined(WITH_SELF_VERIFICATION) /* Force into blocking mode */ diff --git a/vm/compiler/codegen/arm/armv7-a/ArchVariant.c b/vm/compiler/codegen/arm/armv7-a/ArchVariant.c index cd8754c3c..1579d122d 100644 --- a/vm/compiler/codegen/arm/armv7-a/ArchVariant.c +++ b/vm/compiler/codegen/arm/armv7-a/ArchVariant.c @@ -14,7 +14,6 @@ * limitations under the License. */ - /* * Determine the initial instruction set to be used for this trace. * Later components may decide to change this. @@ -48,6 +47,7 @@ bool dvmCompilerArchVariantInit(void) gDvmJit.jitTableSize = 1 << 12; // 4096 gDvmJit.jitTableMask = gDvmJit.jitTableSize - 1; gDvmJit.threshold = 40; + gDvmJit.codeCacheSize = 1024*1024; #if defined(WITH_SELF_VERIFICATION) /* Force into blocking */ |