Move dalvik off cacheflush so we can deprecate it.

Bug: 12965705
Change-Id: I805428e3103ff578d048ecbbc6ae30c0ead19ef9

5 files changed, 10 insertions, 26 deletions

diff --git a/vm/compiler/codegen/arm/ArchUtility.cpp b/vm/compiler/codegen/arm/ArchUtility.cpp
index 9f87b7ff4..b5e739f49 100644
--- a/vm/compiler/codegen/arm/ArchUtility.cpp
+++ b/vm/compiler/codegen/arm/ArchUtility.cpp
@@ -420,12 +420,6 @@ void dvmCompilerCodegenDump(CompilationUnit *cUnit)
     }
 }
 
-/* Target-specific cache flushing */
-void dvmCompilerCacheFlush(long start, long end, long flags)
-{
-    cacheflush(start, end, flags);
-}
-
 /* Target-specific cache clearing */
 void dvmCompilerCacheClear(char *start, size_t size)
 {
diff --git a/vm/compiler/codegen/arm/Assemble.cpp b/vm/compiler/codegen/arm/Assemble.cpp
index 5f2de72d6..7ed2d47d5 100644
--- a/vm/compiler/codegen/arm/Assemble.cpp
+++ b/vm/compiler/codegen/arm/Assemble.cpp
@@ -1562,7 +1562,7 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
 
     /* Flush dcache and invalidate the icache to maintain coherence */
     dvmCompilerCacheFlush((long)cUnit->baseAddr,
-                          (long)((char *) cUnit->baseAddr + offset), 0);
+                          (long)((char *) cUnit->baseAddr + offset));
     UPDATE_CODE_CACHE_PATCHES();
 
     PROTECT_CODE_CACHE(cUnit->baseAddr, offset);
@@ -1662,7 +1662,7 @@ void* dvmJitChain(void* tgtAddr, u4* branchAddr)
         UNPROTECT_CODE_CACHE(branchAddr, sizeof(*branchAddr));
 
         *branchAddr = newInst;
-        dvmCompilerCacheFlush((long)branchAddr, (long)branchAddr + 4, 0);
+        dvmCompilerCacheFlush((long)branchAddr, (long)branchAddr + 4);
         UPDATE_CODE_CACHE_PATCHES();
 
         PROTECT_CODE_CACHE(branchAddr, sizeof(*branchAddr));
@@ -1702,7 +1702,7 @@ static void inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
          */
         android_atomic_release_store((int32_t)newContent->clazz,
             (volatile int32_t *)(void *)&cellAddr->clazz);
-        dvmCompilerCacheFlush((intptr_t) cellAddr, (intptr_t) (cellAddr+1), 0);
+        dvmCompilerCacheFlush((intptr_t) cellAddr, (intptr_t) (cellAddr+1));
         UPDATE_CODE_CACHE_PATCHES();
 
         PROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
@@ -1902,7 +1902,7 @@ void dvmCompilerPatchInlineCache(void)
     }
 
     /* Then synchronize the I/D cache */
-    dvmCompilerCacheFlush((long) minAddr, (long) (maxAddr+1), 0);
+    dvmCompilerCacheFlush((long) minAddr, (long) (maxAddr+1));
     UPDATE_CODE_CACHE_PATCHES();
 
     PROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
@@ -2010,7 +2010,7 @@ void dvmJitUnchainAll()
                     highAddress = lastAddress;
             }
         }
-        dvmCompilerCacheFlush((long)lowAddress, (long)highAddress, 0);
+        dvmCompilerCacheFlush((long)lowAddress, (long)highAddress);
         UPDATE_CODE_CACHE_PATCHES();
 
         PROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
diff --git a/vm/compiler/codegen/mips/ArchUtility.cpp b/vm/compiler/codegen/mips/ArchUtility.cpp
index 47c4c6de1..0b10cdaa0 100644
--- a/vm/compiler/codegen/mips/ArchUtility.cpp
+++ b/vm/compiler/codegen/mips/ArchUtility.cpp
@@ -369,12 +369,6 @@ void dvmCompilerCodegenDump(CompilationUnit *cUnit)
     }
 }
 
-/* Target-specific cache flushing */
-void dvmCompilerCacheFlush(long start, long end, long flags)
-{
-    cacheflush(start, end, flags);
-}
-
 /* Target-specific cache clearing */
 void dvmCompilerCacheClear(char *start, size_t size)
 {
diff --git a/vm/compiler/codegen/mips/Assemble.cpp b/vm/compiler/codegen/mips/Assemble.cpp
index 36a301c9a..76aa60657 100644
--- a/vm/compiler/codegen/mips/Assemble.cpp
+++ b/vm/compiler/codegen/mips/Assemble.cpp
@@ -913,7 +913,7 @@ void dvmCompilerAssembleLIR(CompilationUnit *cUnit, JitTranslationInfo *info)
 
     /* Flush dcache and invalidate the icache to maintain coherence */
     dvmCompilerCacheFlush((long)cUnit->baseAddr,
-                          (long)((char *) cUnit->baseAddr + offset), 0);
+                          (long)((char *) cUnit->baseAddr + offset));
 
     UPDATE_CODE_CACHE_PATCHES();
 
@@ -974,7 +974,7 @@ void* dvmJitChain(void* tgtAddr, u4* branchAddr)
         UNPROTECT_CODE_CACHE(branchAddr, sizeof(*branchAddr));
 
         *branchAddr = newInst;
-        dvmCompilerCacheFlush((long)branchAddr, (long)branchAddr + 4, 0);
+        dvmCompilerCacheFlush((long)branchAddr, (long)branchAddr + 4);
         UPDATE_CODE_CACHE_PATCHES();
 
         PROTECT_CODE_CACHE(branchAddr, sizeof(*branchAddr));
@@ -1015,7 +1015,7 @@ static void inlineCachePatchEnqueue(PredictedChainingCell *cellAddr,
          */
         android_atomic_release_store((int32_t)newContent->clazz,
             (volatile int32_t *)(void*) &cellAddr->clazz);
-        dvmCompilerCacheFlush((long) cellAddr, (long) (cellAddr+1), 0);
+        dvmCompilerCacheFlush((long) cellAddr, (long) (cellAddr+1));
         UPDATE_CODE_CACHE_PATCHES();
 
         PROTECT_CODE_CACHE(cellAddr, sizeof(*cellAddr));
@@ -1226,7 +1226,7 @@ void dvmCompilerPatchInlineCache(void)
     }
 
     /* Then synchronize the I/D cache */
-    dvmCompilerCacheFlush((long) minAddr, (long) (maxAddr+1), 0);
+    dvmCompilerCacheFlush((long) minAddr, (long) (maxAddr+1));
     UPDATE_CODE_CACHE_PATCHES();
 
     PROTECT_CODE_CACHE(gDvmJit.codeCache, gDvmJit.codeCacheByteUsed);
@@ -1353,7 +1353,7 @@ void dvmJitUnchainAll()
         }
 
         if (lowAddress && highAddress)
-            dvmCompilerCacheFlush((long)lowAddress, (long)highAddress, 0);
+            dvmCompilerCacheFlush((long)lowAddress, (long)highAddress);
 
         UPDATE_CODE_CACHE_PATCHES();
 
diff --git a/vm/compiler/codegen/x86/CodegenInterface.cpp b/vm/compiler/codegen/x86/CodegenInterface.cpp
index 337bd61ae..6ec5f9d12 100644
--- a/vm/compiler/codegen/x86/CodegenInterface.cpp
+++ b/vm/compiler/codegen/x86/CodegenInterface.cpp
@@ -1538,8 +1538,4 @@ bool dvmCompilerDoWork(CompilerWorkOrder *work)
     return isCompile;
 }
 
-void dvmCompilerCacheFlush(long start, long end, long flags) {
-  /* cacheflush is needed for ARM, but not for IA32 (coherent icache) */
-}
-
 //#endif