Dalvik: Add sdiv support in the JIT

This patch adds hardware divide support in the JIT side of dalvik.
This operation is supported on new armv7 cpus such as A15 or A7.

The following opcodes are enabled and will generate code based using
SDIV instruction:

        OP_DIV_INT
        OP_DIV_INT_2ADDR
        OP_REM_INT
        OP_REM_INT_2ADDR
        OP_DIV_INT_LIT16
        OP_DIV_INT_LIT8
        OP_REM_INT_LIT16
        OP_REM_INT_LIT8

Change-Id: I2b2f9f337f13b5c794df951c4929b6ca0ad583c4
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>

1 files changed, 21 insertions, 0 deletions

diff --git a/vm/compiler/codegen/arm/Thumb2/Factory.cpp b/vm/compiler/codegen/arm/Thumb2/Factory.cpp
index b9265e823..cc036cb8b 100644
--- a/vm/compiler/codegen/arm/Thumb2/Factory.cpp
+++ b/vm/compiler/codegen/arm/Thumb2/Factory.cpp
@@ -352,6 +352,10 @@ static ArmLIR *opRegRegShift(CompilationUnit *cUnit, OpKind op, int rDestSrc1,
             assert(shift == 0);
             opcode = (thumbForm) ? kThumbMul : kThumb2MulRRR;
             break;
+        case kOpDiv:
+            assert(shift == 0);
+            opcode = kThumb2SdivRRR;
+            break;
         case kOpMvn:
             opcode = (thumbForm) ? kThumbMvn : kThumb2MnvRR;
             break;
@@ -454,6 +458,13 @@ static ArmLIR *opRegRegRegShift(CompilationUnit *cUnit, OpKind op,
             assert(shift == 0);
             opcode = kThumb2MulRRR;
             break;
+        case kOpDiv:
+            assert(shift == 0);
+            opcode = kThumb2SdivRRR;
+            break;
+        case kOpRem:
+            opcode = kThumb2MlsRRRR;
+            break;
         case kOpOr:
             opcode = kThumb2OrrRRR;
             break;
@@ -495,6 +506,12 @@ static ArmLIR *opRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
     return opRegRegRegShift(cUnit, op, rDest, rSrc1, rSrc2, 0);
 }
 
+static ArmLIR *opRegRegRegReg(CompilationUnit *cUnit, OpKind op, int rDest,
+                           int rSrc1, int rSrc2, int rSrc3)
+{
+    return opRegRegRegShift(cUnit, op, rDest, rSrc1, rSrc2, rSrc3);
+}
+
 static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
                            int rSrc1, int value)
 {
@@ -586,6 +603,10 @@ static ArmLIR *opRegRegImm(CompilationUnit *cUnit, OpKind op, int rDest,
             modImm = -1;
             altOpcode = kThumb2MulRRR;
             break;
+        case kOpDiv:
+            modImm = -1;
+            altOpcode = kThumb2SdivRRR;
+            break;
         case kOpCmp: {
             int modImm = modifiedImmediate(value);
             ArmLIR *res;