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| author | Ben Cheng <bccheng@google.com> | 2009-09-11 13:42:05 -0700 |
|---|---|---|
| committer | Ben Cheng <bccheng@google.com> | 2009-09-11 14:21:58 -0700 |
| commit | dcf3e5d43a1831a166f70cb9e0694cd4b0b356b0 (patch) | |
| tree | 52601ee529a5e21c46759521c5d7ba09b41889f2 /vm/compiler/IntermediateRep.c | |
| parent | fc869d7f570750b2318d91f1b047e134a74b8e09 (diff) | |
| download | android_dalvik-dcf3e5d43a1831a166f70cb9e0694cd4b0b356b0.tar.gz android_dalvik-dcf3e5d43a1831a166f70cb9e0694cd4b0b356b0.tar.bz2 android_dalvik-dcf3e5d43a1831a166f70cb9e0694cd4b0b356b0.zip | |
Model resource usage for each Thumb/Thumb2 instrution.
This is an mid-point checkin to avoid future merge nightmare for the register
allocator work.
Diffstat (limited to 'vm/compiler/IntermediateRep.c')
| -rw-r--r-- | vm/compiler/IntermediateRep.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/vm/compiler/IntermediateRep.c b/vm/compiler/IntermediateRep.c index a8bfda096..018d8907a 100644 --- a/vm/compiler/IntermediateRep.c +++ b/vm/compiler/IntermediateRep.c @@ -90,3 +90,17 @@ void dvmCompilerInsertLIRBefore(LIR *currentLIR, LIR *newLIR) newLIR->next = currentLIR; currentLIR->prev = newLIR; } + +/* + * Insert an LIR instruction after the current instruction, which cannot be the + * first instruction. + * + * currentLIR -> newLIR -> oldNext + */ +void dvmCompilerInsertLIRAfter(LIR *currentLIR, LIR *newLIR) +{ + newLIR->prev = currentLIR; + newLIR->next = currentLIR->next; + currentLIR->next = newLIR; + newLIR->next->prev = newLIR; +} |