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| author | Dave Butcher <david.butcher@arm.com> | 2010-06-02 14:52:21 +0100 |
|---|---|---|
| committer | Steve Kondik <shade@chemlab.org> | 2010-06-07 19:21:01 -0400 |
| commit | dd6c2479357965dd3e10c97f6a4d59de9e176557 (patch) | |
| tree | 71befc1f615b62688f5800e8a181a910eec51021 | |
| parent | d1dbd9b7318ffe8ab05028ebde4a49c7647028a0 (diff) | |
| download | android_dalvik-eclair.tar.gz android_dalvik-eclair.tar.bz2 android_dalvik-eclair.zip | |
Fix for use of UNPREDICTABLE register combinationeclair
Use of the LDRD instruction form LDRD Rt, Rt2, [Rn, Rm] has restrictions
on the register combinations - specifically if Rt or Rt2 is equal to Rn or
Rm the behaviour is defined as 'UNPREDICTABLE'.
Change-Id: I19834783865e07897cc7012367e698447f023ce6
| -rw-r--r-- | vm/mterp/armv5te/OP_IGET_WIDE_QUICK.S | 4 | ||||
| -rw-r--r-- | vm/mterp/armv6t2/OP_IGET_WIDE_QUICK.S | 4 | ||||
| -rw-r--r-- | vm/mterp/out/InterpAsm-armv5te-vfp.S | 4 | ||||
| -rw-r--r-- | vm/mterp/out/InterpAsm-armv5te.S | 4 | ||||
| -rw-r--r-- | vm/mterp/out/InterpAsm-armv7-a.S | 4 |
5 files changed, 10 insertions, 10 deletions
diff --git a/vm/mterp/armv5te/OP_IGET_WIDE_QUICK.S b/vm/mterp/armv5te/OP_IGET_WIDE_QUICK.S index ece7e7a73..189b683e7 100644 --- a/vm/mterp/armv5te/OP_IGET_WIDE_QUICK.S +++ b/vm/mterp/armv5te/OP_IGET_WIDE_QUICK.S @@ -3,11 +3,11 @@ /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B GET_VREG(r3, r2) @ r3<- object we're operating on - FETCH(r1, 1) @ r1<- field byte offset + FETCH(ip, 1) @ ip<- field byte offset cmp r3, #0 @ check object for null mov r2, rINST, lsr #8 @ r2<- A(+) beq common_errNullObject @ object was null - ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) and r2, r2, #15 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] diff --git a/vm/mterp/armv6t2/OP_IGET_WIDE_QUICK.S b/vm/mterp/armv6t2/OP_IGET_WIDE_QUICK.S index 129f4242e..98abf724e 100644 --- a/vm/mterp/armv6t2/OP_IGET_WIDE_QUICK.S +++ b/vm/mterp/armv6t2/OP_IGET_WIDE_QUICK.S @@ -2,12 +2,12 @@ %verify "null object" /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B - FETCH(r1, 1) @ r1<- field byte offset + FETCH(ip, 1) @ ip<- field byte offset GET_VREG(r3, r2) @ r3<- object we're operating on ubfx r2, rINST, #8, #4 @ r2<- A cmp r3, #0 @ check object for null beq common_errNullObject @ object was null - ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) FETCH_ADVANCE_INST(2) @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] GET_INST_OPCODE(ip) @ extract opcode from rINST diff --git a/vm/mterp/out/InterpAsm-armv5te-vfp.S b/vm/mterp/out/InterpAsm-armv5te-vfp.S index cea683a86..9f982a2f0 100644 --- a/vm/mterp/out/InterpAsm-armv5te-vfp.S +++ b/vm/mterp/out/InterpAsm-armv5te-vfp.S @@ -7406,11 +7406,11 @@ dalvik_inst: /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B GET_VREG(r3, r2) @ r3<- object we're operating on - FETCH(r1, 1) @ r1<- field byte offset + FETCH(ip, 1) @ ip<- field byte offset cmp r3, #0 @ check object for null mov r2, rINST, lsr #8 @ r2<- A(+) beq common_errNullObject @ object was null - ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) and r2, r2, #15 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] diff --git a/vm/mterp/out/InterpAsm-armv5te.S b/vm/mterp/out/InterpAsm-armv5te.S index bafd44242..d20f841e5 100644 --- a/vm/mterp/out/InterpAsm-armv5te.S +++ b/vm/mterp/out/InterpAsm-armv5te.S @@ -7726,11 +7726,11 @@ d2i_doconv: /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B GET_VREG(r3, r2) @ r3<- object we're operating on - FETCH(r1, 1) @ r1<- field byte offset + FETCH(ip, 1) @ ip<- field byte offset cmp r3, #0 @ check object for null mov r2, rINST, lsr #8 @ r2<- A(+) beq common_errNullObject @ object was null - ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) and r2, r2, #15 FETCH_ADVANCE_INST(2) @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] diff --git a/vm/mterp/out/InterpAsm-armv7-a.S b/vm/mterp/out/InterpAsm-armv7-a.S index 8d018c118..b4da0c37e 100644 --- a/vm/mterp/out/InterpAsm-armv7-a.S +++ b/vm/mterp/out/InterpAsm-armv7-a.S @@ -7328,12 +7328,12 @@ dalvik_inst: /* File: armv6t2/OP_IGET_WIDE_QUICK.S */ /* iget-wide-quick vA, vB, offset@CCCC */ mov r2, rINST, lsr #12 @ r2<- B - FETCH(r1, 1) @ r1<- field byte offset + FETCH(ip, 1) @ ip<- field byte offset GET_VREG(r3, r2) @ r3<- object we're operating on ubfx r2, rINST, #8, #4 @ r2<- A cmp r3, #0 @ check object for null beq common_errNullObject @ object was null - ldrd r0, [r3, r1] @ r0<- obj.field (64 bits, aligned) + ldrd r0, [r3, ip] @ r0<- obj.field (64 bits, aligned) FETCH_ADVANCE_INST(2) @ advance rPC, load rINST add r3, rFP, r2, lsl #2 @ r3<- &fp[A] GET_INST_OPCODE(ip) @ extract opcode from rINST |