Merge branch 'eclair' of git@github.com:cyanogen/android_dalvik into donutdonut

2 files changed, 155 insertions, 44 deletions

diff --git a/libdex/OptInvocation.c b/libdex/OptInvocation.c
index f01c5e26c..8552cfd2e 100644
--- a/libdex/OptInvocation.c
+++ b/libdex/OptInvocation.c
@@ -50,6 +50,8 @@ char* dexOptGenerateCacheFileName(const char* fileName, const char* subFileName)
     const size_t kBufLen = sizeof(nameBuf) - 1;
     const char* dataRoot;
     const char* systemRoot;
+    const char* sdExtRoot;
+    const char* cacheRoot;
     char* cp;
 
     /*
@@ -82,12 +84,33 @@ char* dexOptGenerateCacheFileName(const char* fileName, const char* subFileName)
 
     dataRoot = getenv("ANDROID_DATA");
     systemRoot = getenv("ANDROID_ROOT");
+    sdExtRoot = getenv("SD_EXT_DIRECTORY");
+    cacheRoot = getenv("CACHE_ROOT");
+
+    /* Set some default values just in case the enviornment variables
+     * do not exist.  This will probably never happen, but is good
+     * practice nonetheless.
+     */
+    if (dataRoot == NULL)
+        dataRoot = "/data";
+
+    if (systemRoot == NULL)
+        systemRoot = "/system";
     
-    if (systemRoot != NULL && !strncmp(absoluteFile, systemRoot, strlen(systemRoot))) 
-        dataRoot = "/cache";
+    if (sdExtRoot == NULL)
+        sdExtRoot = "/sd-ext";
+
+    if (cacheRoot == NULL)
+        cacheRoot = "/cache";
     
-    if (dataRoot == NULL) 
-        dataRoot = "/data";
+    /* Determine where to store dalvik-cache based on the
+     * location of the binary we are dexopt'ing
+     */
+    if (systemRoot != NULL && !strncmp(absoluteFile, systemRoot, strlen(systemRoot))) 
+        dataRoot = cacheRoot;
+
+    if (sdExtRoot != NULL && !strncmp(absoluteFile, sdExtRoot, strlen(sdExtRoot)))
+        dataRoot = sdExtRoot;
 
     /* Turn the path into a flat filename by replacing
      * any slashes after the first one with '@' characters.
diff --git a/vm/mterp/out/InterpAsm-armv5te.S b/vm/mterp/out/InterpAsm-armv5te.S
index bafd44242..fd48b99ce 100644
--- a/vm/mterp/out/InterpAsm-armv5te.S
+++ b/vm/mterp/out/InterpAsm-armv5te.S
@@ -5143,7 +5143,12 @@ d2i_doconv:
 
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
                                @ optional op; may set condition codes
-    bl      __aeabi_fadd                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fadd                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fadds	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -5185,7 +5190,12 @@ d2i_doconv:
 
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
                                @ optional op; may set condition codes
-    bl      __aeabi_fsub                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fsub                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fsubs	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -5227,7 +5237,12 @@ d2i_doconv:
 
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
                                @ optional op; may set condition codes
-    bl      __aeabi_fmul                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fmul                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fmuls	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -5269,7 +5284,12 @@ d2i_doconv:
 
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
                                @ optional op; may set condition codes
-    bl      __aeabi_fdiv                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fdiv                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fdivs	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -5348,8 +5368,10 @@ d2i_doconv:
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[AA]
     add     r2, rFP, r2, lsl #2         @ r2<- &fp[BB]
     add     r3, rFP, r3, lsl #2         @ r3<- &fp[CC]
-    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
-    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+@    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
+@    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+    fldd	d6, [r2, #0]
+    fldd	d7, [r3, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -5357,9 +5379,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_dadd                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_dadd                              @ result<- op, r0-r3 changed
+    faddd	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 14-17 instructions */
 
@@ -5393,8 +5419,10 @@ d2i_doconv:
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[AA]
     add     r2, rFP, r2, lsl #2         @ r2<- &fp[BB]
     add     r3, rFP, r3, lsl #2         @ r3<- &fp[CC]
-    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
-    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+@    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
+@    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+    fldd	d6, [r2, #0]
+    fldd	d7, [r3, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -5402,9 +5430,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_dsub                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_dsub                              @ result<- op, r0-r3 changed
+    fsubd	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@   stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 14-17 instructions */
 
@@ -5438,8 +5470,10 @@ d2i_doconv:
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[AA]
     add     r2, rFP, r2, lsl #2         @ r2<- &fp[BB]
     add     r3, rFP, r3, lsl #2         @ r3<- &fp[CC]
-    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
-    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+@    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
+@    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+    fldd	d6, [r2, #0]
+    fldd	d7, [r3, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -5447,9 +5481,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_dmul                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_dmul                              @ result<- op, r0-r3 changed
+    fmuld	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 14-17 instructions */
 
@@ -5483,8 +5521,10 @@ d2i_doconv:
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[AA]
     add     r2, rFP, r2, lsl #2         @ r2<- &fp[BB]
     add     r3, rFP, r3, lsl #2         @ r3<- &fp[CC]
-    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
-    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+@    ldmia   r2, {r0-r1}                 @ r0/r1<- vBB/vBB+1
+@    ldmia   r3, {r2-r3}                 @ r2/r3<- vCC/vCC+1
+    fldd	d6, [r2, #0]
+    fldd	d7, [r3, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -5492,9 +5532,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(2)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_ddiv                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_ddiv                              @ result<- op, r0-r3 changed
+    fdivd	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 14-17 instructions */
 
@@ -6424,7 +6468,12 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_fadd                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fadd                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fadds	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -6464,7 +6513,12 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_fsub                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fsub                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fsubs	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -6504,7 +6558,12 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_fmul                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fmul                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fmuls	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -6544,7 +6603,12 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_fdiv                              @ r0<- op, r0-r3 changed
+@    bl      __aeabi_fdiv                              @ r0<- op, r0-r3 changed
+    fmsr	s14, r0
+    fmsr	s15, r1
+    fdivs	s14, s14, s15
+    fmrs	r0, s14
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
     SET_VREG(r0, r9)               @ vAA<- r0
     GOTO_OPCODE(ip)                     @ jump to next instruction
@@ -6618,8 +6682,10 @@ d2i_doconv:
     and     r9, r9, #15
     add     r1, rFP, r1, lsl #2         @ r1<- &fp[B]
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[A]
-    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
-    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+@    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
+@    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+    fldd	d7, [r1, #0]
+    fldd	d6, [r9, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -6627,9 +6693,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_dadd                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_dadd                              @ result<- op, r0-r3 changed
+    faddd	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 12-15 instructions */
 
@@ -6660,8 +6730,10 @@ d2i_doconv:
     and     r9, r9, #15
     add     r1, rFP, r1, lsl #2         @ r1<- &fp[B]
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[A]
-    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
-    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+@    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
+@    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+    fldd	d7, [r1, #0]
+    fldd	d6, [r9, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -6669,9 +6741,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_dsub                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_dsub                              @ result<- op, r0-r3 changed
+    fsubd	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 12-15 instructions */
 
@@ -6702,8 +6778,10 @@ d2i_doconv:
     and     r9, r9, #15
     add     r1, rFP, r1, lsl #2         @ r1<- &fp[B]
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[A]
-    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
-    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+@    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
+@    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+    fldd	d7, [r1, #0]
+    fldd	d6, [r9, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -6711,9 +6789,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_dmul                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_dmul                              @ result<- op, r0-r3 changed
+    fmuld	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 12-15 instructions */
 
@@ -6744,8 +6826,10 @@ d2i_doconv:
     and     r9, r9, #15
     add     r1, rFP, r1, lsl #2         @ r1<- &fp[B]
     add     r9, rFP, r9, lsl #2         @ r9<- &fp[A]
-    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
-    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+@    ldmia   r1, {r2-r3}                 @ r2/r3<- vBB/vBB+1
+@    ldmia   r9, {r0-r1}                 @ r0/r1<- vAA/vAA+1
+    fldd	d7, [r1, #0]
+    fldd	d6, [r9, #0]
     .if 0
     orrs    ip, r2, r3                  @ second arg (r2-r3) is zero?
     beq     common_errDivideByZero
@@ -6753,9 +6837,13 @@ d2i_doconv:
     FETCH_ADVANCE_INST(1)               @ advance rPC, load rINST
 
                                @ optional op; may set condition codes
-    bl      __aeabi_ddiv                              @ result<- op, r0-r3 changed
+@    bl      __aeabi_ddiv                              @ result<- op, r0-r3 changed
+    fdivd	d6, d6, d7
+
     GET_INST_OPCODE(ip)                 @ extract opcode from rINST
-    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+@    stmia   r9, {r0,r1}     @ vAA/vAA+1<- r0/r1
+    fstd	d6, [r9, #0]
+
     GOTO_OPCODE(ip)                     @ jump to next instruction
     /* 12-15 instructions */