diff options
| -rw-r--r-- | libm/arm/fenv.h | 218 | ||||
| -rw-r--r-- | libm/include/arm/fenv.h | 260 | ||||
| -rw-r--r-- | libm/mips/fenv.h | 220 | ||||
| -rw-r--r-- | tests/Android.mk | 1 | ||||
| -rw-r--r-- | tests/fenv_test.cpp | 81 |
5 files changed, 191 insertions, 589 deletions
diff --git a/libm/arm/fenv.h b/libm/arm/fenv.h deleted file mode 100644 index 534b12cbd..000000000 --- a/libm/arm/fenv.h +++ /dev/null @@ -1,218 +0,0 @@ -/*- - * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ - */ - -#ifndef _FENV_H_ -#define _FENV_H_ - -#include <sys/types.h> - -__BEGIN_DECLS - -typedef uint32_t fenv_t; -typedef uint32_t fexcept_t; - -/* Exception flags */ -#define FE_INVALID 0x0001 -#define FE_DIVBYZERO 0x0002 -#define FE_OVERFLOW 0x0004 -#define FE_UNDERFLOW 0x0008 -#define FE_INEXACT 0x0010 -#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ - FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) - -/* Rounding modes */ -#define FE_TONEAREST 0x0000 -#define FE_TOWARDZERO 0x0001 -#define FE_UPWARD 0x0002 -#define FE_DOWNWARD 0x0003 -#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ - FE_UPWARD | FE_TOWARDZERO) - -/* Default floating-point environment */ -extern const fenv_t __fe_dfl_env; -#define FE_DFL_ENV (&__fe_dfl_env) - -/* We need to be able to map status flag positions to mask flag positions */ -#define _FPUSW_SHIFT 16 -#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) - -#ifdef ARM_HARD_FLOAT -#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr))) -#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr)) -#else -#define __rfs(__fpsr) -#define __wfs(__fpsr) -#endif - -static __inline int -feclearexcept(int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __fpsr &= ~__excepts; - __wfs(__fpsr); - return (0); -} - -static __inline int -fegetexceptflag(fexcept_t *__flagp, int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - *__flagp = __fpsr & __excepts; - return (0); -} - -static __inline int -fesetexceptflag(const fexcept_t *__flagp, int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __fpsr &= ~__excepts; - __fpsr |= *__flagp & __excepts; - __wfs(__fpsr); - return (0); -} - -static __inline int -feraiseexcept(int __excepts) -{ - fexcept_t __ex = __excepts; - - fesetexceptflag(&__ex, __excepts); /* XXX */ - return (0); -} - -static __inline int -fetestexcept(int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - return (__fpsr & __excepts); -} - -static __inline int -fegetround(void) -{ - - /* - * Apparently, the rounding mode is specified as part of the - * instruction format on ARM, so the dynamic rounding mode is - * indeterminate. Some FPUs may differ. - */ - return (-1); -} - -static __inline int -fesetround(int __round) -{ - - return (-1); -} - -static __inline int -fegetenv(fenv_t *__envp) -{ - - __rfs(__envp); - return (0); -} - -static __inline int -feholdexcept(fenv_t *__envp) -{ - fenv_t __env; - - __rfs(&__env); - *__envp = __env; - __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); - __wfs(__env); - return (0); -} - -static __inline int -fesetenv(const fenv_t *__envp) -{ - - __wfs(*__envp); - return (0); -} - -static __inline int -feupdateenv(const fenv_t *__envp) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __wfs(*__envp); - feraiseexcept(__fpsr & FE_ALL_EXCEPT); - return (0); -} - -#if __BSD_VISIBLE - -static __inline int -feenableexcept(int __mask) -{ - fenv_t __old_fpsr, __new_fpsr; - - __rfs(&__old_fpsr); - __new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT; - __wfs(__new_fpsr); - return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); -} - -static __inline int -fedisableexcept(int __mask) -{ - fenv_t __old_fpsr, __new_fpsr; - - __rfs(&__old_fpsr); - __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); - __wfs(__new_fpsr); - return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); -} - -static __inline int -fegetexcept(void) -{ - fenv_t __fpsr; - - __rfs(&__fpsr); - return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT); -} - -#endif /* __BSD_VISIBLE */ - -__END_DECLS - -#endif /* !_FENV_H_ */ diff --git a/libm/include/arm/fenv.h b/libm/include/arm/fenv.h index da7e69652..a96f99ed8 100644 --- a/libm/include/arm/fenv.h +++ b/libm/include/arm/fenv.h @@ -26,193 +26,151 @@ * $FreeBSD: src/lib/msun/arm/fenv.h,v 1.5 2005/03/16 19:03:45 das Exp $ */ -#ifndef _FENV_H_ -#define _FENV_H_ +/* + * Rewritten for Android. + * + * The ARM FPSCR is described here: + * http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0344b/Chdfafia.html + */ + +#ifndef _FENV_H_ +#define _FENV_H_ #include <sys/types.h> __BEGIN_DECLS -typedef __uint32_t fenv_t; -typedef __uint32_t fexcept_t; - -/* Exception flags */ -#define FE_INVALID 0x0001 -#define FE_DIVBYZERO 0x0002 -#define FE_OVERFLOW 0x0004 -#define FE_UNDERFLOW 0x0008 -#define FE_INEXACT 0x0010 -#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ - FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) - -/* Rounding modes */ -#define FE_TONEAREST 0x0000 -#define FE_TOWARDZERO 0x0001 -#define FE_UPWARD 0x0002 -#define FE_DOWNWARD 0x0003 -#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ - FE_UPWARD | FE_TOWARDZERO) - -/* Default floating-point environment */ -extern const fenv_t __fe_dfl_env; -#define FE_DFL_ENV (&__fe_dfl_env) - -/* We need to be able to map status flag positions to mask flag positions */ -#define _FPUSW_SHIFT 16 -#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) - -#ifdef ARM_HARD_FLOAT -#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr))) -#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr)) -#else -#define __rfs(__fpsr) -#define __wfs(__fpsr) -#endif - -static __inline int -feclearexcept(int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __fpsr &= ~__excepts; - __wfs(__fpsr); - return (0); +typedef __uint32_t fenv_t; +typedef __uint32_t fexcept_t; + +/* Exception flags. */ +#define FE_INVALID 0x01 +#define FE_DIVBYZERO 0x02 +#define FE_OVERFLOW 0x04 +#define FE_UNDERFLOW 0x08 +#define FE_INEXACT 0x10 +#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) +#define _FPSCR_ENABLE_SHIFT 8 +#define _FPSCR_ENABLE_MASK (FE_ALL_EXCEPT << _FPSCR_ENABLE_SHIFT) + +/* Rounding modes. */ +#define FE_TONEAREST 0x0 +#define FE_UPWARD 0x1 +#define FE_DOWNWARD 0x2 +#define FE_TOWARDZERO 0x3 +#define _FPSCR_RMODE_SHIFT 22 + +/* Default floating-point environment. */ +extern const fenv_t __fe_dfl_env; +#define FE_DFL_ENV (&__fe_dfl_env) + +static __inline int fegetenv(fenv_t* __envp) { + fenv_t _fpscr; + __asm__ __volatile__("vmrs %0,fpscr" : "=r" (_fpscr)); + *__envp = _fpscr; + return 0; } -static __inline int -fegetexceptflag(fexcept_t *__flagp, int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - *__flagp = __fpsr & __excepts; - return (0); +static __inline int fesetenv(const fenv_t* __envp) { + fenv_t _fpscr = *__envp; + __asm__ __volatile__("vmsr fpscr,%0" : :"ri" (_fpscr)); + return 0; } -static __inline int -fesetexceptflag(const fexcept_t *__flagp, int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __fpsr &= ~__excepts; - __fpsr |= *__flagp & __excepts; - __wfs(__fpsr); - return (0); +static __inline int feclearexcept(int __excepts) { + fexcept_t __fpscr; + fegetenv(&__fpscr); + __fpscr &= ~__excepts; + fesetenv(&__fpscr); + return 0; } -static __inline int -feraiseexcept(int __excepts) -{ - fexcept_t __ex = __excepts; - - fesetexceptflag(&__ex, __excepts); /* XXX */ - return (0); +static __inline int fegetexceptflag(fexcept_t* __flagp, int __excepts) { + fexcept_t __fpscr; + fegetenv(&__fpscr); + *__flagp = __fpscr & __excepts; + return 0; } -static __inline int -fetestexcept(int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - return (__fpsr & __excepts); +static __inline int fesetexceptflag(const fexcept_t* __flagp, int __excepts) { + fexcept_t __fpscr; + fegetenv(&__fpscr); + __fpscr &= ~__excepts; + __fpscr |= *__flagp & __excepts; + fesetenv(&__fpscr); + return 0; } -static __inline int -fegetround(void) -{ - - /* - * Apparently, the rounding mode is specified as part of the - * instruction format on ARM, so the dynamic rounding mode is - * indeterminate. Some FPUs may differ. - */ - return (-1); +static __inline int feraiseexcept(int __excepts) { + fexcept_t __ex = __excepts; + fesetexceptflag(&__ex, __excepts); + return 0; } -static __inline int -fesetround(int __round) -{ - - return (-1); +static __inline int fetestexcept(int __excepts) { + fexcept_t __fpscr; + fegetenv(&__fpscr); + return (__fpscr & __excepts); } -static __inline int -fegetenv(fenv_t *__envp) -{ - - __rfs(__envp); - return (0); +static __inline int fegetround(void) { + fenv_t _fpscr; + fegetenv(&_fpscr); + return ((_fpscr >> _FPSCR_RMODE_SHIFT) & 0x3); } -static __inline int -feholdexcept(fenv_t *__envp) -{ - fenv_t __env; - - __rfs(&__env); - *__envp = __env; - __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); - __wfs(__env); - return (0); +static __inline int fesetround(int __round) { + fenv_t _fpscr; + fegetenv(&_fpscr); + _fpscr &= ~(0x3 << _FPSCR_RMODE_SHIFT); + _fpscr |= (__round << _FPSCR_RMODE_SHIFT); + fesetenv(&_fpscr); + return 0; } -static __inline int -fesetenv(const fenv_t *__envp) -{ - - __wfs(*__envp); - return (0); +static __inline int feholdexcept(fenv_t* __envp) { + fenv_t __env; + fegetenv(&__env); + *__envp = __env; + __env &= ~(FE_ALL_EXCEPT | _FPSCR_ENABLE_MASK); + fesetenv(&__env); + return 0; } -static __inline int -feupdateenv(const fenv_t *__envp) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __wfs(*__envp); - feraiseexcept(__fpsr & FE_ALL_EXCEPT); - return (0); +static __inline int feupdateenv(const fenv_t* __envp) { + fexcept_t __fpscr; + fegetenv(&__fpscr); + fesetenv(__envp); + feraiseexcept(__fpscr & FE_ALL_EXCEPT); + return 0; } #if __BSD_VISIBLE -static __inline int -feenableexcept(int __mask) -{ - fenv_t __old_fpsr, __new_fpsr; - - __rfs(&__old_fpsr); - __new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT; - __wfs(__new_fpsr); - return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); +static __inline int feenableexcept(int __mask) { + fenv_t __old_fpscr, __new_fpscr; + fegetenv(&__old_fpscr); + __new_fpscr = __old_fpscr | (__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT; + fesetenv(&__new_fpscr); + return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT); } -static __inline int -fedisableexcept(int __mask) -{ - fenv_t __old_fpsr, __new_fpsr; - - __rfs(&__old_fpsr); - __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); - __wfs(__new_fpsr); - return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); +static __inline int fedisableexcept(int __mask) { + fenv_t __old_fpscr, __new_fpscr; + fegetenv(&__old_fpscr); + __new_fpscr = __old_fpscr & ~((__mask & FE_ALL_EXCEPT) << _FPSCR_ENABLE_SHIFT); + fesetenv(&__new_fpscr); + return ((__old_fpscr >> _FPSCR_ENABLE_SHIFT) & FE_ALL_EXCEPT); } -static __inline int -fegetexcept(void) -{ - fenv_t __fpsr; - - __rfs(&__fpsr); - return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT); +static __inline int fegetexcept(void) { + fenv_t __fpscr; + fegetenv(&__fpscr); + return ((__fpscr & _FPSCR_ENABLE_MASK) >> _FPSCR_ENABLE_SHIFT); } #endif /* __BSD_VISIBLE */ __END_DECLS -#endif /* !_FENV_H_ */ +#endif /* !_FENV_H_ */ diff --git a/libm/mips/fenv.h b/libm/mips/fenv.h deleted file mode 100644 index 583d0022f..000000000 --- a/libm/mips/fenv.h +++ /dev/null @@ -1,220 +0,0 @@ -/*- - * Copyright (c) 2004-2005 David Schultz <das@FreeBSD.ORG> - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions - * are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * - * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND - * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS - * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) - * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT - * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY - * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF - * SUCH DAMAGE. - * - * $FreeBSD: src/lib/msun/mips/fenv.h,v 1.1 2008/04/26 12:20:29 imp Exp $ - */ - -#ifndef _FENV_H_ -#define _FENV_H_ - -#include <sys/cdefs.h> -#include <sys/_types.h> - -__BEGIN_DECLS - -typedef __uint32_t fenv_t; -typedef __uint32_t fexcept_t; - -/* Exception flags */ -#define FE_INVALID 0x0001 -#define FE_DIVBYZERO 0x0002 -#define FE_OVERFLOW 0x0004 -#define FE_UNDERFLOW 0x0008 -#define FE_INEXACT 0x0010 -#define FE_ALL_EXCEPT (FE_DIVBYZERO | FE_INEXACT | \ - FE_INVALID | FE_OVERFLOW | FE_UNDERFLOW) - -/* Rounding modes */ -#define FE_TONEAREST 0x0000 -#define FE_TOWARDZERO 0x0001 -#define FE_UPWARD 0x0002 -#define FE_DOWNWARD 0x0003 -#define _ROUND_MASK (FE_TONEAREST | FE_DOWNWARD | \ - FE_UPWARD | FE_TOWARDZERO) - -/* Default floating-point environment */ -extern const fenv_t __fe_dfl_env; -#define FE_DFL_ENV (&__fe_dfl_env) - -/* We need to be able to map status flag positions to mask flag positions */ -#define _FPUSW_SHIFT 16 -#define _ENABLE_MASK (FE_ALL_EXCEPT << _FPUSW_SHIFT) - -#ifdef ARM_HARD_FLOAT -#define __rfs(__fpsr) __asm __volatile("rfs %0" : "=r" (*(__fpsr))) -#define __wfs(__fpsr) __asm __volatile("wfs %0" : : "r" (__fpsr)) -#else -#define __rfs(__fpsr) -#define __wfs(__fpsr) -#endif - -static __inline int -feclearexcept(int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __fpsr &= ~__excepts; - __wfs(__fpsr); - return (0); -} - -static __inline int -fegetexceptflag(fexcept_t *__flagp, int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - *__flagp = __fpsr & __excepts; - return (0); -} - -static __inline int -fesetexceptflag(const fexcept_t *__flagp, int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __fpsr &= ~__excepts; - __fpsr |= *__flagp & __excepts; - __wfs(__fpsr); - return (0); -} - -static __inline int -feraiseexcept(int __excepts) -{ - fexcept_t __ex = __excepts; - - fesetexceptflag(&__ex, __excepts); /* XXX */ - return (0); -} - -static __inline int -fetestexcept(int __excepts) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - return (__fpsr & __excepts); -} - -static __inline int -fegetround(void) -{ - - /* - * Apparently, the rounding mode is specified as part of the - * instruction format on ARM, so the dynamic rounding mode is - * indeterminate. Some FPUs may differ. - */ - return (-1); -} - -static __inline int -fesetround(int __round) -{ - - return (-1); -} - -static __inline int -fegetenv(fenv_t *__envp) -{ - - __rfs(__envp); - return (0); -} - -static __inline int -feholdexcept(fenv_t *__envp) -{ - fenv_t __env; - - __rfs(&__env); - *__envp = __env; - __env &= ~(FE_ALL_EXCEPT | _ENABLE_MASK); - __wfs(__env); - return (0); -} - -static __inline int -fesetenv(const fenv_t *__envp) -{ - - __wfs(*__envp); - return (0); -} - -static __inline int -feupdateenv(const fenv_t *__envp) -{ - fexcept_t __fpsr; - - __rfs(&__fpsr); - __wfs(*__envp); - feraiseexcept(__fpsr & FE_ALL_EXCEPT); - return (0); -} - -#if __BSD_VISIBLE - -static __inline int -feenableexcept(int __mask) -{ - fenv_t __old_fpsr, __new_fpsr; - - __rfs(&__old_fpsr); - __new_fpsr = __old_fpsr | (__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT; - __wfs(__new_fpsr); - return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); -} - -static __inline int -fedisableexcept(int __mask) -{ - fenv_t __old_fpsr, __new_fpsr; - - __rfs(&__old_fpsr); - __new_fpsr = __old_fpsr & ~((__mask & FE_ALL_EXCEPT) << _FPUSW_SHIFT); - __wfs(__new_fpsr); - return ((__old_fpsr >> _FPUSW_SHIFT) & FE_ALL_EXCEPT); -} - -static __inline int -fegetexcept(void) -{ - fenv_t __fpsr; - - __rfs(&__fpsr); - return ((__fpsr & _ENABLE_MASK) >> _FPUSW_SHIFT); -} - -#endif /* __BSD_VISIBLE */ - -__END_DECLS - -#endif /* !_FENV_H_ */ - diff --git a/tests/Android.mk b/tests/Android.mk index 9d5cd36a7..66d023f2a 100644 --- a/tests/Android.mk +++ b/tests/Android.mk @@ -26,6 +26,7 @@ test_c_flags = \ test_src_files = \ dirent_test.cpp \ + fenv_test.cpp \ getcwd_test.cpp \ libgen_test.cpp \ pthread_test.cpp \ diff --git a/tests/fenv_test.cpp b/tests/fenv_test.cpp new file mode 100644 index 000000000..4adb06658 --- /dev/null +++ b/tests/fenv_test.cpp @@ -0,0 +1,81 @@ +/* + * Copyright (C) 2012 The Android Open Source Project + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#include <gtest/gtest.h> + +#include <fenv.h> +#include <stdint.h> + +static void TestRounding(float expectation1, float expectation2) { + // volatile to prevent compiler optimizations. + volatile float f = 1.968750f; + volatile float m = 0x1.0p23f; + volatile float x = f + m; + ASSERT_FLOAT_EQ(expectation1, x); + x -= m; + ASSERT_EQ(expectation2, x); +} + +static void DivideByZero() { + // volatile to prevent compiler optimizations. + volatile float zero = 0.0f; + volatile float result __attribute__((unused)) = 123.0f / zero; +} + +TEST(fenv, fesetround_fegetround_FE_TONEAREST) { + fesetround(FE_TONEAREST); + ASSERT_EQ(FE_TONEAREST, fegetround()); + TestRounding(8388610.0f, 2.0f); +} + +TEST(fenv, fesetround_fegetround_FE_TOWARDZERO) { + fesetround(FE_TOWARDZERO); + ASSERT_EQ(FE_TOWARDZERO, fegetround()); + TestRounding(8388609.0f, 1.0f); +} + +TEST(fenv, fesetround_fegetround_FE_UPWARD) { + fesetround(FE_UPWARD); + ASSERT_EQ(FE_UPWARD, fegetround()); + TestRounding(8388610.0f, 2.0f); +} + +TEST(fenv, fesetround_fegetround_FE_DOWNWARD) { + fesetround(FE_DOWNWARD); + ASSERT_EQ(FE_DOWNWARD, fegetround()); + TestRounding(8388609.0f, 1.0f); +} + +TEST(fenv, feclearexcept_fetestexcept) { + // Clearing clears. + feclearexcept(FE_ALL_EXCEPT); + ASSERT_EQ(0, fetestexcept(FE_ALL_EXCEPT)); + + // Dividing by zero sets FE_DIVBYZERO. + DivideByZero(); + int raised = fetestexcept(FE_DIVBYZERO | FE_OVERFLOW); + ASSERT_TRUE((raised & FE_OVERFLOW) == 0); + ASSERT_TRUE((raised & FE_DIVBYZERO) != 0); + + // Clearing an unset bit is a no-op. + feclearexcept(FE_OVERFLOW); + ASSERT_TRUE((raised & FE_OVERFLOW) == 0); + ASSERT_TRUE((raised & FE_DIVBYZERO) != 0); + + // Clearing a set bit works. + feclearexcept(FE_DIVBYZERO); + ASSERT_EQ(0, fetestexcept(FE_ALL_EXCEPT)); +} |