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| * | | | Remove the old CFI infrastructure.David Srbecky2015-04-079-391/+13
| |/ / / | | | | | | | | | | | | Change-Id: I12a17a8a1c39ffccaa499c328ebac36e4d74dc4e
* | | | Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for words."Roland Levillain2015-04-081-0/+44
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| * | Exercise art::arm::Thumb2Assembler::StoreToOffset for words.Roland Levillain2015-04-021-0/+44
| | | | | | | | | | | | Change-Id: Ifa82e69c055eb99e526fc7ab5db54bde988d2caf
* | | Fix JNI compiler for mips64Goran Jakovljevic2015-04-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Fix assembly instructions in JNI stub to store the right size. Fix callee-saves in JNI calling convention to reflect return registers. Fix pointer size in mips64 assembler. Change-Id: I4eccd1f56f62fa9119918192ec424e9073398bc7
* | | ART: Enable more Clang warningsAndreas Gampe2015-04-063-6/+3
| | | | | | | | | | | | Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
* | | ART: Enable Clang's -WdeprecatedAndreas Gampe2015-04-061-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Replace throw() with noexcept. Add default copy constructors and copy assignment constructors for cases with destructors, as the implicit definition is deprecated. Change-Id: Ice306a3f510b072b00bec4d4360f7c8055135c9d
* | | ART: Add Clang's -Wused-but-marked-unusedAndreas Gampe2015-04-031-1/+1
| | | | | | | | | | | | | | | | | | Add detection of wrong unused annotations. Fix our codebase. Change-Id: I85cc20f2eac71c1ec6c5c7cd6efb08454a629634
* | | Merge "[optimizing] Implement x86/x86_64 math intrinsics"Andreas Gampe2015-04-026-0/+121
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| * | [optimizing] Implement x86/x86_64 math intrinsicsMark Mendell2015-04-016-0/+121
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement floor/ceil/round/RoundFloat on x86 and x86_64. Implement RoundDouble on x86_64. Add support for roundss and roundsd on both architectures. Support them in the disassembler as well. Add the instruction set features for x86, as the 'round' instruction is only supported if SSE4.1 is supported. Fix the tests to handle the addition of passing the instruction set features to x86 and x86_64. Add assembler tests for roundsd and roundss to x86_64 assembler tests. Change-Id: I9742d5930befb0bbc23f3d6c83ce0183ed9fe04f Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Merge "ARM64: Update to VIXL 1.9."Andreas Gampe2015-04-011-2/+2
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| * | ARM64: Update to VIXL 1.9.Serban Constantinescu2015-03-311-2/+2
| |/ | | | | | | | | | | | | Update VIXL's interface to VIXL 1.9. Change-Id: Iebae947539cbad65488b7195aaf01de284b71cbb Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
* / Fixed layout for dex caches in boot image.Vladimir Marko2015-03-312-0/+166
|/ | | | | | | | | | | | | | | | | | | | | | | | | Define a fixed layout for dex cache arrays (type, method, string and field arrays) for dex caches in the boot image. This gives those arrays fixed offsets from the boot image code and allows PC-relative addressing of their elements. Use the PC-relative load on arm64 for relevant instructions, i.e. invoke-static, invoke-direct, const-string, const-class, check-cast and instance-of. This reduces the arm64 boot.oat on Nexus 9 by 1.1MiB. This CL provides the infrastructure and shows on the arm64 the gains that we can achieve by having fixed dex cache arrays' layout. To fully use this for the boot images, we need to implement the PC-relative addressing for other architectures. To achieve similar gains for apps, we need to move the dex cache arrays to a .bss section of the oat file. These changes will be implemented in subsequent CLs. (Also remove some compiler_driver.h dependencies to reduce incremental build times.) Change-Id: Ib1859fa4452d01d983fd92ae22b611f45a85d69b
* [optimizing] Implement X86 intrinsic supportMark Mendell2015-03-262-0/+72
| | | | | | | | | | | Implement the supported intrinsics for X86. Enhance the graph visualizer to print <U> for unallocated locations, to allow calling the graph dumper from within register allocation for debugging purposes. Change-Id: I3b0319eb70a9a4ea228f67065b4c52d13a1ae775 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* Merge changes I4b3b4d90,I70e0d78f,I2848636fCalin Juravle2015-03-253-19/+48
|\ | | | | | | | | | | | | * changes: Forbid the use of shifts in ShifterOperand in Thumb2 Make subs and adds alter flags when rn is an immediate Inline long shift code
| * Forbid the use of shifts in ShifterOperand in Thumb2Guillaume "Vermeille" Sanchez2015-03-252-0/+6
| | | | | | | | Change-Id: I4b3b4d90f11f2dd0c9a274b724051fa98982fb19
| * Make subs and adds alter flags when rn is an immediateGuillaume "Vermeille" Sanchez2015-03-252-19/+42
| | | | | | | | Change-Id: I70e0d78f155bf806222ad12a324dbd8c8fe575a1
| * Merge "Revert "Forbid the use of shifts in ShifterOperand in Thumb2""Calin Juravle2015-03-172-6/+0
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| | * Revert "Forbid the use of shifts in ShifterOperand in Thumb2"Calin Juravle2015-03-172-6/+0
| | | | | | | | | | | | | | | | | | This reverts commit bada8b0f0a10bd32d6cb87ed4e57f2aa3d7c03c2. Change-Id: Ic89c76367c8ab91cfb5d1510789ac2e352922da8
| * | Merge "Revert "Make subs alter flags when rn is an immediate""Calin Juravle2015-03-172-28/+15
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| | * | Revert "Make subs alter flags when rn is an immediate"Calin Juravle2015-03-172-28/+15
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8de00e3f5fcb99bfd7e4dc679ab7333549bec2c1. Change-Id: Ie9da31279f565f165d51d8c0036928377280e3b8
| * | | Merge "Make subs alter flags when rn is an immediate"Calin Juravle2015-03-172-15/+28
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| | * | Make subs alter flags when rn is an immediateGuillaume "Vermeille" Sanchez2015-03-172-15/+28
| | | | | | | | | | | | | | | | Change-Id: I7ea84fca5f97713871744b8ac4265a84fd6a5248
| * | | Merge "Forbid the use of shifts in ShifterOperand in Thumb2"Calin Juravle2015-03-172-0/+6
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| | * | Forbid the use of shifts in ShifterOperand in Thumb2Guillaume "Vermeille" Sanchez2015-03-112-0/+6
| | |/ | | | | | | | | | Change-Id: Ib141f53e52cce3032a42fbc991303e227c98820b
* | / [optimizing] Improve x86, x86_64 codeMark Mendell2015-03-132-4/+17
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | Tweak the generated code to allow more use of constants and other small changes - Use test vs. compare to 0 - EmitMove of 0.0 should use xorps - VisitCompare kPrimLong can use constants - cmp/add/sub/mul on x86_64 can use constants if in int32_t range - long bit operations on x86 examine long constant high/low to optimize - Use 3 operand imulq if constant is in int32_t range Change-Id: I2dd4010fdffa129fe00905b0020590fe95f3f926 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* / Revert "Revert "[optimizing] Enable x86 long support.""Nicolas Geoffray2015-03-112-0/+35
|/ | | | | | This reverts commit 154552e666347d41d95d7619c6ee56249ff4feca. Change-Id: Idc726551c249a888b7ff5fde8508ae50e81b2e13
* Revert "[optimizing] Enable x86 long support."Nicolas Geoffray2015-03-062-35/+0
| | | | | | | | Few libcore failures. This reverts commit b4ba354cf8d22b261205494875cc014f18587b50. Change-Id: I4a28d853e730dff9b69aec9555505803cf2fcd63
* [optimizing] Enable x86 long support.Nicolas Geoffray2015-03-062-0/+35
| | | | Change-Id: I9006972a65a1f191c45691104a960366747f9d16
* Stack support for Optimizing compilerSebastien Hertz2015-03-033-9/+70
| | | | | | | | | | | Allows to read/write DEX registers from physical register or stack location when the method is compiled with the Optimizing compiler. Required fixing arm and arm64 JNI compiler by saving floating point registers. Bug: 18547544 Change-Id: I401579f251d1c0a130f6cf4a93a960cdcd7518f5
* Revert "Revert "Add JIT""Mathieu Chartier2015-02-241-200/+0
| | | | | | | | Added missing EntryPointToCodePointer. This reverts commit a5ca888d715cd0c6c421313211caa1928be3e399. Change-Id: Ia74df0ef3a7babbdcb0466fd24da28e304e3f5af
* Revert "Add JIT"Nicolas Geoffray2015-02-241-0/+200
| | | | | | | | | | | | | | | Sorry, run-test crashes on target: 0-05 12:15:51.633 I/DEBUG (27995): Abort message: 'art/runtime/mirror/art_method.cc:349] Check failed: PcIsWithinQuickCode(reinterpret_cast<uintptr_t>(code), pc) java.lang.Throwable java.lang.Throwable.fillInStackTrace() pc=71e3366b code=0x71e3362d size=ad000000' 10-05 12:15:51.633 I/DEBUG (27995): r0 00000000 r1 0000542b r2 00000006 r3 00000000 10-05 12:15:51.633 I/DEBUG (27995): r4 00000006 r5 b6f9addc r6 00000002 r7 0000010c 10-05 12:15:51.633 I/DEBUG (27995): r8 b63fe1e8 r9 be8e1418 sl b6427400 fp b63fcce0 10-05 12:15:51.633 I/DEBUG (27995): ip 0000542b sp be8e1358 lr b6e9a27b pc b6e9c280 cpsr 40070010 10-05 12:15:51.633 I/DEBUG (27995): Bug: 17950037 This reverts commit 2535abe7d1fcdd0e6aca782b1f1932a703ed50a4. Change-Id: I6f88849bc6f2befed0c0aaa0b7b2a08c967a83c3
* Add JITMathieu Chartier2015-02-231-200/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently disabled by default unless -Xjit is passed in. The proposed JIT is a method JIT which works by utilizing interpreter instrumentation to request compilation of hot methods async during runtime. JIT options: -Xjit / -Xnojit -Xjitcodecachesize:N -Xjitthreshold:integervalue The JIT has a shared copy of a compiler driver which is accessed by worker threads to compile individual methods. Added JIT code cache and data cache, currently sized at 2 MB capacity by default. Most apps will only fill a small fraction of this cache however. Added support to the compiler for compiling interpreter quickened byte codes. Added test target ART_TEST_JIT=TRUE and --jit for run-test. TODO: Clean up code cache. Delete compiled methods after they are added to code cache. Add more optimizations related to runtime checks e.g. direct pointers for invokes. Add method recompilation. Move instrumentation to DexFile to improve performance and reduce memory usage. Bug: 17950037 Change-Id: Ifa5b2684a2d5059ec5a5210733900aafa3c51bca
* Merge "Replace a few std::vector with ArenaVector in Mir2Lir."Vladimir Marko2015-02-191-14/+14
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| * Replace a few std::vector with ArenaVector in Mir2Lir.Vladimir Marko2015-02-191-14/+14
| | | | | | | | Change-Id: I7867d60afc60f57cdbbfd312f02883854d65c805
* | Move arenas into runtimeMathieu Chartier2015-02-1913-1439/+6
|/ | | | | | | | | | Moved arena pool into the runtime. Motivation: Allow GC to use arena allocators, recycle arena pool for linear alloc. Bug: 19264997 Change-Id: I8ddbb6d55ee923a980b28fb656c758c5d7697c2f
* Merge "ART: Templatize IsInt & IsUint"Andreas Gampe2015-02-198-50/+58
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| * ART: Templatize IsInt & IsUintAndreas Gampe2015-02-188-50/+58
| | | | | | | | | | | | Ensure that things are used correctly. Change-Id: I76f082b32dcee28bbfb4c519daa401ac595873b3
* | Dead code elimination based on GVN results.Vladimir Marko2015-02-171-0/+4
|/ | | | Change-Id: I5b77411a8f088f0b561da14b123cf6b0501c9db5
* Merge "Clean up Scoped-/ArenaAlocator array allocations."Vladimir Marko2015-02-134-12/+14
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| * Clean up Scoped-/ArenaAlocator array allocations.Vladimir Marko2015-02-134-12/+14
| | | | | | | | Change-Id: Id718f8a4450adf1608306286fa4e6b9194022532
* | Optimize double/float immediate loading on arm.Nicolas Geoffray2015-02-131-6/+32
|/ | | | | | Also reserve a D register for temp. Change-Id: I6584d9005b0f5685c3afcd8e9153b4c87b56aa8e
* Merge "Quick: Rewrite Phi node insertion."Vladimir Marko2015-02-101-4/+0
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| * Quick: Rewrite Phi node insertion.Vladimir Marko2015-02-101-4/+0
| | | | | | | | | | | | | | | | Delay Phi node insertion to the SSAConversion pass to allow updating the vreg_to_ssa_map_ with INVALID_SREG when we omit a Phi in the pruned SSA form. Change-Id: I450dee21f7dc4353d25fc66f4d0ee01671de6e0e
* | Merge "Improve ParallelMoveResolver to work with pairs."Nicolas Geoffray2015-02-101-0/+10
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| * Improve ParallelMoveResolver to work with pairs.Nicolas Geoffray2015-02-101-0/+10
| | | | | | | | Change-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9
* | Merge "ART: Arm intrinsics for Optimizing compiler"Andreas Gampe2015-02-092-0/+13
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| * | ART: Arm intrinsics for Optimizing compilerAndreas Gampe2015-02-092-0/+13
| |/ | | | | | | | | | | Add arm32 intrinsics to the optimizing compiler. Change-Id: If4aeedbf560862074d8ee08ca4484b666d6b9bf0
* / x64 goodness.Nicolas Geoffray2015-02-062-0/+9
|/ | | | | | | | - Use test instead of cmp when comparing against 0. - Make it possible to use lea for add. - Use xor instead of mov when loading 0. Change-Id: Ide95c4e2d9b773e952412892f2df6869600c324e
* Fix build by putting ATTRIBUTE_UNUSUED.Nicolas Geoffray2015-02-031-2/+2
| | | | Change-Id: If894fa1343a7c8a6456d707e815d803404a171d7
* Fix thumb2 assembler's ShifterOperandCanHold.Nicolas Geoffray2015-02-031-7/+0
| | | | Change-Id: Ica3c5f39d52722950725ba622fc67bd7f634918a
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-16 16:42:50 +0000