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* MIPS: Initial version of optimizing compiler for MIPS64R6.Roland Levillain2015-06-263-238/+808
| | | | | | | | | | (cherry picked from commit 4dda3376b71209fae07f5c3c8ac3eb4b54207aa8) (amended for mnc-dev) Bug: 21555893 Change-Id: I874dc356eee6ab061a32f8f3df5f8ac3a4ab7dcf Signed-off-by: Alexey Frunze <Alexey.Frunze@imgtec.com> Signed-off-by: Douglas Leung <douglas.leung@imgtec.com>
* [MIPS64] JNI Compiler: Sign-extend int function argumentsLazar Trsic2015-06-241-4/+4
| | | | | | | | | | | | | | | MIPS n64 ABI differs from arm64. Arguments smaller than the 8B stack slot need to be sign-extended. Use combination (lw,sd), instead of (lw,sw) for 4B values. Change fixes software keyboard crash on mips64. Bug: 21555893 (cherry picked from commit f652d605753f1387e7797461b47116c5dcdf928d) Change-Id: I7574d37f6039e9e8c9e0047254be71d28d4c829a
* Move mirror::ArtMethod to nativeMathieu Chartier2015-06-0215-74/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
* ART: Clean up arm64 kNumberOfXRegisters usage.Vladimir Marko2015-05-2622-21/+20
| | | | | | | | | | | | | | | | | | | | | Avoid undefined behavior for arm64 stemming from 1u << 32 in loops with upper bound kNumberOfXRegisters. Create iterators for enumerating bits in an integer either from high to low or from low to high and use them for <arch>Context::FillCalleeSaves() on all architectures. Refactor runtime/utils.{h,cc} by moving all bit-fiddling functions to runtime/base/bit_utils.{h,cc} (together with the new bit iterators) and all time-related functions to runtime/base/time_utils.{h,cc}. Improve test coverage and fix some corner cases for the bit-fiddling functions. Bug: 13925192 (cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0) Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
* ART: x86 indexOf intrinsics for the optimizing compilerAndreas Gampe2015-05-116-0/+32
| | | | | | | | Add intrinsics implementations for indexOf in the optimizing compiler. These are mostly ported from Quick. Add instruction support to assemblers where necessary. Change-Id: Ife90ed0245532a5c436a26fe84715dc357f353c8
* ART: Fix mips64 jni bugs.Douglas Leung2015-05-062-9/+16
| | | | | | | | | For mips64, 32-bits loads can be zero extended or sign extended to 64-bits. The extension type must match the data type to be loaded. Also re-enable mips64 generic jni testing. Change-Id: I9cabaf80b4fde63d9868fccd74593b36d1c324e8
* Revert "Revert "Revert "Revert "[optimizing] Improve x86 shifts""""Mark P Mendell2015-05-042-13/+69
| | | | | | | | | This reverts commit 2a7a1d7808f003bea908023ebd11eb442d2fca39. Fix the problem that a long long >> 63 got the wrong answer. The problem was that a shr was used instead of a sar. Change-Id: I0327f79c718016ddec9272a605fc50ec15ec4566
* Revert "Revert "Revert "[optimizing] Improve x86 shifts"""Roland Levillain2015-04-292-69/+13
| | | | | | | | | | | | | | | | | | | | This reverts commit 9b95a057ee20e4b1ca2e9c663726482172dc9ba3. Reverting this CL as it breaks libcore tests: org.apache.harmony.tests.java.lang.DoubleTest#test_compare junit.framework.AssertionFailedError: compare() -0.0 should be less 0.0 at junit.framework.Assert.assertTrue(Assert.java:140) at org.apache.harmony.tests.java.lang.DoubleTest.test_compare(DoubleTest.java:258) org.apache.harmony.tests.java.lang.DoubleTest#test_compare FAIL (EXEC_FAILED) org.apache.harmony.tests.java.lang.DoubleTest#test_compareToLjava_lang_Double junit.framework.AssertionFailedError: Assert 2: compare() -0.0 should be less 0.0 at junit.framework.Assert.assertTrue(Assert.java:140) at org.apache.harmony.tests.java.lang.DoubleTest.test_compareToLjava_lang_Double(DoubleTest.java:1320) org.apache.harmony.tests.java.lang.DoubleTest#test_compareToLjava_lang_Double FAIL (EXEC_FAILED) Change-Id: I10f0ec8cc9495cc225fef1940b3f1a9fe87d996f
* Revert "Revert "[optimizing] Improve x86 shifts""Roland Levillain2015-04-292-13/+69
| | | | | | | | | This reverts commit f9aac1e9f442c2486cd54f045d43e15791601205. Don't use Location::Any() for the first input if the output is Location::SameAsFirstInput(). Change-Id: I400834052b114abf0d616da1b4b6506f7bba10ab
* ART: Refactor utils/assembler testAndreas Gampe2015-04-242-469/+561
| | | | | | | | Split out the part that compares a buffer with the product of a host assembler. That will allow to reuse this for the Quick assemblers. Change-Id: Ie15777cb0a22f7532d8a8ea35403db0f229cd26f
* ART: Dead block removalDavid Brazdil2015-04-241-0/+8
| | | | | | | | | Adds a new pass which finds all unreachable blocks, typically due to simplifying an if-condition to a constant, and removes them from the graph. The patch also slightly generalizes the graph-transforming operations. Change-Id: Iff7c97f1d10b52886f3cd7401689ebe1bfdbf456
* Revert "Revert "Quick: Rewrite type inference pass.""Vladimir Marko2015-04-232-0/+456
| | | | | | | | | Fix the type of the ArtMethod* SSA register. Bug: 19419671 This reverts commit 1b717f63847de8762e7f7bdd6708fdfae9d24a67. Change-Id: Ie4da3c03a0e0334a39a24718f6dc31f9255cfb53
* Revert "Quick: Rewrite type inference pass."Andreas Gampe2015-04-222-456/+0
| | | | | | | | Breaks arm64, as the method register is not correctly flagged as ref and thus 32bit. Bug: 19419671 This reverts commit e490b01c12d33f3bd5c247b55b47e507cc9c8fab.
* Replace NULL with nullptrMathieu Chartier2015-04-2210-50/+50
| | | | | | | Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
* Merge "Quick: Rewrite type inference pass."Vladimir Marko2015-04-222-0/+456
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| * Quick: Rewrite type inference pass.Vladimir Marko2015-04-222-0/+456
| | | | | | | | | | | | | | | | | | | | | | Use method signatures, field types and types embedded in dex insns for type inference. Perform the type inference in two phases, first a simple pass that records all types implied by individual insns, and then an iterative pass to propagate those types further via phi, move, if-cc and aget/aput insns. Bug: 19419671 Change-Id: Id38579d48a44fc5eadd13780afb6d370093056f9
* | Fix X86_64 assembler REX instructionsMark Mendell2015-04-222-4/+32
| | | | | | | | | | | | | | | | | | | | | | A couple of instructions don't pass the 'Address' to EmitRex64. This will cause the incorrect register number to be assembled if the register is >= 8. This may cause bad code to be generated in some cases. Change-Id: I2907ae8b7629ee95d542e3fab429318994a78938 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Merge "[optimizing] Use more X86_64 addressing modes"Nicolas Geoffray2015-04-223-3/+246
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| * [optimizing] Use more X86_64 addressing modesMark Mendell2015-04-213-3/+246
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow constant and memory addresses to more X86_64 instructions. Add memory formats to X86_64 instructions to match. Fix a bug in cmpq(CpuRegister, const Address&). Allow mov <addr>,immediate (instruction 0xC7) to be a valid faulting instruction. Change-Id: I5b8a409444426633920cd08e09f687a7afc88a39 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Move GetAndroidToolsDir to common location.David Srbecky2015-04-211-89/+5
|/ | | | | | | Move the code which looks for the prebuilts directory to CommonRuntimeTest and add test for it. Change-Id: Id804de31c466656957fdd4b6a470f80a00477aed
* ARM64: Remove suspend register.Zheng Xu2015-04-142-68/+106
| | | | | | | | It also clean up build/remove frame used by JNI compiler and generates stp/ldp instead of str/ldr. Also x19 has been unblocked in both quick and optimizing compiler. Change-Id: Idbeac0942265f493266b2ef9b7a65bb4054f0e2d
* Merge "Exercise the x86 and x86-64 FILD and FISTP instructions."Roland Levillain2015-04-136-0/+52
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| * Exercise the x86 and x86-64 FILD and FISTP instructions.Roland Levillain2015-04-136-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Ensure the double- and quadword x87 (FPU) instructions for integer loading (resp. fildl and fildll) are properly generated by the x86 and x86-64 generators (resp. X86Assembler::filds/X86_64Assembler::filds and X86Assembler::fildl/X86_64Assembler::fildl). - Ensure the double- and quadword x87 (FPU) instructions for integer storing & popping (resp. filstpl and fistpll) are properly generated by the x86 and x86-64 generators (resp. X86Assembler::fistps/X86_64Assembler::fistps and X86Assembler::fistpl/X86_64Assembler::fistpl). These instructions can be used in the implementation of the long-to-float and long-to-double Dex type conversions. Change-Id: Iade52a9aee326d189d77d3dbd352a2b5dab52e46
| * Merge "Revert "Optimizing: Fix long-to-fp conversion on x86.""Nicolas Geoffray2015-04-134-16/+0
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| | * Revert "Optimizing: Fix long-to-fp conversion on x86."Nicolas Geoffray2015-04-134-16/+0
| | | | | | | | | | | | | | | | | | | | | | | | Test fails on arm. This reverts commit 2d45b4df3838d9c0e5a213305ccd1d7009e01437. Change-Id: Id2864917b52f7ffba459680303a2d15b34f16a4e
| * | Merge "Optimizing: Fix long-to-fp conversion on x86."Roland Levillain2015-04-134-0/+16
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| | * Optimizing: Fix long-to-fp conversion on x86.Serguei Katkov2015-04-134-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | long-to-fp conversion implemented using SSE loses the precision. The test is included. CL uses FPU to provide the correct result. Change-Id: I8eaf3c46819a8cb52642a7e7d7c4e3e0edbc88db Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
* | | ART: Clean up includes.Vladimir Marko2015-04-131-0/+1
|/ / | | | | | | | | | | | | Reduce dependencies to improve incremental build times. Break up circular dependency involving class_linker-inl.h. Change-Id: I4be742c5c2b5cd9855beea86630fd68aab76b0db
* | Merge "Revert "[optimizing] Improve x86 shifts""Nicolas Geoffray2015-04-102-69/+13
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| * | Revert "[optimizing] Improve x86 shifts"Roland Levillain2015-04-102-69/+13
| | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 222fcf96c9b73bbb739012575e7e413caf9348ec. Reverting this CL as it is breaking a few tests (see http://build.chromium.org/p/client.art/builders/host-x86/builds/3251/steps/test%20optimizing/logs/stdio). Will investigate ASAP. Change-Id: Iddd8363e83a24aa49fbdf0f0c9dc12e63b4848de
* | | Move ArtField to nativeMathieu Chartier2015-04-102-23/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add linear alloc. Moved ArtField to be native object. Changed image writer to put ArtFields after the mirror section. Savings: 2MB on low ram devices 4MB on normal devices Total PSS measurements before (normal N5, 95s after shell start): Image size: 7729152 bytes 23112 kB: .NonMoving 23212 kB: .NonMoving 22868 kB: .NonMoving 23072 kB: .NonMoving 22836 kB: .NonMoving 19618 kB: .Zygote 19850 kB: .Zygote 19623 kB: .Zygote 19924 kB: .Zygote 19612 kB: .Zygote Avg: 42745.4 kB After: Image size: 7462912 bytes 17440 kB: .NonMoving 16776 kB: .NonMoving 16804 kB: .NonMoving 17812 kB: .NonMoving 16820 kB: .NonMoving 18788 kB: .Zygote 18856 kB: .Zygote 19064 kB: .Zygote 18841 kB: .Zygote 18629 kB: .Zygote 3499 kB: .LinearAlloc 3408 kB: .LinearAlloc 3424 kB: .LinearAlloc 3600 kB: .LinearAlloc 3436 kB: .LinearAlloc Avg: 39439.4 kB No reflection performance changes. Bug: 19264997 Bug: 17643507 Change-Id: I10c73a37913332080aeb978c7c94713bdfe4fe1c
* | | Merge "[optimizing] Improve x86 shifts"Roland Levillain2015-04-102-13/+69
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| * | [optimizing] Improve x86 shiftsMark Mendell2015-04-102-13/+69
| | | | | | | | | | | | | | | | | | | | | | | | Support memory operands for integer shifts. Generate better code for long shifts by constants. Change-Id: Icc92fa1b59cc280d4894af6f054e19b01977d5ce Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | [optimizing] Address x86_64 RIP patch commentsMark Mendell2015-04-102-51/+26
|/ / | | | | | | | | | | | | | | | | Nicolas had some comments after the patch https://android-review.googlesource.com/#/c/144100 had merged. Fix the problems that he found. Change-Id: I40e8a4273997860db7511dc8f1986281b72bead2 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | Merge "[optimizing] Add RIP support for x86_64"Roland Levillain2015-04-092-2/+164
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| * | [optimizing] Add RIP support for x86_64Mark Mendell2015-04-092-2/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | Support a constant area addressed using RIP on x86_64. Use it for FP operations to avoid loading constants into a CPU register and moving to a XMM register. Change-Id: I58421759ef2a8475538876c20e696ec787015a72 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | Merge "Implement CFI for JNI."David Srbecky2015-04-0914-122/+199
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| * | | Implement CFI for JNI.David Srbecky2015-04-0814-122/+199
| | | | | | | | | | | | | | | | | | | | | | | | CFI is necessary for stack unwinding in gdb, lldb, and libunwind. Change-Id: I37eb7973f99a6975034cf0e699e138c3a9aba10f
* | | | Merge "x86_64: Fix the rex prefix for movzxb, movsxb, movb"Andreas Gampe2015-04-093-25/+102
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| * | | x86_64: Fix the rex prefix for movzxb, movsxb, movbChao-ying Fu2015-04-083-25/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch sets the rex prefix for the source byte register of movzxb, movsxb, and movb that has the destination memory operand, when the register is SPL, BPL, SIL, DIL. This patch adds tests for movzxb and movsxb via Repeatrb(), and adds the tertiary and quaternary register views for word and byte registers on x86_64. TODO: Support tests with memory operands. Change-Id: I0c5c727f3dd4a75af039b87f7e57d0741e689038 Signed-off-by: Chao-ying Fu <chao-ying.fu@intel.com>
* | | | Merge "Speedup div/rem by constants on x86 and x86_64"Calin Juravle2015-04-093-0/+13
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| * | | | Speedup div/rem by constants on x86 and x86_64Guillaume Sanchez2015-04-093-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is done using the algorithms in Hacker's Delight chapter 10. Change-Id: I7bacefe10067569769ed31a1f7834f796fb41119
* | | | | Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs."Roland Levillain2015-04-093-10/+85
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| * | | | Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs.Roland Levillain2015-04-073-10/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Augment compiler/utils/arm/assembler_thumb2_test.cc. - Ensure art::arm::Thumb2Assembler::StoreToOffset properly handles IP as (implicit) second source register. - Remove the parity constraint on the first source register for art::arm::Thumb2Assembler::ldrd and art::arm::Thumb2Assembler::strd (as they are not required by the Thumb-2 encoding). - Introduce additional versions of art::arm::Thumb2Assembler::ldrd and art::arm::Thumb2Assembler::strd accepting a second source register, which is not necessarily the one following the first source register, as it is allowed by the Thumb-2 encoding. Change-Id: I7dba168437a96a5cbb117058e9c547fb1ff5c295
* | | | | Merge "[optimizing] Implement more x86/x86_64 intrinsics"Andreas Gampe2015-04-086-0/+125
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| * | | | [optimizing] Implement more x86/x86_64 intrinsicsMark Mendell2015-04-066-0/+125
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implement CAS and bit reverse and byte reverse intrinsics that were missing from x86 and x86_64 implementations. Add assembler tests and compareAndSwapLong test. Change-Id: Iabb2ff46036645df0a91f640288ef06090a64ee3 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
* | | | Merge "Remove the old CFI infrastructure."David Srbecky2015-04-089-391/+13
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| * | | | Remove the old CFI infrastructure.David Srbecky2015-04-079-391/+13
| |/ / / | | | | | | | | | | | | Change-Id: I12a17a8a1c39ffccaa499c328ebac36e4d74dc4e
* | | | Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for words."Roland Levillain2015-04-081-0/+44
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| * | Exercise art::arm::Thumb2Assembler::StoreToOffset for words.Roland Levillain2015-04-021-0/+44
| | | | | | | | | | | | Change-Id: Ifa82e69c055eb99e526fc7ab5db54bde988d2caf
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