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authorMark Mendell <mark.p.mendell@intel.com>2015-04-22 10:46:07 -0400
committerMark Mendell <mark.p.mendell@intel.com>2015-04-22 11:16:51 -0400
commit7fd8b59ab9fcd896a95883ce7be781d74e849d60 (patch)
tree80b8d9f3b56159e75100dcf570b19246d8d548a7 /compiler/utils
parentf456ce1d602044e96deef30297b16bfb44f6663a (diff)
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Fix X86_64 assembler REX instructions
A couple of instructions don't pass the 'Address' to EmitRex64. This will cause the incorrect register number to be assembled if the register is >= 8. This may cause bad code to be generated in some cases. Change-Id: I2907ae8b7629ee95d542e3fab429318994a78938 Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'compiler/utils')
-rw-r--r--compiler/utils/x86_64/assembler_x86_64.cc8
-rw-r--r--compiler/utils/x86_64/assembler_x86_64_test.cc28
2 files changed, 32 insertions, 4 deletions
diff --git a/compiler/utils/x86_64/assembler_x86_64.cc b/compiler/utils/x86_64/assembler_x86_64.cc
index 1ff99df118..0344f52a3f 100644
--- a/compiler/utils/x86_64/assembler_x86_64.cc
+++ b/compiler/utils/x86_64/assembler_x86_64.cc
@@ -398,7 +398,7 @@ void X86_64Assembler::movsxd(CpuRegister dst, CpuRegister src) {
void X86_64Assembler::movsxd(CpuRegister dst, const Address& src) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitRex64(dst);
+ EmitRex64(dst, src);
EmitUint8(0x63);
EmitOperand(dst.LowBits(), src);
}
@@ -1342,7 +1342,7 @@ void X86_64Assembler::testq(CpuRegister reg1, CpuRegister reg2) {
void X86_64Assembler::testq(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitRex64(reg);
+ EmitRex64(reg, address);
EmitUint8(0x85);
EmitOperand(reg.LowBits(), address);
}
@@ -1558,7 +1558,7 @@ void X86_64Assembler::addq(CpuRegister reg, const Immediate& imm) {
void X86_64Assembler::addq(CpuRegister dst, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitRex64(dst);
+ EmitRex64(dst, address);
EmitUint8(0x03);
EmitOperand(dst.LowBits(), address);
}
@@ -1621,7 +1621,7 @@ void X86_64Assembler::subq(CpuRegister dst, CpuRegister src) {
void X86_64Assembler::subq(CpuRegister reg, const Address& address) {
AssemblerBuffer::EnsureCapacity ensured(&buffer_);
- EmitRex64(reg);
+ EmitRex64(reg, address);
EmitUint8(0x2B);
EmitOperand(reg.LowBits() & 7, address);
}
diff --git a/compiler/utils/x86_64/assembler_x86_64_test.cc b/compiler/utils/x86_64/assembler_x86_64_test.cc
index 454cb029b5..9e4144ac26 100644
--- a/compiler/utils/x86_64/assembler_x86_64_test.cc
+++ b/compiler/utils/x86_64/assembler_x86_64_test.cc
@@ -705,6 +705,34 @@ TEST_F(AssemblerX86_64Test, CmpqAddr) {
DriverStr(expected, "cmpq");
}
+TEST_F(AssemblerX86_64Test, MovsxdAddr) {
+ GetAssembler()->movsxd(x86_64::CpuRegister(x86_64::R12),
+ x86_64::Address(x86_64::CpuRegister(x86_64::R9), 0));
+ const char* expected = "movslq 0(%R9), %R12\n";
+ DriverStr(expected, "movsxd");
+}
+
+TEST_F(AssemblerX86_64Test, TestqAddr) {
+ GetAssembler()->testq(x86_64::CpuRegister(x86_64::R12),
+ x86_64::Address(x86_64::CpuRegister(x86_64::R9), 0));
+ const char* expected = "testq 0(%R9), %R12\n";
+ DriverStr(expected, "testq");
+}
+
+TEST_F(AssemblerX86_64Test, AddqAddr) {
+ GetAssembler()->addq(x86_64::CpuRegister(x86_64::R12),
+ x86_64::Address(x86_64::CpuRegister(x86_64::R9), 0));
+ const char* expected = "addq 0(%R9), %R12\n";
+ DriverStr(expected, "addq");
+}
+
+TEST_F(AssemblerX86_64Test, SubqAddr) {
+ GetAssembler()->subq(x86_64::CpuRegister(x86_64::R12),
+ x86_64::Address(x86_64::CpuRegister(x86_64::R9), 0));
+ const char* expected = "subq 0(%R9), %R12\n";
+ DriverStr(expected, "subq");
+}
+
TEST_F(AssemblerX86_64Test, Cvtss2sdAddr) {
GetAssembler()->cvtss2sd(x86_64::XmmRegister(x86_64::XMM0),
x86_64::Address(x86_64::CpuRegister(x86_64::RAX), 0));