summaryrefslogtreecommitdiffstats
path: root/compiler/utils/arm
Commit message (Collapse)AuthorAgeFilesLines
* Move mirror::ArtMethod to nativeMathieu Chartier2015-06-022-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Optimizing + quick tests are passing, devices boot. TODO: Test and fix bugs in mips64. Saves 16 bytes per most ArtMethod, 7.5MB reduction in system PSS. Some of the savings are from removal of virtual methods and direct methods object arrays. Bug: 19264997 (cherry picked from commit e401d146407d61eeb99f8d6176b2ac13c4df1e33) Change-Id: I622469a0cfa0e7082a2119f3d6a9491eb61e3f3d Fix some ArtMethod related bugs Added root visiting for runtime methods, not currently required since the GcRoots in these methods are null. Added missing GetInterfaceMethodIfProxy in GetMethodLine, fixes --trace run-tests 005, 044. Fixed optimizing compiler bug where we used a normal stack location instead of double on ARM64, this fixes the debuggable tests. TODO: Fix JDWP tests. Bug: 19264997 Change-Id: I7c55f69c61d1b45351fd0dc7185ffe5efad82bd3 ART: Fix casts for 64-bit pointers on 32-bit compiler. Bug: 19264997 Change-Id: Ief45cdd4bae5a43fc8bfdfa7cf744e2c57529457 Fix JDWP tests after ArtMethod change Fixes Throwable::GetStackDepth for exception event detection after internal stack trace representation change. Adds missing ArtMethod::GetInterfaceMethodIfProxy call in case of proxy method. Bug: 19264997 Change-Id: I363e293796848c3ec491c963813f62d868da44d2 Fix accidental IMT and root marking regression Was always using the conflict trampoline. Also included fix for regression in GC time caused by extra roots. Most of the regression was IMT. Fixed bug in DumpGcPerformanceInfo where we would get SIGABRT due to detached thread. EvaluateAndApplyChanges: From ~2500 -> ~1980 GC time: 8.2s -> 7.2s due to 1s less of MarkConcurrentRoots Bug: 19264997 Change-Id: I4333e80a8268c2ed1284f87f25b9f113d4f2c7e0 Fix bogus image test assert Previously we were comparing the size of the non moving space to size of the image file. Now we properly compare the size of the image space against the size of the image file. Bug: 19264997 Change-Id: I7359f1f73ae3df60c5147245935a24431c04808a [MIPS64] Fix art_quick_invoke_stub argument offsets. ArtMethod reference's size got bigger, so we need to move other args and leave enough space for ArtMethod* and 'this' pointer. This fixes mips64 boot. Bug: 19264997 Change-Id: I47198d5f39a4caab30b3b77479d5eedaad5006ab
* ART: Clean up arm64 kNumberOfXRegisters usage.Vladimir Marko2015-05-266-6/+4
| | | | | | | | | | | | | | | | | | | | | Avoid undefined behavior for arm64 stemming from 1u << 32 in loops with upper bound kNumberOfXRegisters. Create iterators for enumerating bits in an integer either from high to low or from low to high and use them for <arch>Context::FillCalleeSaves() on all architectures. Refactor runtime/utils.{h,cc} by moving all bit-fiddling functions to runtime/base/bit_utils.{h,cc} (together with the new bit iterators) and all time-related functions to runtime/base/time_utils.{h,cc}. Improve test coverage and fix some corner cases for the bit-fiddling functions. Bug: 13925192 (cherry picked from commit 80afd02024d20e60b197d3adfbb43cc303cf29e0) Change-Id: I905257a21de90b5860ebe1e39563758f721eab82
* Replace NULL with nullptrMathieu Chartier2015-04-221-7/+7
| | | | | | | Also fixed some lines that were too long, and a few other minor details. Change-Id: I6efba5fb6e03eb5d0a300fddb2a75bf8e2f175cb
* Merge "Implement CFI for JNI."David Srbecky2015-04-092-39/+46
|\
| * Implement CFI for JNI.David Srbecky2015-04-082-39/+46
| | | | | | | | | | | | CFI is necessary for stack unwinding in gdb, lldb, and libunwind. Change-Id: I37eb7973f99a6975034cf0e699e138c3a9aba10f
* | Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs."Roland Levillain2015-04-093-10/+85
|\ \ | |/ |/|
| * Exercise art::arm::Thumb2Assembler::StoreToOffset for word pairs.Roland Levillain2015-04-073-10/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Augment compiler/utils/arm/assembler_thumb2_test.cc. - Ensure art::arm::Thumb2Assembler::StoreToOffset properly handles IP as (implicit) second source register. - Remove the parity constraint on the first source register for art::arm::Thumb2Assembler::ldrd and art::arm::Thumb2Assembler::strd (as they are not required by the Thumb-2 encoding). - Introduce additional versions of art::arm::Thumb2Assembler::ldrd and art::arm::Thumb2Assembler::strd accepting a second source register, which is not necessarily the one following the first source register, as it is allowed by the Thumb-2 encoding. Change-Id: I7dba168437a96a5cbb117058e9c547fb1ff5c295
* | Merge "Exercise art::arm::Thumb2Assembler::StoreToOffset for words."Roland Levillain2015-04-081-0/+44
|\|
| * Exercise art::arm::Thumb2Assembler::StoreToOffset for words.Roland Levillain2015-04-021-0/+44
| | | | | | | | Change-Id: Ifa82e69c055eb99e526fc7ab5db54bde988d2caf
* | ART: Enable more Clang warningsAndreas Gampe2015-04-062-6/+1
| | | | | | | | Change-Id: Ie6aba02f4223b1de02530e1515c63505f37e184c
* | ART: Add Clang's -Wused-but-marked-unusedAndreas Gampe2015-04-031-1/+1
|/ | | | | | Add detection of wrong unused annotations. Fix our codebase. Change-Id: I85cc20f2eac71c1ec6c5c7cd6efb08454a629634
* Forbid the use of shifts in ShifterOperand in Thumb2Guillaume "Vermeille" Sanchez2015-03-252-0/+6
| | | | Change-Id: I4b3b4d90f11f2dd0c9a274b724051fa98982fb19
* Make subs and adds alter flags when rn is an immediateGuillaume "Vermeille" Sanchez2015-03-252-19/+42
| | | | Change-Id: I70e0d78f155bf806222ad12a324dbd8c8fe575a1
* Revert "Forbid the use of shifts in ShifterOperand in Thumb2"Calin Juravle2015-03-172-6/+0
| | | | | | This reverts commit bada8b0f0a10bd32d6cb87ed4e57f2aa3d7c03c2. Change-Id: Ic89c76367c8ab91cfb5d1510789ac2e352922da8
* Forbid the use of shifts in ShifterOperand in Thumb2Guillaume "Vermeille" Sanchez2015-03-112-0/+6
| | | | Change-Id: Ib141f53e52cce3032a42fbc991303e227c98820b
* Stack support for Optimizing compilerSebastien Hertz2015-03-031-6/+34
| | | | | | | | | | | Allows to read/write DEX registers from physical register or stack location when the method is compiled with the Optimizing compiler. Required fixing arm and arm64 JNI compiler by saving floating point registers. Bug: 18547544 Change-Id: I401579f251d1c0a130f6cf4a93a960cdcd7518f5
* ART: Templatize IsInt & IsUintAndreas Gampe2015-02-183-18/+19
| | | | | | Ensure that things are used correctly. Change-Id: I76f082b32dcee28bbfb4c519daa401ac595873b3
* Optimize double/float immediate loading on arm.Nicolas Geoffray2015-02-131-6/+32
| | | | | | Also reserve a D register for temp. Change-Id: I6584d9005b0f5685c3afcd8e9153b4c87b56aa8e
* Merge "Improve ParallelMoveResolver to work with pairs."Nicolas Geoffray2015-02-101-0/+10
|\
| * Improve ParallelMoveResolver to work with pairs.Nicolas Geoffray2015-02-101-0/+10
| | | | | | | | Change-Id: Ie2a540ffdb78f7f15d69c16a08ca2d3e794f65b9
* | ART: Arm intrinsics for Optimizing compilerAndreas Gampe2015-02-092-0/+13
|/ | | | | | Add arm32 intrinsics to the optimizing compiler. Change-Id: If4aeedbf560862074d8ee08ca4484b666d6b9bf0
* Fix build by putting ATTRIBUTE_UNUSUED.Nicolas Geoffray2015-02-031-2/+2
| | | | Change-Id: If894fa1343a7c8a6456d707e815d803404a171d7
* Fix thumb2 assembler's ShifterOperandCanHold.Nicolas Geoffray2015-02-031-7/+0
| | | | Change-Id: Ica3c5f39d52722950725ba622fc67bd7f634918a
* ART: Fix assembler_thumb_testAndreas Gampe2015-02-021-0/+2
| | | | | | | | | Fix the inconsistent calls. This was bad practice, requiring that shape meant arm32 and thumb were not interchangeable. Also fix an error in the assembler itself for tst and teq. Change-Id: I50242801002aa81cc17bfaa53eb8b7c1d9488fbc
* ART: Fix thumb2 utils assemblerAndreas Gampe2015-02-022-23/+76
| | | | | | | | | It didn't correctly put down the 16b variants, as it was not checking the ShifterOperand correctly. Add one simple test. TODO: exhaustive testing. Change-Id: Ied08da115f8417a3ca92bd9967c6dcdc102e7510
* Implement double and float support for arm in register allocator.Nicolas Geoffray2015-01-081-0/+7
| | | | | | | | | | | | The basic approach is: - An instruction that needs two registers gets two intervals. - When allocating the low part, we also allocate the high part. - When splitting a low (or high) interval, we also split the high (or low) equivalent. - Allocation follows the (S/D register) requirement that low registers are always even and the high equivalent is low + 1. Change-Id: I06a5148e05a2ffc7e7555d08e871ed007b4c2797
* [optimizing compiler] Add support for volatileCalin Juravle2014-12-197-3/+136
| | | | | | | | | | | | - for backends: arm, x86, x86_64 - added necessary instructions to assemblies - clean up code gen for field set/get - fixed InstructionDataEquals for some instructions - fixed comments in compiler_enums * 003-opcode test verifies basic volatile functionality Change-Id: I144393efa312dfb2c332cb84056b00edffee338a
* Fix Thumb2 Emit16BitAddSub() to keep full immediate.Vladimir Marko2014-12-181-7/+7
| | | | Change-Id: I2d4b44752150669119ead16e99f7d7a945d2e88f
* Fix Thumb2 assembler to emit 16-bit add/sub SP, #imm.Vladimir Marko2014-12-181-34/+23
| | | | | | Also allow 16-bit add rN, SP, #imm. Change-Id: I50100ad0b0e19a1c855a2319615e86d7a2b66a69
* Don't use CanHoldArm in the code generator.Nicolas Geoffray2014-11-286-77/+113
| | | | | | | | CanHoldArm was ARM32 specific. Instead use a virtual Assembler::ShifterOperandCanHold that both thumb2 and arm32 implement. Change-Id: I33794a93caf02ee5d78d32a8471d9fd6fe4f0a00
* Merge "[optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}"Calin Juravle2014-11-273-3/+25
|\
| * [optimizing compiler] Add CMP{L,G}_{FLOAT,DOUBLE}Calin Juravle2014-11-273-3/+25
| | | | | | | | | | | | | | | | | | | | Adds: - float comparison for arm, x86, x86_64 backends. - ucomis{s,d} assembly to x86 and x86_64. - vmstat assebmly for thumb2 - new assembly tests Change-Id: Ie3e19d0c08b3b875cd0a4be4ee4e9c8a4a076290
* | Optimizing: Use 16-bit Thumb2 PUSH/POP when possible.Vladimir Marko2014-11-261-19/+29
|/ | | | | | | JNI compiler uses the same assembler but always pushes and pops registers that require the 32-bit PUSH/POP. Change-Id: I7e857ae799316586cd09d6547cf971ef439af147
* Merge "ART: Fix unused variables and functions"Andreas Gampe2014-11-241-2/+1
|\
| * ART: Fix unused variables and functionsAndreas Gampe2014-11-241-2/+1
| | | | | | | | Change-Id: Icbab884d2dfd71656347368b424cb35cbf524051
* | Merge "[optimizing compiler] Add shifts"Calin Juravle2014-11-242-8/+8
|\ \ | |/ |/|
| * [optimizing compiler] Add shiftsCalin Juravle2014-11-242-8/+8
| | | | | | | | | | | | Added SHL, SHR, USHR for arm, x86, x86_64. Change-Id: I971f594e270179457e6958acf1401ff7630df07e
* | Merge "test: Fix assember_arm_test to compile on gcc"Igor Murashkin2014-11-221-1/+1
|\ \
| * | test: Fix assember_arm_test to compile on gccIgor Murashkin2014-11-211-1/+1
| | | | | | | | | | | | | | | Bug: 18484809 Change-Id: I2677de5fdb418091bc753271ad38972f375c96d8
* | | ART: Fix uninitialized value in arm32 assembler testAndreas Gampe2014-11-201-0/+1
| | | | | | | | | | | | | | | | | | | | | The first_ field was meant to be initialized for each generation invocation. Change-Id: If4d36d84afe24d8ddc6bb9d25b85c764285e166a
* | | ART: Fix arm32 assembler test.Andreas Gampe2014-11-201-1/+1
|/ / | | | | | | | | | | | | | | Drop the requested architecture from armv7ve to armv7-a, but tune for cortex-a15. That allows sdiv and udiv, but has the advantage that it works on gcc 4.8. Change-Id: I92cca55ce01334119d8a402103ec295c66d34ca6
* | Merge "ART: Assembler_arm_test"Andreas Gampe2014-11-203-87/+1180
|\ \ | |/ |/|
| * ART: Assembler_arm_testAndreas Gampe2014-11-203-87/+1180
| | | | | | | | | | | | | | Add some generic test infrastructure, and update the arm32 test. Supports many of the GPR instructions. Change-Id: I8a270ec377f3266d6ab486e636abb50c56b87823
* | Fix the last users of TARGET_CPU_SMP.Elliott Hughes2014-11-192-4/+0
|/ | | | | | Everyone else assumes SMP. Change-Id: I7ff7faef46fbec6c67d6e446812d599e473cba39
* Add support for int-to-char in the optimizing compiler.Roland Levillain2014-11-147-0/+119
| | | | | | | | | | | | | - Add support for the int-to-char Dex instruction in the optimizing compiler. - Implement the ARM and Thumb-2 UBFX instructions and add tests for them. - Generate x86, x86-64 and ARM (but not ARM64) code for byte to char, short to char, int to char (and char to char!) HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: I5cd4c6d86f0f6a966c059715b98db35cc8f9de76
* ART: Multiview assembler_test, fix x86-64 assemblerAndreas Gampe2014-11-132-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Expose "secondary" names for registers so it is possible to test 32b views for 64b architectures. Add floating-point register testing. Refactor assembler_test for better code reuse (and simpler adding of combination drivers). Fix movss, movsd (MR instead of RM encoding), xchgl, xchgq, both versions of EmitGenericShift. Tighten imull(Reg,Imm), imulq(Reg,Imm), xchgl and xchgq encoding. Clarify cv*** variants with a comment. Add tests for movl, addl, imull, imuli, mull, subl, cmpqi, cmpl, xorq (regs), xorl, movss, movsd, addss, addsd, subss, subsd, mulss, mulsd, divss, divsd, cvtsi2ss, cvtsi2sd, cvtss2si, cvtss2sd, cvtsd2si, cvttss2si, cvttsd2si, cvtsd2ss, cvtdq2pd, comiss, comisd, sqrtss, sqrtsd, xorps, xorpd, fincstp, fsin, fcos, fptan, xchgl (disabled, see code comment), xchgq, testl, andl, andq, orl, orq, shll, shrl, sarl, negq, negl, notq, notl, enter and leave, call, ret, and jmp, and make some older ones more exhaustive. Follow-up TODOs: 1) Support memory (Address). 2) Support tertiary and quaternary register views. Bug: 18117217 Change-Id: I1d583a3bec552e3cc7c315925e1e006f393ab687
* Exercise the generation of SBFX on ARM32 & Thumb-2.Roland Levillain2014-11-132-0/+242
| | | | | | | | | | Exercise the generation of the ARM SBFX intruction in compiler/utils/arm/assembler_arm32_test.cc (ARM instruction set encoding) and in compiler/utils/arm/assembler_thumb2_test.cc (Thumb instruction set encoding). Change-Id: Ic72683aac6dd6628e227523e352c395e1a63b52e
* Add support for int-to-byte in the optimizing compiler.Roland Levillain2014-11-135-0/+47
| | | | | | | | | | | | - Add support for the int-to-byte Dex instruction in the optimizing compiler. - Implement the ARM and Thumb-2 SBFX instructions. - Generate x86, x86-64 and ARM (but not ARM64) code for char to byte, short to byte and int to byte HTypeConversion nodes. - Add related tests to test/422-type-conversion. Change-Id: Ic8b8911b90d4b5281fad15bcee96bc3ee85dc577
* Merge "Fix store instructions to large frames in ARM opt. compiler."Roland Levillain2014-11-051-6/+24
|\
| * Fix store instructions to large frames in ARM opt. compiler.Roland Levillain2014-11-041-6/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | When accessing a stack frame at a large offset, use an additional core register (R5 or R6) as a temporary register whenever IP contains the value to store (and thus cannot be used by art::Thumb2Assembler::StoreToOffset as a temporary register to compute the memory address where the value is to be stored). The previous value of R5 (or R6) is saved on the stack before the emission of the store instruction and restored afterwards. Change-Id: Ic5fd5ab2c09d8327dd1f0f241d40d2c397ce64cd
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-18 01:03:50 +0000