diff options
Diffstat (limited to 'compiler/dex/quick')
44 files changed, 178 insertions, 80 deletions
diff --git a/compiler/dex/quick/arm/arm_lir.h b/compiler/dex/quick/arm/arm_lir.h index 5d09ae1cf3..971745930e 100644 --- a/compiler/dex/quick/arm/arm_lir.h +++ b/compiler/dex/quick/arm/arm_lir.h @@ -17,7 +17,9 @@ #ifndef ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_ #define ART_COMPILER_DEX_QUICK_ARM_ARM_LIR_H_ -#include "dex/compiler_internals.h" +#include "dex/compiler_enums.h" +#include "dex/reg_location.h" +#include "dex/reg_storage.h" namespace art { diff --git a/compiler/dex/quick/arm/assemble_arm.cc b/compiler/dex/quick/arm/assemble_arm.cc index 65fb3cd393..05e2abec8e 100644 --- a/compiler/dex/quick/arm/assemble_arm.cc +++ b/compiler/dex/quick/arm/assemble_arm.cc @@ -14,9 +14,12 @@ * limitations under the License. */ -#include "arm_lir.h" #include "codegen_arm.h" -#include "dex/quick/mir_to_lir-inl.h" + +#include "arm_lir.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/quick/mir_to_lir.h" namespace art { diff --git a/compiler/dex/quick/arm/call_arm.cc b/compiler/dex/quick/arm/call_arm.cc index 0713b7a18e..f15b727857 100644 --- a/compiler/dex/quick/arm/call_arm.cc +++ b/compiler/dex/quick/arm/call_arm.cc @@ -16,9 +16,13 @@ /* This file contains codegen for the Thumb2 ISA. */ -#include "arm_lir.h" #include "codegen_arm.h" + +#include "arm_lir.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" +#include "driver/compiler_driver.h" #include "gc/accounting/card_table.h" #include "mirror/art_method.h" #include "mirror/object_array-inl.h" diff --git a/compiler/dex/quick/arm/codegen_arm.h b/compiler/dex/quick/arm/codegen_arm.h index 6ac1849180..025e69f0ba 100644 --- a/compiler/dex/quick/arm/codegen_arm.h +++ b/compiler/dex/quick/arm/codegen_arm.h @@ -18,12 +18,14 @@ #define ART_COMPILER_DEX_QUICK_ARM_CODEGEN_ARM_H_ #include "arm_lir.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" #include "dex/quick/mir_to_lir.h" #include "utils/arena_containers.h" namespace art { +struct CompilationUnit; + class ArmMir2Lir FINAL : public Mir2Lir { protected: // Inherited class for ARM backend. diff --git a/compiler/dex/quick/arm/fp_arm.cc b/compiler/dex/quick/arm/fp_arm.cc index 2b2592d5db..eb1383fcff 100644 --- a/compiler/dex/quick/arm/fp_arm.cc +++ b/compiler/dex/quick/arm/fp_arm.cc @@ -14,8 +14,11 @@ * limitations under the License. */ -#include "arm_lir.h" #include "codegen_arm.h" + +#include "arm_lir.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" namespace art { diff --git a/compiler/dex/quick/arm/int_arm.cc b/compiler/dex/quick/arm/int_arm.cc index 7970bd823d..3159886826 100644 --- a/compiler/dex/quick/arm/int_arm.cc +++ b/compiler/dex/quick/arm/int_arm.cc @@ -16,11 +16,16 @@ /* This file contains codegen for the Thumb2 ISA. */ +#include "codegen_arm.h" + #include "arch/instruction_set_features.h" #include "arm_lir.h" -#include "codegen_arm.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" +#include "driver/compiler_driver.h" #include "entrypoints/quick/quick_entrypoints.h" #include "mirror/array-inl.h" #include "utils.h" @@ -1140,7 +1145,7 @@ LIR* ArmMir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* targe } bool ArmMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { - if (!cu_->GetInstructionSetFeatures()->IsSmp()) { + if (!cu_->compiler_driver->GetInstructionSetFeatures()->IsSmp()) { return false; } // Start off with using the last LIR as the barrier. If it is not enough, then we will generate one. diff --git a/compiler/dex/quick/arm/target_arm.cc b/compiler/dex/quick/arm/target_arm.cc index 52a516cc5a..5538d798b2 100644 --- a/compiler/dex/quick/arm/target_arm.cc +++ b/compiler/dex/quick/arm/target_arm.cc @@ -21,7 +21,8 @@ #include <string> #include "backend_arm.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" namespace art { diff --git a/compiler/dex/quick/arm/utility_arm.cc b/compiler/dex/quick/arm/utility_arm.cc index 73b68a5961..e4bd2a33ae 100644 --- a/compiler/dex/quick/arm/utility_arm.cc +++ b/compiler/dex/quick/arm/utility_arm.cc @@ -18,8 +18,10 @@ #include "arch/arm/instruction_set_features_arm.h" #include "arm_lir.h" +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" +#include "driver/compiler_driver.h" namespace art { diff --git a/compiler/dex/quick/arm64/arm64_lir.h b/compiler/dex/quick/arm64/arm64_lir.h index 943c5c18d4..d15412a1bd 100644 --- a/compiler/dex/quick/arm64/arm64_lir.h +++ b/compiler/dex/quick/arm64/arm64_lir.h @@ -17,7 +17,9 @@ #ifndef ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ #define ART_COMPILER_DEX_QUICK_ARM64_ARM64_LIR_H_ -#include "dex/compiler_internals.h" +#include "dex/compiler_enums.h" +#include "dex/reg_location.h" +#include "dex/reg_storage.h" namespace art { diff --git a/compiler/dex/quick/arm64/assemble_arm64.cc b/compiler/dex/quick/arm64/assemble_arm64.cc index d45ec497f0..54956d9b16 100644 --- a/compiler/dex/quick/arm64/assemble_arm64.cc +++ b/compiler/dex/quick/arm64/assemble_arm64.cc @@ -18,7 +18,10 @@ #include "arch/arm64/instruction_set_features_arm64.h" #include "arm64_lir.h" -#include "dex/quick/mir_to_lir-inl.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/quick/mir_to_lir.h" +#include "driver/compiler_driver.h" namespace art { @@ -1016,7 +1019,7 @@ void Arm64Mir2Lir::AssembleLIR() { // Avoid emitting code that could trigger Cortex A53's erratum 835769. // This fixup should be carried out for all multiply-accumulate instructions: madd, msub, // smaddl, smsubl, umaddl and umsubl. - if (cu_->GetInstructionSetFeatures()->AsArm64InstructionSetFeatures() + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsArm64InstructionSetFeatures() ->NeedFixCortexA53_835769()) { // Check that this is a 64-bit multiply-accumulate. if (IS_WIDE(lir->opcode)) { diff --git a/compiler/dex/quick/arm64/call_arm64.cc b/compiler/dex/quick/arm64/call_arm64.cc index 089e4b6709..6492442b94 100644 --- a/compiler/dex/quick/arm64/call_arm64.cc +++ b/compiler/dex/quick/arm64/call_arm64.cc @@ -16,9 +16,13 @@ /* This file contains codegen for the Thumb2 ISA. */ -#include "arm64_lir.h" #include "codegen_arm64.h" + +#include "arm64_lir.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" +#include "driver/compiler_driver.h" #include "gc/accounting/card_table.h" #include "entrypoints/quick/quick_entrypoints.h" #include "mirror/art_method.h" diff --git a/compiler/dex/quick/arm64/codegen_arm64.h b/compiler/dex/quick/arm64/codegen_arm64.h index c68b1d0a37..49ca625096 100644 --- a/compiler/dex/quick/arm64/codegen_arm64.h +++ b/compiler/dex/quick/arm64/codegen_arm64.h @@ -18,7 +18,7 @@ #define ART_COMPILER_DEX_QUICK_ARM64_CODEGEN_ARM64_H_ #include "arm64_lir.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" #include "dex/quick/mir_to_lir.h" #include <map> diff --git a/compiler/dex/quick/arm64/fp_arm64.cc b/compiler/dex/quick/arm64/fp_arm64.cc index ff692b77ac..a8ec6c0a07 100644 --- a/compiler/dex/quick/arm64/fp_arm64.cc +++ b/compiler/dex/quick/arm64/fp_arm64.cc @@ -14,8 +14,11 @@ * limitations under the License. */ -#include "arm64_lir.h" #include "codegen_arm64.h" + +#include "arm64_lir.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" #include "utils.h" diff --git a/compiler/dex/quick/arm64/int_arm64.cc b/compiler/dex/quick/arm64/int_arm64.cc index 88ab6f82d4..92675f361a 100644 --- a/compiler/dex/quick/arm64/int_arm64.cc +++ b/compiler/dex/quick/arm64/int_arm64.cc @@ -16,11 +16,16 @@ /* This file contains codegen for the Thumb2 ISA. */ +#include "codegen_arm64.h" + #include "arch/instruction_set_features.h" #include "arm64_lir.h" -#include "codegen_arm64.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" +#include "driver/compiler_driver.h" #include "entrypoints/quick/quick_entrypoints.h" #include "mirror/array-inl.h" #include "utils.h" @@ -1003,7 +1008,7 @@ LIR* Arm64Mir2Lir::OpDecAndBranch(ConditionCode c_code, RegStorage reg, LIR* tar } bool Arm64Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { - if (!cu_->GetInstructionSetFeatures()->IsSmp()) { + if (!cu_->compiler_driver->GetInstructionSetFeatures()->IsSmp()) { return false; } // Start off with using the last LIR as the barrier. If it is not enough, then we will generate one. diff --git a/compiler/dex/quick/arm64/target_arm64.cc b/compiler/dex/quick/arm64/target_arm64.cc index ee7e818f85..34662f27f2 100644 --- a/compiler/dex/quick/arm64/target_arm64.cc +++ b/compiler/dex/quick/arm64/target_arm64.cc @@ -21,7 +21,8 @@ #include <string> #include "backend_arm64.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" diff --git a/compiler/dex/quick/arm64/utility_arm64.cc b/compiler/dex/quick/arm64/utility_arm64.cc index a331f41aff..f48290d6f7 100644 --- a/compiler/dex/quick/arm64/utility_arm64.cc +++ b/compiler/dex/quick/arm64/utility_arm64.cc @@ -14,8 +14,10 @@ * limitations under the License. */ -#include "arm64_lir.h" #include "codegen_arm64.h" + +#include "arm64_lir.h" +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" diff --git a/compiler/dex/quick/codegen_util.cc b/compiler/dex/quick/codegen_util.cc index ae9b0f4baf..52b2e15342 100644 --- a/compiler/dex/quick/codegen_util.cc +++ b/compiler/dex/quick/codegen_util.cc @@ -14,13 +14,16 @@ * limitations under the License. */ -#include "dex/compiler_internals.h" +#include "mir_to_lir-inl.h" + +#include "dex/mir_graph.h" +#include "driver/compiler_driver.h" #include "driver/compiler_options.h" +#include "driver/dex_compilation_unit.h" #include "dex_file-inl.h" #include "gc_map.h" #include "gc_map_builder.h" #include "mapping_table.h" -#include "mir_to_lir-inl.h" #include "dex/quick/dex_file_method_inliner.h" #include "dex/quick/dex_file_to_method_inliner_map.h" #include "dex/verification_results.h" diff --git a/compiler/dex/quick/dex_file_method_inliner.cc b/compiler/dex/quick/dex_file_method_inliner.cc index 84c0d93008..7245853125 100644 --- a/compiler/dex/quick/dex_file_method_inliner.cc +++ b/compiler/dex/quick/dex_file_method_inliner.cc @@ -18,18 +18,15 @@ #include <algorithm> +#include "base/logging.h" #include "base/macros.h" -#include "base/mutex.h" #include "base/mutex-inl.h" -#include "dex/frontend.h" -#include "thread.h" +#include "dex/compiler_ir.h" #include "thread-inl.h" #include "dex/mir_graph.h" #include "dex/quick/mir_to_lir.h" -#include "dex_instruction.h" #include "dex_instruction-inl.h" #include "driver/dex_compilation_unit.h" -#include "verifier/method_verifier.h" #include "verifier/method_verifier-inl.h" namespace art { diff --git a/compiler/dex/quick/gen_common.cc b/compiler/dex/quick/gen_common.cc index aa47cee36b..9f53b89186 100644 --- a/compiler/dex/quick/gen_common.cc +++ b/compiler/dex/quick/gen_common.cc @@ -14,13 +14,16 @@ * limitations under the License. */ +#include "mir_to_lir-inl.h" + #include <functional> #include "arch/arm/instruction_set_features_arm.h" +#include "base/macros.h" #include "dex/compiler_ir.h" -#include "dex/compiler_internals.h" +#include "dex/mir_graph.h" #include "dex/quick/arm/arm_lir.h" -#include "dex/quick/mir_to_lir-inl.h" +#include "driver/compiler_driver.h" #include "entrypoints/quick/quick_entrypoints.h" #include "mirror/array.h" #include "mirror/object_array-inl.h" @@ -41,6 +44,18 @@ typedef mirror::ObjectArray<mirror::Class> ClassArray; * and "op" calls may be used here. */ +ALWAYS_INLINE static inline bool ForceSlowFieldPath(CompilationUnit* cu) { + return (cu->enable_debug & (1 << kDebugSlowFieldPath)) != 0; +} + +ALWAYS_INLINE static inline bool ForceSlowStringPath(CompilationUnit* cu) { + return (cu->enable_debug & (1 << kDebugSlowStringPath)) != 0; +} + +ALWAYS_INLINE static inline bool ForceSlowTypePath(CompilationUnit* cu) { + return (cu->enable_debug & (1 << kDebugSlowTypePath)) != 0; +} + /* * Generate a kPseudoBarrier marker to indicate the boundary of special * blocks. @@ -594,7 +609,7 @@ void Mir2Lir::GenSput(MIR* mir, RegLocation rl_src, OpSize size) { const MirSFieldLoweringInfo& field_info = mir_graph_->GetSFieldLoweringInfo(mir); DCHECK_EQ(SPutMemAccessType(mir->dalvikInsn.opcode), field_info.MemAccessType()); cu_->compiler_driver->ProcessedStaticField(field_info.FastPut(), field_info.IsReferrersClass()); - if (!SLOW_FIELD_PATH && field_info.FastPut()) { + if (!ForceSlowFieldPath(cu_) && field_info.FastPut()) { DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); RegStorage r_base; if (field_info.IsReferrersClass()) { @@ -714,7 +729,7 @@ void Mir2Lir::GenSget(MIR* mir, RegLocation rl_dest, OpSize size, Primitive::Typ DCHECK_EQ(SGetMemAccessType(mir->dalvikInsn.opcode), field_info.MemAccessType()); cu_->compiler_driver->ProcessedStaticField(field_info.FastGet(), field_info.IsReferrersClass()); - if (!SLOW_FIELD_PATH && field_info.FastGet()) { + if (!ForceSlowFieldPath(cu_) && field_info.FastGet()) { DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); RegStorage r_base; if (field_info.IsReferrersClass()) { @@ -852,7 +867,7 @@ void Mir2Lir::GenIGet(MIR* mir, int opt_flags, OpSize size, Primitive::Type type const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); DCHECK_EQ(IGetMemAccessType(mir->dalvikInsn.opcode), field_info.MemAccessType()); cu_->compiler_driver->ProcessedInstanceField(field_info.FastGet()); - if (!SLOW_FIELD_PATH && field_info.FastGet()) { + if (!ForceSlowFieldPath(cu_) && field_info.FastGet()) { RegisterClass reg_class = RegClassForFieldLoadStore(size, field_info.IsVolatile()); // A load of the class will lead to an iget with offset 0. DCHECK_GE(field_info.FieldOffset().Int32Value(), 0); @@ -926,7 +941,7 @@ void Mir2Lir::GenIPut(MIR* mir, int opt_flags, OpSize size, const MirIFieldLoweringInfo& field_info = mir_graph_->GetIFieldLoweringInfo(mir); DCHECK_EQ(IPutMemAccessType(mir->dalvikInsn.opcode), field_info.MemAccessType()); cu_->compiler_driver->ProcessedInstanceField(field_info.FastPut()); - if (!SLOW_FIELD_PATH && field_info.FastPut()) { + if (!ForceSlowFieldPath(cu_) && field_info.FastPut()) { RegisterClass reg_class = RegClassForFieldLoadStore(size, field_info.IsVolatile()); // Dex code never writes to the class field. DCHECK_GE(static_cast<uint32_t>(field_info.FieldOffset().Int32Value()), @@ -1016,7 +1031,7 @@ void Mir2Lir::GenConstClass(uint32_t type_idx, RegLocation rl_dest) { int32_t offset_of_type = ClassArray::OffsetOfElement(type_idx).Int32Value(); LoadRefDisp(res_reg, offset_of_type, rl_result.reg, kNotVolatile); if (!cu_->compiler_driver->CanAssumeTypeIsPresentInDexCache(*cu_->dex_file, - type_idx) || SLOW_TYPE_PATH) { + type_idx) || ForceSlowTypePath(cu_)) { // Slow path, at runtime test if type is null and if so initialize FlushAllRegs(); LIR* branch = OpCmpImmBranch(kCondEq, rl_result.reg, 0, NULL); @@ -1061,7 +1076,7 @@ void Mir2Lir::GenConstString(uint32_t string_idx, RegLocation rl_dest) { int32_t offset_of_string = mirror::ObjectArray<mirror::String>::OffsetOfElement(string_idx). Int32Value(); if (!cu_->compiler_driver->CanAssumeStringIsPresentInDexCache( - *cu_->dex_file, string_idx) || SLOW_STRING_PATH) { + *cu_->dex_file, string_idx) || ForceSlowStringPath(cu_)) { // slow path, resolve string if not in dex cache FlushAllRegs(); LockCallTemps(); // Using explicit registers @@ -1679,7 +1694,7 @@ void Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, rl_result = GenDivRem(rl_dest, rl_src1.reg, rl_src2.reg, op == kOpDiv); done = true; } else if (cu_->instruction_set == kThumb2) { - if (cu_->GetInstructionSetFeatures()->AsArmInstructionSetFeatures()-> + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsArmInstructionSetFeatures()-> HasDivideInstruction()) { // Use ARM SDIV instruction for division. For remainder we also need to // calculate using a MUL and subtract. @@ -1973,7 +1988,7 @@ void Mir2Lir::GenArithOpIntLit(Instruction::Code opcode, RegLocation rl_dest, Re rl_result = GenDivRemLit(rl_dest, rl_src, lit, is_div); done = true; } else if (cu_->instruction_set == kThumb2) { - if (cu_->GetInstructionSetFeatures()->AsArmInstructionSetFeatures()-> + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsArmInstructionSetFeatures()-> HasDivideInstruction()) { // Use ARM SDIV instruction for division. For remainder we also need to // calculate using a MUL and subtract. diff --git a/compiler/dex/quick/gen_invoke.cc b/compiler/dex/quick/gen_invoke.cc index d5889f5b48..bb5b0cdd22 100755 --- a/compiler/dex/quick/gen_invoke.cc +++ b/compiler/dex/quick/gen_invoke.cc @@ -14,12 +14,16 @@ * limitations under the License. */ +#include "mir_to_lir-inl.h" + #include "arm/codegen_arm.h" #include "dex/compiler_ir.h" -#include "dex/frontend.h" +#include "dex/dex_flags.h" +#include "dex/mir_graph.h" #include "dex/quick/dex_file_method_inliner.h" #include "dex/quick/dex_file_to_method_inliner_map.h" #include "dex_file-inl.h" +#include "driver/compiler_driver.h" #include "entrypoints/quick/quick_entrypoints.h" #include "invoke_type.h" #include "mirror/array.h" @@ -27,7 +31,6 @@ #include "mirror/dex_cache.h" #include "mirror/object_array-inl.h" #include "mirror/string.h" -#include "mir_to_lir-inl.h" #include "scoped_thread_state_change.h" namespace art { diff --git a/compiler/dex/quick/gen_loadstore.cc b/compiler/dex/quick/gen_loadstore.cc index d3146018d6..9f36e35f5e 100644 --- a/compiler/dex/quick/gen_loadstore.cc +++ b/compiler/dex/quick/gen_loadstore.cc @@ -14,9 +14,10 @@ * limitations under the License. */ +#include "mir_to_lir-inl.h" + #include "dex/compiler_ir.h" -#include "dex/compiler_internals.h" -#include "dex/quick/mir_to_lir-inl.h" +#include "dex/mir_graph.h" #include "invoke_type.h" namespace art { diff --git a/compiler/dex/quick/local_optimizations.cc b/compiler/dex/quick/local_optimizations.cc index e0f4691063..e5738998a0 100644 --- a/compiler/dex/quick/local_optimizations.cc +++ b/compiler/dex/quick/local_optimizations.cc @@ -14,9 +14,10 @@ * limitations under the License. */ -#include "dex/compiler_internals.h" #include "dex/quick/mir_to_lir-inl.h" +#include "base/logging.h" + namespace art { #define DEBUG_OPT(X) diff --git a/compiler/dex/quick/mips/assemble_mips.cc b/compiler/dex/quick/mips/assemble_mips.cc index 4265ae119f..a531317237 100644 --- a/compiler/dex/quick/mips/assemble_mips.cc +++ b/compiler/dex/quick/mips/assemble_mips.cc @@ -16,7 +16,9 @@ #include "codegen_mips.h" -#include "dex/quick/mir_to_lir-inl.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/quick/mir_to_lir.h" #include "mips_lir.h" namespace art { diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc index ed92e82049..ccfdaf60bb 100644 --- a/compiler/dex/quick/mips/call_mips.cc +++ b/compiler/dex/quick/mips/call_mips.cc @@ -18,6 +18,8 @@ #include "codegen_mips.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" #include "entrypoints/quick/quick_entrypoints.h" #include "gc/accounting/card_table.h" diff --git a/compiler/dex/quick/mips/codegen_mips.h b/compiler/dex/quick/mips/codegen_mips.h index ac14704f6b..a37fe40cfa 100644 --- a/compiler/dex/quick/mips/codegen_mips.h +++ b/compiler/dex/quick/mips/codegen_mips.h @@ -17,12 +17,13 @@ #ifndef ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ #define ART_COMPILER_DEX_QUICK_MIPS_CODEGEN_MIPS_H_ -#include "dex/compiler_internals.h" #include "dex/quick/mir_to_lir.h" #include "mips_lir.h" namespace art { +struct CompilationUnit; + class MipsMir2Lir FINAL : public Mir2Lir { protected: class InToRegStorageMipsMapper : public InToRegStorageMapper { diff --git a/compiler/dex/quick/mips/fp_mips.cc b/compiler/dex/quick/mips/fp_mips.cc index 495d85e0a4..d7ed7acf57 100644 --- a/compiler/dex/quick/mips/fp_mips.cc +++ b/compiler/dex/quick/mips/fp_mips.cc @@ -16,6 +16,7 @@ #include "codegen_mips.h" +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "entrypoints/quick/quick_entrypoints.h" #include "mips_lir.h" diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc index aabef60c30..17ac62931d 100644 --- a/compiler/dex/quick/mips/int_mips.cc +++ b/compiler/dex/quick/mips/int_mips.cc @@ -18,6 +18,8 @@ #include "codegen_mips.h" +#include "base/logging.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" #include "entrypoints/quick/quick_entrypoints.h" diff --git a/compiler/dex/quick/mips/mips_lir.h b/compiler/dex/quick/mips/mips_lir.h index 3df8f2ee0b..66e3894204 100644 --- a/compiler/dex/quick/mips/mips_lir.h +++ b/compiler/dex/quick/mips/mips_lir.h @@ -17,7 +17,8 @@ #ifndef ART_COMPILER_DEX_QUICK_MIPS_MIPS_LIR_H_ #define ART_COMPILER_DEX_QUICK_MIPS_MIPS_LIR_H_ -#include "dex/compiler_internals.h" +#include "dex/reg_location.h" +#include "dex/reg_storage.h" namespace art { diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc index c819903b7a..8574ffd541 100644 --- a/compiler/dex/quick/mips/target_mips.cc +++ b/compiler/dex/quick/mips/target_mips.cc @@ -22,8 +22,10 @@ #include "arch/mips/instruction_set_features_mips.h" #include "backend_mips.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" #include "dex/quick/mir_to_lir-inl.h" +#include "driver/compiler_driver.h" #include "mips_lir.h" namespace art { @@ -143,7 +145,8 @@ RegStorage MipsMir2Lir::InToRegStorageMipsMapper::GetNextReg(ShortyArg arg) { */ ResourceMask MipsMir2Lir::GetRegMaskCommon(const RegStorage& reg) const { if (reg.IsDouble()) { - if (cu_->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures()->Is32BitFloatingPoint()) { + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() + ->Is32BitFloatingPoint()) { return ResourceMask::TwoBits((reg.GetRegNum() & ~1) + kMipsFPReg0); } else { return ResourceMask::TwoBits(reg.GetRegNum() * 2 + kMipsFPReg0); @@ -398,7 +401,8 @@ void MipsMir2Lir::ClobberCallerSave() { Clobber(rs_rF13); Clobber(rs_rF14); Clobber(rs_rF15); - if (cu_->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures()->Is32BitFloatingPoint()) { + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() + ->Is32BitFloatingPoint()) { Clobber(rs_rD0_fr0); Clobber(rs_rD1_fr0); Clobber(rs_rD2_fr0); @@ -449,7 +453,7 @@ void MipsMir2Lir::FreeCallTemps() { } bool MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind ATTRIBUTE_UNUSED) { - if (cu_->GetInstructionSetFeatures()->IsSmp()) { + if (cu_->compiler_driver->GetInstructionSetFeatures()->IsSmp()) { NewLIR1(kMipsSync, 0 /* Only stype currently supported */); return true; } else { @@ -459,7 +463,8 @@ bool MipsMir2Lir::GenMemBarrier(MemBarrierKind barrier_kind ATTRIBUTE_UNUSED) { void MipsMir2Lir::CompilerInitializeRegAlloc() { const bool fpu_is_32bit = - cu_->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures()->Is32BitFloatingPoint(); + cu_->compiler_driver->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() + ->Is32BitFloatingPoint(); reg_pool_.reset(new (arena_) RegisterPool(this, arena_, core_regs, empty_pool /* core64 */, sp_regs, fpu_is_32bit ? dp_fr0_regs : dp_fr1_regs, diff --git a/compiler/dex/quick/mips/utility_mips.cc b/compiler/dex/quick/mips/utility_mips.cc index 15fc69d4a2..6f6bf68fea 100644 --- a/compiler/dex/quick/mips/utility_mips.cc +++ b/compiler/dex/quick/mips/utility_mips.cc @@ -17,8 +17,10 @@ #include "codegen_mips.h" #include "arch/mips/instruction_set_features_mips.h" +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" +#include "driver/compiler_driver.h" #include "mips_lir.h" namespace art { @@ -306,7 +308,7 @@ LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) case kOpXor: return OpRegRegReg(op, r_dest_src1, r_dest_src1, r_src2); case kOp2Byte: - if (cu_->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() ->IsMipsIsaRevGreaterThanEqual2()) { res = NewLIR2(kMipsSeb, r_dest_src1.GetReg(), r_src2.GetReg()); } else { @@ -315,7 +317,7 @@ LIR* MipsMir2Lir::OpRegReg(OpKind op, RegStorage r_dest_src1, RegStorage r_src2) } return res; case kOp2Short: - if (cu_->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() + if (cu_->compiler_driver->GetInstructionSetFeatures()->AsMipsInstructionSetFeatures() ->IsMipsIsaRevGreaterThanEqual2()) { res = NewLIR2(kMipsSeh, r_dest_src1.GetReg(), r_src2.GetReg()); } else { diff --git a/compiler/dex/quick/mir_to_lir-inl.h b/compiler/dex/quick/mir_to_lir-inl.h index 144790e9d7..280dbbe106 100644 --- a/compiler/dex/quick/mir_to_lir-inl.h +++ b/compiler/dex/quick/mir_to_lir-inl.h @@ -19,7 +19,8 @@ #include "mir_to_lir.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" namespace art { diff --git a/compiler/dex/quick/mir_to_lir.cc b/compiler/dex/quick/mir_to_lir.cc index 1ff64c9ee7..274e078399 100644 --- a/compiler/dex/quick/mir_to_lir.cc +++ b/compiler/dex/quick/mir_to_lir.cc @@ -14,10 +14,11 @@ * limitations under the License. */ -#include "dex/compiler_internals.h" +#include "mir_to_lir-inl.h" + #include "dex/dataflow_iterator-inl.h" #include "dex/quick/dex_file_method_inliner.h" -#include "mir_to_lir-inl.h" +#include "driver/compiler_driver.h" #include "primitive.h" #include "thread-inl.h" diff --git a/compiler/dex/quick/mir_to_lir.h b/compiler/dex/quick/mir_to_lir.h index fabf941e4f..64ecf946f7 100644 --- a/compiler/dex/quick/mir_to_lir.h +++ b/compiler/dex/quick/mir_to_lir.h @@ -17,15 +17,14 @@ #ifndef ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ #define ART_COMPILER_DEX_QUICK_MIR_TO_LIR_H_ -#include "arch/instruction_set.h" #include "compiled_method.h" #include "dex/compiler_enums.h" -#include "dex/compiler_ir.h" +#include "dex/dex_flags.h" +#include "dex/dex_types.h" #include "dex/reg_location.h" #include "dex/reg_storage.h" #include "dex/backend.h" #include "dex/quick/resource_mask.h" -#include "driver/compiler_driver.h" #include "entrypoints/quick/quick_entrypoints_enum.h" #include "invoke_type.h" #include "leb128.h" @@ -125,10 +124,12 @@ namespace art { #define REG_USE23 (REG_USE2 | REG_USE3) #define REG_USE123 (REG_USE1 | REG_USE2 | REG_USE3) -// TODO: #includes need a cleanup -#ifndef INVALID_SREG -#define INVALID_SREG (-1) -#endif +/* + * Assembly is an iterative process, and usually terminates within + * two or three passes. This should be high enough to handle bizarre + * cases, but detect an infinite loop bug. + */ +#define MAX_ASSEMBLER_RETRIES 50 class BasicBlock; struct CallInfo; @@ -140,7 +141,6 @@ struct RegisterInfo; class DexFileMethodInliner; class MIRGraph; class MirMethodLoweringInfo; -class Mir2Lir; typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, const MethodReference& target_method, @@ -148,6 +148,7 @@ typedef int (*NextCallInsn)(CompilationUnit*, CallInfo*, int, uintptr_t direct_method, InvokeType type); typedef std::vector<uint8_t> CodeBuffer; +typedef uint32_t CodeOffset; // Native code offset in bytes. struct UseDefMasks { const ResourceMask* use_mask; // Resource mask for use. @@ -200,13 +201,6 @@ struct LIR { // Mask to denote sreg as the start of a 64-bit item. Must not interfere with low 16 bits. #define STARTING_WIDE_SREG 0x10000 -// TODO: replace these macros -#define SLOW_FIELD_PATH (cu_->enable_debug & (1 << kDebugSlowFieldPath)) -#define SLOW_INVOKE_PATH (cu_->enable_debug & (1 << kDebugSlowInvokePath)) -#define SLOW_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowStringPath)) -#define SLOW_TYPE_PATH (cu_->enable_debug & (1 << kDebugSlowTypePath)) -#define EXERCISE_SLOWEST_STRING_PATH (cu_->enable_debug & (1 << kDebugSlowestStringPath)) - class Mir2Lir : public Backend { public: static constexpr bool kFailOnSizeError = true && kIsDebugBuild; diff --git a/compiler/dex/quick/quick_compiler.cc b/compiler/dex/quick/quick_compiler.cc index 102ce175a2..699f9908b6 100644 --- a/compiler/dex/quick/quick_compiler.cc +++ b/compiler/dex/quick/quick_compiler.cc @@ -18,8 +18,10 @@ #include <cstdint> +#include "base/logging.h" #include "compiler.h" #include "dex_file-inl.h" +#include "dex/compiler_ir.h" #include "dex/frontend.h" #include "dex/mir_graph.h" #include "dex/quick/mir_to_lir.h" @@ -27,7 +29,6 @@ #include "elf_writer_quick.h" #include "jni/quick/jni_compiler.h" #include "mirror/art_method-inl.h" -#include "base/logging.h" // Specific compiler backends. #include "dex/quick/arm/backend_arm.h" diff --git a/compiler/dex/quick/ralloc_util.cc b/compiler/dex/quick/ralloc_util.cc index 0a98c800a8..8efafb23fe 100644 --- a/compiler/dex/quick/ralloc_util.cc +++ b/compiler/dex/quick/ralloc_util.cc @@ -16,10 +16,13 @@ /* This file contains register alloction support. */ -#include "dex/compiler_ir.h" -#include "dex/compiler_internals.h" #include "mir_to_lir-inl.h" +#include "dex/compiler_ir.h" +#include "dex/mir_graph.h" +#include "driver/compiler_driver.h" +#include "driver/dex_compilation_unit.h" + namespace art { /* diff --git a/compiler/dex/quick/resource_mask.cc b/compiler/dex/quick/resource_mask.cc index ca68f95411..8a27ecb94f 100644 --- a/compiler/dex/quick/resource_mask.cc +++ b/compiler/dex/quick/resource_mask.cc @@ -18,6 +18,7 @@ #include "resource_mask.h" +#include "base/logging.h" #include "utils/arena_allocator.h" #include "utils.h" diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc index ad2ed01ad5..6f26b78872 100644 --- a/compiler/dex/quick/x86/assemble_x86.cc +++ b/compiler/dex/quick/x86/assemble_x86.cc @@ -15,7 +15,10 @@ */ #include "codegen_x86.h" -#include "dex/quick/mir_to_lir-inl.h" + +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/quick/mir_to_lir.h" #include "oat.h" #include "x86_lir.h" diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc index 544ac3b815..aa0972f861 100644 --- a/compiler/dex/quick/x86/call_x86.cc +++ b/compiler/dex/quick/x86/call_x86.cc @@ -17,7 +17,10 @@ /* This file contains codegen for the X86 ISA */ #include "codegen_x86.h" + +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" +#include "driver/compiler_driver.h" #include "gc/accounting/card_table.h" #include "mirror/art_method.h" #include "mirror/object_array-inl.h" diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h index c7d83dda62..3815722f10 100644 --- a/compiler/dex/quick/x86/codegen_x86.h +++ b/compiler/dex/quick/x86/codegen_x86.h @@ -17,7 +17,9 @@ #ifndef ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ #define ART_COMPILER_DEX_QUICK_X86_CODEGEN_X86_H_ -#include "dex/compiler_internals.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" +#include "dex/mir_graph.h" #include "dex/quick/mir_to_lir.h" #include "x86_lir.h" diff --git a/compiler/dex/quick/x86/fp_x86.cc b/compiler/dex/quick/x86/fp_x86.cc index 89c5648d0a..d8616a7bf3 100755 --- a/compiler/dex/quick/x86/fp_x86.cc +++ b/compiler/dex/quick/x86/fp_x86.cc @@ -15,6 +15,8 @@ */ #include "codegen_x86.h" + +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" #include "x86_lir.h" diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc index 03156dc5ad..4fe7a43a85 100755 --- a/compiler/dex/quick/x86/int_x86.cc +++ b/compiler/dex/quick/x86/int_x86.cc @@ -17,6 +17,8 @@ /* This file contains codegen for the X86 ISA */ #include "codegen_x86.h" + +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" #include "mirror/art_method.h" diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc index 142acbc8a4..5a0d6128f1 100755 --- a/compiler/dex/quick/x86/target_x86.cc +++ b/compiler/dex/quick/x86/target_x86.cc @@ -14,16 +14,19 @@ * limitations under the License. */ +#include "codegen_x86.h" + #include <cstdarg> #include <inttypes.h> #include <string> #include "arch/instruction_set_features.h" #include "backend_x86.h" -#include "codegen_x86.h" -#include "dex/compiler_internals.h" +#include "base/logging.h" +#include "dex/compiler_ir.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/reg_storage_eq.h" +#include "driver/compiler_driver.h" #include "mirror/array-inl.h" #include "mirror/art_method.h" #include "mirror/string.h" @@ -596,7 +599,7 @@ bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { } bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { - if (!cu_->GetInstructionSetFeatures()->IsSmp()) { + if (!cu_->compiler_driver->GetInstructionSetFeatures()->IsSmp()) { return false; } // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc index 3b58698619..893b98a49d 100644 --- a/compiler/dex/quick/x86/utility_x86.cc +++ b/compiler/dex/quick/x86/utility_x86.cc @@ -15,12 +15,15 @@ */ #include "codegen_x86.h" + +#include "base/logging.h" #include "dex/quick/mir_to_lir-inl.h" #include "dex/dataflow_iterator-inl.h" -#include "x86_lir.h" #include "dex/quick/dex_file_method_inliner.h" #include "dex/quick/dex_file_to_method_inliner_map.h" #include "dex/reg_storage_eq.h" +#include "driver/compiler_driver.h" +#include "x86_lir.h" namespace art { @@ -509,7 +512,7 @@ LIR* X86Mir2Lir::OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src, int } } if (r_dest != r_src) { - if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case + if ((false) && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case // TODO: fix bug in LEA encoding when disp == 0 return NewLIR5(kX86Lea32RA, r_dest.GetReg(), r5sib_no_base /* base */, r_src.GetReg() /* index */, value /* scale */, 0 /* disp */); diff --git a/compiler/dex/quick/x86/x86_lir.h b/compiler/dex/quick/x86/x86_lir.h index 3e0a8527a3..bc4cb5a9d8 100644 --- a/compiler/dex/quick/x86/x86_lir.h +++ b/compiler/dex/quick/x86/x86_lir.h @@ -17,7 +17,8 @@ #ifndef ART_COMPILER_DEX_QUICK_X86_X86_LIR_H_ #define ART_COMPILER_DEX_QUICK_X86_X86_LIR_H_ -#include "dex/compiler_internals.h" +#include "dex/reg_location.h" +#include "dex/reg_storage.h" namespace art { |