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-rw-r--r--compiler/dex/quick/x86/assemble_x86.cc4
-rw-r--r--compiler/dex/quick/x86/call_x86.cc2
-rw-r--r--compiler/dex/quick/x86/fp_x86.cc2
-rw-r--r--compiler/dex/quick/x86/target_x86.cc4
-rw-r--r--compiler/dex/quick/x86/utility_x86.cc10
-rw-r--r--compiler/dex/quick/x86/x86_lir.h36
6 files changed, 29 insertions, 29 deletions
diff --git a/compiler/dex/quick/x86/assemble_x86.cc b/compiler/dex/quick/x86/assemble_x86.cc
index d864115fc0..e8834320a9 100644
--- a/compiler/dex/quick/x86/assemble_x86.cc
+++ b/compiler/dex/quick/x86/assemble_x86.cc
@@ -474,7 +474,7 @@ int X86Mir2Lir::GetInsnSize(LIR* lir) {
return ComputeSize(entry, lir->operands[1], 0x12345678, true);
} else {
DCHECK(entry->opcode == kX86PcRelAdr);
- return 5; // opcode with reg + 4 byte immediate
+ return 5; // opcode with reg + 4 byte immediate
}
case kMacro:
DCHECK_EQ(lir->opcode, static_cast<int>(kX86StartOfMethod));
@@ -1342,7 +1342,7 @@ AssemblerStatus X86Mir2Lir::AssembleInstructions(uintptr_t start_addr) {
case kShiftRegImm: // lir operands - 0: reg, 1: immediate
EmitShiftRegImm(entry, lir->operands[0], lir->operands[1]);
break;
- case kShiftRegCl: // lir operands - 0: reg, 1: cl
+ case kShiftRegCl: // lir operands - 0: reg, 1: cl
EmitShiftRegCl(entry, lir->operands[0], lir->operands[1]);
break;
case kRegCond: // lir operands - 0: reg, 1: condition
diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc
index 1aeb39ae4b..d530a1c644 100644
--- a/compiler/dex/quick/x86/call_x86.cc
+++ b/compiler/dex/quick/x86/call_x86.cc
@@ -87,7 +87,7 @@ void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
rl_src = LoadValue(rl_src, kCoreReg);
int start_of_method_reg = AllocTemp();
// Materialize a pointer to the switch table
- //NewLIR0(kX86Bkpt);
+ // NewLIR0(kX86Bkpt);
NewLIR1(kX86StartOfMethod, start_of_method_reg);
int low_key = s4FromSwitchData(&table[2]);
int keyReg;
diff --git a/compiler/dex/quick/x86/fp_x86.cc b/compiler/dex/quick/x86/fp_x86.cc
index f2ecf6c959..cc6f374488 100644
--- a/compiler/dex/quick/x86/fp_x86.cc
+++ b/compiler/dex/quick/x86/fp_x86.cc
@@ -373,4 +373,4 @@ bool X86Mir2Lir::GenInlinedSqrt(CallInfo* info) {
-} // namespace art
+} // namespace art
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index 5b64a6b5c3..2c9b3c837c 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -23,7 +23,7 @@
namespace art {
-//FIXME: restore "static" when usage uncovered
+// FIXME: restore "static" when usage uncovered
/*static*/ int core_regs[] = {
rAX, rCX, rDX, rBX, rX86_SP, rBP, rSI, rDI
#ifdef TARGET_REX_SUPPORT
@@ -541,4 +541,4 @@ const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
return X86Mir2Lir::EncodingMap[opcode].fmt;
}
-} // namespace art
+} // namespace art
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index 75367a340a..e15995fef4 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -61,7 +61,7 @@ bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) {
}
bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) {
- return false; // TUNING
+ return false; // TUNING
}
/*
@@ -135,7 +135,7 @@ LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
case kOpAdd: opcode = byte_imm ? kX86Add32RI8 : kX86Add32RI; break;
case kOpOr: opcode = byte_imm ? kX86Or32RI8 : kX86Or32RI; break;
case kOpAdc: opcode = byte_imm ? kX86Adc32RI8 : kX86Adc32RI; break;
- //case kOpSbb: opcode = kX86Sbb32RI; break;
+ // case kOpSbb: opcode = kX86Sbb32RI; break;
case kOpAnd: opcode = byte_imm ? kX86And32RI8 : kX86And32RI; break;
case kOpSub: opcode = byte_imm ? kX86Sub32RI8 : kX86Sub32RI; break;
case kOpXor: opcode = byte_imm ? kX86Xor32RI8 : kX86Xor32RI; break;
@@ -221,7 +221,7 @@ LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,
int r_src2) {
if (r_dest != r_src1 && r_dest != r_src2) {
- if (op == kOpAdd) { // lea special case, except can't encode rbp as base
+ if (op == kOpAdd) { // lea special case, except can't encode rbp as base
if (r_src1 == r_src2) {
OpRegCopy(r_dest, r_src1);
return OpRegImm(kOpLsl, r_dest, 1);
@@ -279,11 +279,11 @@ LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src,
}
}
if (r_dest != r_src) {
- if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case
+ if (false && op == kOpLsl && value >= 0 && value <= 3) { // lea shift special case
// TODO: fix bug in LEA encoding when disp == 0
return NewLIR5(kX86Lea32RA, r_dest, r5sib_no_base /* base */,
r_src /* index */, value /* scale */, 0 /* disp */);
- } else if (op == kOpAdd) { // lea add special case
+ } else if (op == kOpAdd) { // lea add special case
return NewLIR5(kX86Lea32RA, r_dest, r_src /* base */,
r4sib_no_index /* index */, 0 /* scale */, value /* disp */);
}
diff --git a/compiler/dex/quick/x86/x86_lir.h b/compiler/dex/quick/x86/x86_lir.h
index 73e562e85f..643a3d5b8f 100644
--- a/compiler/dex/quick/x86/x86_lir.h
+++ b/compiler/dex/quick/x86/x86_lir.h
@@ -219,7 +219,7 @@ enum X86NativeRegisterPool {
*/
enum X86OpCode {
kX86First = 0,
- kX8632BitData = kX86First, // data [31..0].
+ kX8632BitData = kX86First, // data [31..0].
kX86Bkpt,
kX86Nop,
// Define groups of binary operations
@@ -322,12 +322,12 @@ enum X86OpCode {
Binary0fOpCode(kX86Movss),
kX86MovssMR,
kX86MovssAR,
- Binary0fOpCode(kX86Cvtsi2sd), // int to double
- Binary0fOpCode(kX86Cvtsi2ss), // int to float
- Binary0fOpCode(kX86Cvttsd2si),// truncating double to int
- Binary0fOpCode(kX86Cvttss2si),// truncating float to int
- Binary0fOpCode(kX86Cvtsd2si), // rounding double to int
- Binary0fOpCode(kX86Cvtss2si), // rounding float to int
+ Binary0fOpCode(kX86Cvtsi2sd), // int to double
+ Binary0fOpCode(kX86Cvtsi2ss), // int to float
+ Binary0fOpCode(kX86Cvttsd2si), // truncating double to int
+ Binary0fOpCode(kX86Cvttss2si), // truncating float to int
+ Binary0fOpCode(kX86Cvtsd2si), // rounding double to int
+ Binary0fOpCode(kX86Cvtss2si), // rounding float to int
Binary0fOpCode(kX86Ucomisd), // unordered double compare
Binary0fOpCode(kX86Ucomiss), // unordered float compare
Binary0fOpCode(kX86Comisd), // double compare
@@ -338,8 +338,8 @@ enum X86OpCode {
Binary0fOpCode(kX86Addss), // float add
Binary0fOpCode(kX86Mulsd), // double multiply
Binary0fOpCode(kX86Mulss), // float multiply
- Binary0fOpCode(kX86Cvtsd2ss), // double to float
- Binary0fOpCode(kX86Cvtss2sd), // float to double
+ Binary0fOpCode(kX86Cvtsd2ss), // double to float
+ Binary0fOpCode(kX86Cvtss2sd), // float to double
Binary0fOpCode(kX86Subsd), // double subtract
Binary0fOpCode(kX86Subss), // float subtract
Binary0fOpCode(kX86Divsd), // double divide
@@ -347,13 +347,13 @@ enum X86OpCode {
kX86PsrlqRI, // right shift of floating point registers
kX86PsllqRI, // left shift of floating point registers
Binary0fOpCode(kX86Movdxr), // move into xmm from gpr
- kX86MovdrxRR, kX86MovdrxMR, kX86MovdrxAR,// move into reg from xmm
- kX86Set8R, kX86Set8M, kX86Set8A,// set byte depending on condition operand
+ kX86MovdrxRR, kX86MovdrxMR, kX86MovdrxAR, // move into reg from xmm
+ kX86Set8R, kX86Set8M, kX86Set8A, // set byte depending on condition operand
kX86Mfence, // memory barrier
Binary0fOpCode(kX86Imul16), // 16bit multiply
Binary0fOpCode(kX86Imul32), // 32bit multiply
- kX86CmpxchgRR, kX86CmpxchgMR, kX86CmpxchgAR,// compare and exchange
- kX86LockCmpxchgRR, kX86LockCmpxchgMR, kX86LockCmpxchgAR,// locked compare and exchange
+ kX86CmpxchgRR, kX86CmpxchgMR, kX86CmpxchgAR, // compare and exchange
+ kX86LockCmpxchgRR, kX86LockCmpxchgMR, kX86LockCmpxchgAR, // locked compare and exchange
Binary0fOpCode(kX86Movzx8), // zero-extend 8-bit value
Binary0fOpCode(kX86Movzx16), // zero-extend 16-bit value
Binary0fOpCode(kX86Movsx8), // sign-extend 8-bit value
@@ -383,9 +383,9 @@ enum X86EncodingKind {
kNullary, // Opcode that takes no arguments.
kReg, kMem, kArray, // R, M and A instruction kinds.
kMemReg, kArrayReg, kThreadReg, // MR, AR and TR instruction kinds.
- kRegReg, kRegMem, kRegArray, kRegThread, // RR, RM, RA and RT instruction kinds.
+ kRegReg, kRegMem, kRegArray, kRegThread, // RR, RM, RA and RT instruction kinds.
kRegRegStore, // RR following the store modrm reg-reg encoding rather than the load.
- kRegImm, kMemImm, kArrayImm, kThreadImm, // RI, MI, AI and TI instruction kinds.
+ kRegImm, kMemImm, kArrayImm, kThreadImm, // RI, MI, AI and TI instruction kinds.
kRegRegImm, kRegMemImm, kRegArrayImm, // RRI, RMI and RAI instruction kinds.
kMovRegImm, // Shorter form move RI.
kShiftRegImm, kShiftMemImm, kShiftArrayImm, // Shift opcode with immediate.
@@ -407,13 +407,13 @@ struct X86EncodingMap {
uint8_t prefix1; // non-zero => a prefix byte
uint8_t prefix2; // non-zero => a second prefix byte
uint8_t opcode; // 1 byte opcode
- uint8_t extra_opcode1; // possible extra opcode byte
- uint8_t extra_opcode2; // possible second extra opcode byte
+ uint8_t extra_opcode1; // possible extra opcode byte
+ uint8_t extra_opcode2; // possible second extra opcode byte
// 3bit opcode that gets encoded in the register bits of the modrm byte, use determined by the
// encoding kind
uint8_t modrm_opcode;
uint8_t ax_opcode; // non-zero => shorter encoding for AX as a destination
- uint8_t immediate_bytes; // number of bytes of immediate
+ uint8_t immediate_bytes; // number of bytes of immediate
} skeleton;
const char *name;
const char* fmt;
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-21 18:37:02 +0000