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-rw-r--r--compiler/dex/quick/x86/call_x86.cc27
-rw-r--r--compiler/dex/quick/x86/fp_x86.cc6
-rw-r--r--compiler/dex/quick/x86/int_x86.cc99
-rw-r--r--compiler/dex/quick/x86/target_x86.cc81
-rw-r--r--compiler/dex/quick/x86/utility_x86.cc60
5 files changed, 91 insertions, 182 deletions
diff --git a/compiler/dex/quick/x86/call_x86.cc b/compiler/dex/quick/x86/call_x86.cc
index d60be72c31..1aeb39ae4b 100644
--- a/compiler/dex/quick/x86/call_x86.cc
+++ b/compiler/dex/quick/x86/call_x86.cc
@@ -23,8 +23,7 @@
namespace art {
void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
- SpecialCaseHandler special_case)
-{
+ SpecialCaseHandler special_case) {
// TODO
}
@@ -33,8 +32,7 @@ void X86Mir2Lir::GenSpecialCase(BasicBlock* bb, MIR* mir,
* pairs.
*/
void X86Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
if (cu_->verbose) {
DumpSparseSwitchTable(table);
@@ -69,8 +67,7 @@ void X86Mir2Lir::GenSparseSwitch(MIR* mir, uint32_t table_offset,
* done:
*/
void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
- RegLocation rl_src)
-{
+ RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
if (cu_->verbose) {
DumpPackedSwitchTable(table);
@@ -130,8 +127,7 @@ void X86Mir2Lir::GenPackedSwitch(MIR* mir, uint32_t table_offset,
*
* Total size is 4+(width * size + 1)/2 16-bit code units.
*/
-void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
-{
+void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src) {
const uint16_t* table = cu_->insns + current_dalvik_offset_ + table_offset;
// Add the table to the list - we'll process it later
FillArrayData *tab_rec =
@@ -156,8 +152,7 @@ void X86Mir2Lir::GenFillArrayData(uint32_t table_offset, RegLocation rl_src)
rX86_ARG1, true);
}
-void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
-{
+void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
LoadValueDirectFixed(rl_src, rCX); // Get obj
LockCallTemps(); // Prepare for explicit register usage
@@ -174,8 +169,7 @@ void X86Mir2Lir::GenMonitorEnter(int opt_flags, RegLocation rl_src)
branch->target = NewLIR0(kPseudoTargetLabel);
}
-void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
-{
+void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src) {
FlushAllRegs();
LoadValueDirectFixed(rl_src, rAX); // Get obj
LockCallTemps(); // Prepare for explicit register usage
@@ -195,8 +189,7 @@ void X86Mir2Lir::GenMonitorExit(int opt_flags, RegLocation rl_src)
branch2->target = NewLIR0(kPseudoTargetLabel);
}
-void X86Mir2Lir::GenMoveException(RegLocation rl_dest)
-{
+void X86Mir2Lir::GenMoveException(RegLocation rl_dest) {
int ex_offset = Thread::ExceptionOffset().Int32Value();
RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true);
NewLIR2(kX86Mov32RT, rl_result.low_reg, ex_offset);
@@ -207,8 +200,7 @@ void X86Mir2Lir::GenMoveException(RegLocation rl_dest)
/*
* Mark garbage collection card. Skip if the value we're storing is null.
*/
-void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
-{
+void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg) {
int reg_card_base = AllocTemp();
int reg_card_no = AllocTemp();
LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL);
@@ -222,8 +214,7 @@ void X86Mir2Lir::MarkGCCard(int val_reg, int tgt_addr_reg)
FreeTemp(reg_card_no);
}
-void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method)
-{
+void X86Mir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) {
/*
* On entry, rX86_ARG0, rX86_ARG1, rX86_ARG2 are live. Let the register
* allocation mechanism know so it doesn't try to use any of them when
diff --git a/compiler/dex/quick/x86/fp_x86.cc b/compiler/dex/quick/x86/fp_x86.cc
index 906b4cc759..f2ecf6c959 100644
--- a/compiler/dex/quick/x86/fp_x86.cc
+++ b/compiler/dex/quick/x86/fp_x86.cc
@@ -349,8 +349,7 @@ void X86Mir2Lir::GenFusedFPCmpBranch(BasicBlock* bb, MIR* mir, bool gt_bias,
OpCondBranch(ccode, taken);
}
-void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
-{
+void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src) {
RegLocation rl_result;
rl_src = LoadValue(rl_src, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
@@ -358,8 +357,7 @@ void X86Mir2Lir::GenNegFloat(RegLocation rl_dest, RegLocation rl_src)
StoreValue(rl_dest, rl_result);
}
-void X86Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src)
-{
+void X86Mir2Lir::GenNegDouble(RegLocation rl_dest, RegLocation rl_src) {
RegLocation rl_result;
rl_src = LoadValueWide(rl_src, kCoreReg);
rl_result = EvalLoc(rl_dest, kCoreReg, true);
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc
index 97d9d2deed..3be24df565 100644
--- a/compiler/dex/quick/x86/int_x86.cc
+++ b/compiler/dex/quick/x86/int_x86.cc
@@ -27,8 +27,7 @@ namespace art {
* Perform register memory operation.
*/
LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code,
- int reg1, int base, int offset, ThrowKind kind)
-{
+ int reg1, int base, int offset, ThrowKind kind) {
LIR* tgt = RawLIR(0, kPseudoThrowTarget, kind,
current_dalvik_offset_, reg1, base, offset);
OpRegMem(kOpCmp, reg1, base, offset);
@@ -45,8 +44,7 @@ LIR* X86Mir2Lir::GenRegMemCheck(ConditionCode c_code,
* x > y return 1
*/
void X86Mir2Lir::GenCmpLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
FlushAllRegs();
LockCallTemps(); // Prepare for explicit register usage
LoadValueDirectWideFixed(rl_src1, r0, r1);
@@ -88,8 +86,7 @@ X86ConditionCode X86ConditionEncoding(ConditionCode cond) {
}
LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
- LIR* target)
-{
+ LIR* target) {
NewLIR2(kX86Cmp32RR, src1, src2);
X86ConditionCode cc = X86ConditionEncoding(cond);
LIR* branch = NewLIR2(kX86Jcc8, 0 /* lir operand for Jcc offset */ ,
@@ -99,8 +96,7 @@ LIR* X86Mir2Lir::OpCmpBranch(ConditionCode cond, int src1, int src2,
}
LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
- int check_value, LIR* target)
-{
+ int check_value, LIR* target) {
if ((check_value == 0) && (cond == kCondEq || cond == kCondNe)) {
// TODO: when check_value == 0 and reg is rCX, use the jcxz/nz opcode
NewLIR2(kX86Test32RR, reg, reg);
@@ -113,8 +109,7 @@ LIR* X86Mir2Lir::OpCmpImmBranch(ConditionCode cond, int reg,
return branch;
}
-LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
-{
+LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src) {
if (X86_FPREG(r_dest) || X86_FPREG(r_src))
return OpFpRegCopy(r_dest, r_src);
LIR* res = RawLIR(current_dalvik_offset_, kX86Mov32RR,
@@ -125,16 +120,14 @@ LIR* X86Mir2Lir::OpRegCopyNoInsert(int r_dest, int r_src)
return res;
}
-LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src)
-{
+LIR* X86Mir2Lir::OpRegCopy(int r_dest, int r_src) {
LIR *res = OpRegCopyNoInsert(r_dest, r_src);
AppendLIR(res);
return res;
}
void X86Mir2Lir::OpRegCopyWide(int dest_lo, int dest_hi,
- int src_lo, int src_hi)
-{
+ int src_lo, int src_hi) {
bool dest_fp = X86_FPREG(dest_lo) && X86_FPREG(dest_hi);
bool src_fp = X86_FPREG(src_lo) && X86_FPREG(src_hi);
assert(X86_FPREG(src_lo) == X86_FPREG(src_hi));
@@ -168,8 +161,7 @@ void X86Mir2Lir::OpRegCopyWide(int dest_lo, int dest_hi,
}
}
-void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir)
-{
+void X86Mir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
UNIMPLEMENTED(FATAL) << "Need codegen for GenSelect";
}
@@ -213,21 +205,18 @@ void X86Mir2Lir::GenFusedLongCmpBranch(BasicBlock* bb, MIR* mir) {
}
RegLocation X86Mir2Lir::GenDivRemLit(RegLocation rl_dest, int reg_lo,
- int lit, bool is_div)
-{
+ int lit, bool is_div) {
LOG(FATAL) << "Unexpected use of GenDivRemLit for x86";
return rl_dest;
}
RegLocation X86Mir2Lir::GenDivRem(RegLocation rl_dest, int reg_lo,
- int reg_hi, bool is_div)
-{
+ int reg_hi, bool is_div) {
LOG(FATAL) << "Unexpected use of GenDivRem for x86";
return rl_dest;
}
-bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
-{
+bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min) {
DCHECK_EQ(cu_->instruction_set, kX86);
RegLocation rl_src1 = info->args[0];
RegLocation rl_src2 = info->args[1];
@@ -247,13 +236,11 @@ bool X86Mir2Lir::GenInlinedMinMaxInt(CallInfo* info, bool is_min)
return true;
}
-void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset)
-{
+void X86Mir2Lir::OpLea(int rBase, int reg1, int reg2, int scale, int offset) {
NewLIR5(kX86Lea32RA, rBase, reg1, reg2, scale, offset);
}
-void X86Mir2Lir::OpTlsCmp(int offset, int val)
-{
+void X86Mir2Lir::OpTlsCmp(int offset, int val) {
NewLIR2(kX86Cmp16TI8, offset, val);
}
@@ -267,22 +254,19 @@ LIR* X86Mir2Lir::OpPcRelLoad(int reg, LIR* target) {
return NULL;
}
-LIR* X86Mir2Lir::OpVldm(int rBase, int count)
-{
+LIR* X86Mir2Lir::OpVldm(int rBase, int count) {
LOG(FATAL) << "Unexpected use of OpVldm for x86";
return NULL;
}
-LIR* X86Mir2Lir::OpVstm(int rBase, int count)
-{
+LIR* X86Mir2Lir::OpVstm(int rBase, int count) {
LOG(FATAL) << "Unexpected use of OpVstm for x86";
return NULL;
}
void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
RegLocation rl_result, int lit,
- int first_bit, int second_bit)
-{
+ int first_bit, int second_bit) {
int t_reg = AllocTemp();
OpRegRegImm(kOpLsl, t_reg, rl_src.low_reg, second_bit - first_bit);
OpRegRegReg(kOpAdd, rl_result.low_reg, rl_src.low_reg, t_reg);
@@ -292,8 +276,7 @@ void X86Mir2Lir::GenMultiplyByTwoBitMultiplier(RegLocation rl_src,
}
}
-void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
-{
+void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi) {
int t_reg = AllocTemp();
OpRegRegReg(kOpOr, t_reg, reg_lo, reg_hi);
GenImmedCheck(kCondEq, t_reg, 0, kThrowDivZero);
@@ -301,40 +284,34 @@ void X86Mir2Lir::GenDivZeroCheck(int reg_lo, int reg_hi)
}
// Test suspend flag, return target of taken suspend branch
-LIR* X86Mir2Lir::OpTestSuspend(LIR* target)
-{
+LIR* X86Mir2Lir::OpTestSuspend(LIR* target) {
OpTlsCmp(Thread::ThreadFlagsOffset().Int32Value(), 0);
return OpCondBranch((target == NULL) ? kCondNe : kCondEq, target);
}
// Decrement register and branch on condition
-LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target)
-{
+LIR* X86Mir2Lir::OpDecAndBranch(ConditionCode c_code, int reg, LIR* target) {
OpRegImm(kOpSub, reg, 1);
return OpCmpImmBranch(c_code, reg, 0, target);
}
bool X86Mir2Lir::SmallLiteralDivide(Instruction::Code dalvik_opcode,
- RegLocation rl_src, RegLocation rl_dest, int lit)
-{
+ RegLocation rl_src, RegLocation rl_dest, int lit) {
LOG(FATAL) << "Unexpected use of smallLiteralDive in x86";
return false;
}
-LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide)
-{
+LIR* X86Mir2Lir::OpIT(ConditionCode cond, const char* guide) {
LOG(FATAL) << "Unexpected use of OpIT in x86";
return NULL;
}
void X86Mir2Lir::GenMulLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
LOG(FATAL) << "Unexpected use of GenX86Long for x86";
}
void X86Mir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
// TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
// enough.
FlushAllRegs();
@@ -350,8 +327,7 @@ void X86Mir2Lir::GenAddLong(RegLocation rl_dest, RegLocation rl_src1,
}
void X86Mir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
// TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
// enough.
FlushAllRegs();
@@ -367,8 +343,7 @@ void X86Mir2Lir::GenSubLong(RegLocation rl_dest, RegLocation rl_src1,
}
void X86Mir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
- RegLocation rl_src2)
-{
+ RegLocation rl_src2) {
// TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
// enough.
FlushAllRegs();
@@ -384,8 +359,7 @@ void X86Mir2Lir::GenAndLong(RegLocation rl_dest, RegLocation rl_src1,
}
void X86Mir2Lir::GenOrLong(RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_src1, RegLocation rl_src2) {
// TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
// enough.
FlushAllRegs();
@@ -401,8 +375,7 @@ void X86Mir2Lir::GenOrLong(RegLocation rl_dest,
}
void X86Mir2Lir::GenXorLong(RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_src1, RegLocation rl_src2) {
// TODO: fixed register usage here as we only have 4 temps and temporary allocation isn't smart
// enough.
FlushAllRegs();
@@ -417,8 +390,7 @@ void X86Mir2Lir::GenXorLong(RegLocation rl_dest,
StoreValueWide(rl_dest, rl_result);
}
-void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src)
-{
+void X86Mir2Lir::GenNegLong(RegLocation rl_dest, RegLocation rl_src) {
FlushAllRegs();
LockCallTemps(); // Prepare for explicit register usage
LoadValueDirectWideFixed(rl_src, r0, r1);
@@ -447,8 +419,7 @@ void X86Mir2Lir::OpRegThreadMem(OpKind op, int r_dest, int thread_offset) {
* Generate array load
*/
void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_dest, int scale)
-{
+ RegLocation rl_index, RegLocation rl_dest, int scale) {
RegisterClass reg_class = oat_reg_class_by_size(size);
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
@@ -495,8 +466,7 @@ void X86Mir2Lir::GenArrayGet(int opt_flags, OpSize size, RegLocation rl_array,
*
*/
void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_src, int scale)
-{
+ RegLocation rl_index, RegLocation rl_src, int scale) {
RegisterClass reg_class = oat_reg_class_by_size(size);
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset;
@@ -539,8 +509,7 @@ void X86Mir2Lir::GenArrayPut(int opt_flags, OpSize size, RegLocation rl_array,
*
*/
void X86Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
- RegLocation rl_index, RegLocation rl_src, int scale)
-{
+ RegLocation rl_index, RegLocation rl_src, int scale) {
int len_offset = mirror::Array::LengthOffset().Int32Value();
int data_offset = mirror::Array::DataOffset(sizeof(mirror::Object*)).Int32Value();
@@ -590,15 +559,13 @@ void X86Mir2Lir::GenArrayObjPut(int opt_flags, RegLocation rl_array,
}
void X86Mir2Lir::GenShiftImmOpLong(Instruction::Code opcode, RegLocation rl_dest,
- RegLocation rl_src1, RegLocation rl_shift)
-{
+ RegLocation rl_src1, RegLocation rl_shift) {
// Default implementation is just to ignore the constant case.
GenShiftOpLong(opcode, rl_dest, rl_src1, rl_shift);
}
void X86Mir2Lir::GenArithImmOpLong(Instruction::Code opcode,
- RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2)
-{
+ RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2) {
// Default - bail to non-const handler.
GenArithOpLong(opcode, rl_dest, rl_src1, rl_src2);
}
diff --git a/compiler/dex/quick/x86/target_x86.cc b/compiler/dex/quick/x86/target_x86.cc
index c421ef3f11..5b64a6b5c3 100644
--- a/compiler/dex/quick/x86/target_x86.cc
+++ b/compiler/dex/quick/x86/target_x86.cc
@@ -45,26 +45,22 @@ namespace art {
#endif
};
-RegLocation X86Mir2Lir::LocCReturn()
-{
+RegLocation X86Mir2Lir::LocCReturn() {
RegLocation res = X86_LOC_C_RETURN;
return res;
}
-RegLocation X86Mir2Lir::LocCReturnWide()
-{
+RegLocation X86Mir2Lir::LocCReturnWide() {
RegLocation res = X86_LOC_C_RETURN_WIDE;
return res;
}
-RegLocation X86Mir2Lir::LocCReturnFloat()
-{
+RegLocation X86Mir2Lir::LocCReturnFloat() {
RegLocation res = X86_LOC_C_RETURN_FLOAT;
return res;
}
-RegLocation X86Mir2Lir::LocCReturnDouble()
-{
+RegLocation X86Mir2Lir::LocCReturnDouble() {
RegLocation res = X86_LOC_C_RETURN_DOUBLE;
return res;
}
@@ -95,28 +91,24 @@ int X86Mir2Lir::TargetReg(SpecialTargetRegister reg) {
}
// Create a double from a pair of singles.
-int X86Mir2Lir::S2d(int low_reg, int high_reg)
-{
+int X86Mir2Lir::S2d(int low_reg, int high_reg) {
return X86_S2D(low_reg, high_reg);
}
// Return mask to strip off fp reg flags and bias.
-uint32_t X86Mir2Lir::FpRegMask()
-{
+uint32_t X86Mir2Lir::FpRegMask() {
return X86_FP_REG_MASK;
}
// True if both regs single, both core or both double.
-bool X86Mir2Lir::SameRegType(int reg1, int reg2)
-{
+bool X86Mir2Lir::SameRegType(int reg1, int reg2) {
return (X86_REGTYPE(reg1) == X86_REGTYPE(reg2));
}
/*
* Decode the register id.
*/
-uint64_t X86Mir2Lir::GetRegMaskCommon(int reg)
-{
+uint64_t X86Mir2Lir::GetRegMaskCommon(int reg) {
uint64_t seed;
int shift;
int reg_id;
@@ -131,8 +123,7 @@ uint64_t X86Mir2Lir::GetRegMaskCommon(int reg)
return (seed << shift);
}
-uint64_t X86Mir2Lir::GetPCUseDefEncoding()
-{
+uint64_t X86Mir2Lir::GetPCUseDefEncoding() {
/*
* FIXME: might make sense to use a virtual resource encoding bit for pc. Might be
* able to clean up some of the x86/Arm_Mips differences
@@ -141,8 +132,7 @@ uint64_t X86Mir2Lir::GetPCUseDefEncoding()
return 0ULL;
}
-void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir)
-{
+void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir) {
DCHECK_EQ(cu_->instruction_set, kX86);
// X86-specific resource map setup here.
@@ -263,8 +253,7 @@ std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char
return buf;
}
-void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix)
-{
+void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, uint64_t mask, const char *prefix) {
char buf[256];
buf[0] = 0;
@@ -317,16 +306,14 @@ void X86Mir2Lir::AdjustSpillMask() {
* include any holes in the mask. Associate holes with
* Dalvik register INVALID_VREG (0xFFFFU).
*/
-void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg)
-{
+void X86Mir2Lir::MarkPreservedSingle(int v_reg, int reg) {
UNIMPLEMENTED(WARNING) << "MarkPreservedSingle";
#if 0
LOG(FATAL) << "No support yet for promoted FP regs";
#endif
}
-void X86Mir2Lir::FlushRegWide(int reg1, int reg2)
-{
+void X86Mir2Lir::FlushRegWide(int reg1, int reg2) {
RegisterInfo* info1 = GetRegInfo(reg1);
RegisterInfo* info2 = GetRegInfo(reg2);
DCHECK(info1 && info2 && info1->pair && info2->pair &&
@@ -347,8 +334,7 @@ void X86Mir2Lir::FlushRegWide(int reg1, int reg2)
}
}
-void X86Mir2Lir::FlushReg(int reg)
-{
+void X86Mir2Lir::FlushReg(int reg) {
RegisterInfo* info = GetRegInfo(reg);
if (info->live && info->dirty) {
info->dirty = false;
@@ -363,8 +349,7 @@ bool X86Mir2Lir::IsFpReg(int reg) {
}
/* Clobber all regs that might be used by an external C call */
-void X86Mir2Lir::ClobberCalleeSave()
-{
+void X86Mir2Lir::ClobberCalleeSave() {
Clobber(rAX);
Clobber(rCX);
Clobber(rDX);
@@ -382,8 +367,7 @@ RegLocation X86Mir2Lir::GetReturnWideAlt() {
return res;
}
-RegLocation X86Mir2Lir::GetReturnAlt()
-{
+RegLocation X86Mir2Lir::GetReturnAlt() {
RegLocation res = LocCReturn();
res.low_reg = rDX;
Clobber(rDX);
@@ -391,15 +375,13 @@ RegLocation X86Mir2Lir::GetReturnAlt()
return res;
}
-X86Mir2Lir::RegisterInfo* X86Mir2Lir::GetRegInfo(int reg)
-{
+X86Mir2Lir::RegisterInfo* X86Mir2Lir::GetRegInfo(int reg) {
return X86_FPREG(reg) ? &reg_pool_->FPRegs[reg & X86_FP_REG_MASK]
: &reg_pool_->core_regs[reg];
}
/* To be used when explicitly managing register use */
-void X86Mir2Lir::LockCallTemps()
-{
+void X86Mir2Lir::LockCallTemps() {
LockTemp(rX86_ARG0);
LockTemp(rX86_ARG1);
LockTemp(rX86_ARG2);
@@ -407,16 +389,14 @@ void X86Mir2Lir::LockCallTemps()
}
/* To be used when explicitly managing register use */
-void X86Mir2Lir::FreeCallTemps()
-{
+void X86Mir2Lir::FreeCallTemps() {
FreeTemp(rX86_ARG0);
FreeTemp(rX86_ARG1);
FreeTemp(rX86_ARG2);
FreeTemp(rX86_ARG3);
}
-void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
-{
+void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) {
#if ANDROID_SMP != 0
// TODO: optimize fences
NewLIR0(kX86Mfence);
@@ -427,8 +407,7 @@ void X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind)
* high reg in next byte.
*/
int X86Mir2Lir::AllocTypedTempPair(bool fp_hint,
- int reg_class)
-{
+ int reg_class) {
int high_reg;
int low_reg;
int res = 0;
@@ -485,8 +464,7 @@ void X86Mir2Lir::CompilerInitializeRegAlloc() {
}
void X86Mir2Lir::FreeRegLocTemps(RegLocation rl_keep,
- RegLocation rl_free)
-{
+ RegLocation rl_free) {
if ((rl_free.low_reg != rl_keep.low_reg) && (rl_free.low_reg != rl_keep.high_reg) &&
(rl_free.high_reg != rl_keep.low_reg) && (rl_free.high_reg != rl_keep.high_reg)) {
// No overlap, free both
@@ -525,8 +503,7 @@ void X86Mir2Lir::UnSpillCoreRegs() {
}
}
-bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir)
-{
+bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) {
return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32);
}
@@ -547,24 +524,20 @@ Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph,
}
// Not used in x86
-int X86Mir2Lir::LoadHelper(int offset)
-{
+int X86Mir2Lir::LoadHelper(int offset) {
LOG(FATAL) << "Unexpected use of LoadHelper in x86";
return INVALID_REG;
}
-uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode)
-{
+uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) {
return X86Mir2Lir::EncodingMap[opcode].flags;
}
-const char* X86Mir2Lir::GetTargetInstName(int opcode)
-{
+const char* X86Mir2Lir::GetTargetInstName(int opcode) {
return X86Mir2Lir::EncodingMap[opcode].name;
}
-const char* X86Mir2Lir::GetTargetInstFmt(int opcode)
-{
+const char* X86Mir2Lir::GetTargetInstFmt(int opcode) {
return X86Mir2Lir::EncodingMap[opcode].fmt;
}
diff --git a/compiler/dex/quick/x86/utility_x86.cc b/compiler/dex/quick/x86/utility_x86.cc
index fb07ff1e22..6376e3b87a 100644
--- a/compiler/dex/quick/x86/utility_x86.cc
+++ b/compiler/dex/quick/x86/utility_x86.cc
@@ -22,8 +22,7 @@ namespace art {
/* This file contains codegen for the X86 ISA */
-LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src)
-{
+LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src) {
int opcode;
/* must be both DOUBLE or both not DOUBLE */
DCHECK_EQ(X86_DOUBLEREG(r_dest), X86_DOUBLEREG(r_src));
@@ -49,23 +48,19 @@ LIR* X86Mir2Lir::OpFpRegCopy(int r_dest, int r_src)
return res;
}
-bool X86Mir2Lir::InexpensiveConstantInt(int32_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantInt(int32_t value) {
return true;
}
-bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantFloat(int32_t value) {
return false;
}
-bool X86Mir2Lir::InexpensiveConstantLong(int64_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantLong(int64_t value) {
return true;
}
-bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value)
-{
+bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value) {
return false; // TUNING
}
@@ -78,8 +73,7 @@ bool X86Mir2Lir::InexpensiveConstantDouble(int64_t value)
* 1) r_dest is freshly returned from AllocTemp or
* 2) The codegen is under fixed register usage
*/
-LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value)
-{
+LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value) {
int r_dest_save = r_dest;
if (X86_FPREG(r_dest)) {
if (value == 0) {
@@ -105,23 +99,20 @@ LIR* X86Mir2Lir::LoadConstantNoClobber(int r_dest, int value)
return res;
}
-LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target)
-{
+LIR* X86Mir2Lir::OpUnconditionalBranch(LIR* target) {
LIR* res = NewLIR1(kX86Jmp8, 0 /* offset to be patched during assembly*/ );
res->target = target;
return res;
}
-LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target)
-{
+LIR* X86Mir2Lir::OpCondBranch(ConditionCode cc, LIR* target) {
LIR* branch = NewLIR2(kX86Jcc8, 0 /* offset to be patched */,
X86ConditionEncoding(cc));
branch->target = target;
return branch;
}
-LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src)
-{
+LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpNeg: opcode = kX86Neg32R; break;
@@ -133,8 +124,7 @@ LIR* X86Mir2Lir::OpReg(OpKind op, int r_dest_src)
return NewLIR1(opcode, r_dest_src);
}
-LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value)
-{
+LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value) {
X86OpCode opcode = kX86Bkpt;
bool byte_imm = IS_SIMM8(value);
DCHECK(!X86_FPREG(r_dest_src1));
@@ -160,8 +150,7 @@ LIR* X86Mir2Lir::OpRegImm(OpKind op, int r_dest_src1, int value)
return NewLIR2(opcode, r_dest_src1, value);
}
-LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
-{
+LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2) {
X86OpCode opcode = kX86Nop;
bool src2_must_be_cx = false;
switch (op) {
@@ -207,8 +196,7 @@ LIR* X86Mir2Lir::OpRegReg(OpKind op, int r_dest_src1, int r_src2)
}
LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
- int offset)
-{
+ int offset) {
X86OpCode opcode = kX86Nop;
switch (op) {
// X86 binary opcodes
@@ -231,8 +219,7 @@ LIR* X86Mir2Lir::OpRegMem(OpKind op, int r_dest, int rBase,
}
LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,
- int r_src2)
-{
+ int r_src2) {
if (r_dest != r_src1 && r_dest != r_src2) {
if (op == kOpAdd) { // lea special case, except can't encode rbp as base
if (r_src1 == r_src2) {
@@ -280,8 +267,7 @@ LIR* X86Mir2Lir::OpRegRegReg(OpKind op, int r_dest, int r_src1,
}
LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src,
- int value)
-{
+ int value) {
if (op == kOpMul) {
X86OpCode opcode = IS_SIMM8(value) ? kX86Imul32RRI8 : kX86Imul32RRI;
return NewLIR3(opcode, r_dest, r_src, value);
@@ -306,8 +292,7 @@ LIR* X86Mir2Lir::OpRegRegImm(OpKind op, int r_dest, int r_src,
return OpRegImm(op, r_dest, value);
}
-LIR* X86Mir2Lir::OpThreadMem(OpKind op, int thread_offset)
-{
+LIR* X86Mir2Lir::OpThreadMem(OpKind op, int thread_offset) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpBlx: opcode = kX86CallT; break;
@@ -318,8 +303,7 @@ LIR* X86Mir2Lir::OpThreadMem(OpKind op, int thread_offset)
return NewLIR1(opcode, thread_offset);
}
-LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp)
-{
+LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp) {
X86OpCode opcode = kX86Bkpt;
switch (op) {
case kOpBlx: opcode = kX86CallM; break;
@@ -330,8 +314,7 @@ LIR* X86Mir2Lir::OpMem(OpKind op, int rBase, int disp)
return NewLIR2(opcode, rBase, disp);
}
-LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value)
-{
+LIR* X86Mir2Lir::LoadConstantWide(int r_dest_lo, int r_dest_hi, int64_t value) {
int32_t val_lo = Low32Bits(value);
int32_t val_hi = High32Bits(value);
LIR *res;
@@ -558,23 +541,20 @@ LIR* X86Mir2Lir::StoreBaseIndexedDisp(int rBase, int r_index, int scale,
/* store value base base + scaled index. */
LIR* X86Mir2Lir::StoreBaseIndexed(int rBase, int r_index, int r_src,
- int scale, OpSize size)
-{
+ int scale, OpSize size) {
return StoreBaseIndexedDisp(rBase, r_index, scale, 0,
r_src, INVALID_REG, size, INVALID_SREG);
}
LIR* X86Mir2Lir::StoreBaseDisp(int rBase, int displacement,
- int r_src, OpSize size)
-{
+ int r_src, OpSize size) {
return StoreBaseIndexedDisp(rBase, INVALID_REG, 0,
displacement, r_src, INVALID_REG, size,
INVALID_SREG);
}
LIR* X86Mir2Lir::StoreBaseDispWide(int rBase, int displacement,
- int r_src_lo, int r_src_hi)
-{
+ int r_src_lo, int r_src_hi) {
return StoreBaseIndexedDisp(rBase, INVALID_REG, 0, displacement,
r_src_lo, r_src_hi, kLong, INVALID_SREG);
}
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-21 18:36:44 +0000