diff options
| -rw-r--r-- | compiler/jni/quick/arm64/calling_convention_arm64.cc | 36 | ||||
| -rw-r--r-- | compiler/trampolines/trampoline_compiler.cc | 16 | ||||
| -rw-r--r-- | compiler/utils/arm64/assembler_arm64.cc | 242 | ||||
| -rw-r--r-- | compiler/utils/arm64/assembler_arm64.h | 27 | ||||
| -rw-r--r-- | compiler/utils/arm64/managed_register_arm64.cc | 20 | ||||
| -rw-r--r-- | compiler/utils/arm64/managed_register_arm64.h | 66 | ||||
| -rw-r--r-- | compiler/utils/arm64/managed_register_arm64_test.cc | 248 | ||||
| -rw-r--r-- | runtime/arch/arm64/context_arm64.cc | 10 | ||||
| -rw-r--r-- | runtime/arch/arm64/context_arm64.h | 6 | ||||
| -rw-r--r-- | runtime/arch/arm64/registers_arm64.cc | 4 | ||||
| -rw-r--r-- | runtime/arch/arm64/registers_arm64.h | 6 |
11 files changed, 340 insertions, 341 deletions
diff --git a/compiler/jni/quick/arm64/calling_convention_arm64.cc b/compiler/jni/quick/arm64/calling_convention_arm64.cc index b95dad261e..29763a2a10 100644 --- a/compiler/jni/quick/arm64/calling_convention_arm64.cc +++ b/compiler/jni/quick/arm64/calling_convention_arm64.cc @@ -21,7 +21,7 @@ namespace art { namespace arm64 { -static const Register kCoreArgumentRegisters[] = { +static const XRegister kXArgumentRegisters[] = { X0, X1, X2, X3, X4, X5, X6, X7 }; @@ -39,11 +39,11 @@ static const SRegister kSArgumentRegisters[] = { // Calling convention ManagedRegister Arm64ManagedRuntimeCallingConvention::InterproceduralScratchRegister() { - return Arm64ManagedRegister::FromCoreRegister(X20); // saved on entry restored on exit + return Arm64ManagedRegister::FromXRegister(X20); // saved on entry restored on exit } ManagedRegister Arm64JniCallingConvention::InterproceduralScratchRegister() { - return Arm64ManagedRegister::FromCoreRegister(X20); // saved on entry restored on exit + return Arm64ManagedRegister::FromXRegister(X20); // saved on entry restored on exit } static ManagedRegister ReturnRegisterForShorty(const char* shorty) { @@ -52,7 +52,7 @@ static ManagedRegister ReturnRegisterForShorty(const char* shorty) { } else if (shorty[0] == 'D') { return Arm64ManagedRegister::FromDRegister(D0); } else if (shorty[0] == 'J') { - return Arm64ManagedRegister::FromCoreRegister(X0); + return Arm64ManagedRegister::FromXRegister(X0); } else if (shorty[0] == 'V') { return Arm64ManagedRegister::NoRegister(); } else { @@ -75,7 +75,7 @@ ManagedRegister Arm64JniCallingConvention::IntReturnRegister() { // Managed runtime calling convention ManagedRegister Arm64ManagedRuntimeCallingConvention::MethodRegister() { - return Arm64ManagedRegister::FromCoreRegister(X0); + return Arm64ManagedRegister::FromXRegister(X0); } bool Arm64ManagedRuntimeCallingConvention::IsCurrentParamInRegister() { @@ -129,7 +129,7 @@ const ManagedRegisterEntrySpills& Arm64ManagedRuntimeCallingConvention::EntrySpi } else { // GP regs. if (gp_reg_index < 8) { if (IsCurrentParamALong() && (!IsCurrentParamAReference())) { - entry_spills_.push_back(Arm64ManagedRegister::FromCoreRegister(kCoreArgumentRegisters[gp_reg_index])); + entry_spills_.push_back(Arm64ManagedRegister::FromXRegister(kXArgumentRegisters[gp_reg_index])); } else { entry_spills_.push_back(Arm64ManagedRegister::FromWRegister(kWArgumentRegisters[gp_reg_index])); } @@ -154,17 +154,17 @@ Arm64JniCallingConvention::Arm64JniCallingConvention(bool is_static, bool is_syn : JniCallingConvention(is_static, is_synchronized, shorty, kFramePointerSize) { // TODO: Ugly hard code... // Should generate these according to the spill mask automatically. - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X20)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X21)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X22)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X23)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X24)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X25)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X26)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X27)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X28)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X29)); - callee_save_regs_.push_back(Arm64ManagedRegister::FromCoreRegister(X30)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X20)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X21)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X22)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X23)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X24)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X25)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X26)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X27)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X28)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X29)); + callee_save_regs_.push_back(Arm64ManagedRegister::FromXRegister(X30)); } uint32_t Arm64JniCallingConvention::CoreSpillMask() const { @@ -232,7 +232,7 @@ ManagedRegister Arm64JniCallingConvention::CurrentParamRegister() { int gp_reg = itr_args_ - itr_float_and_doubles_; CHECK_LT(static_cast<unsigned int>(gp_reg), 8u); if (IsCurrentParamALong() || IsCurrentParamAReference() || IsCurrentParamJniEnv()) { - return Arm64ManagedRegister::FromCoreRegister(kCoreArgumentRegisters[gp_reg]); + return Arm64ManagedRegister::FromXRegister(kXArgumentRegisters[gp_reg]); } else { return Arm64ManagedRegister::FromWRegister(kWArgumentRegisters[gp_reg]); } diff --git a/compiler/trampolines/trampoline_compiler.cc b/compiler/trampolines/trampoline_compiler.cc index e793c6b12c..733b58fa5a 100644 --- a/compiler/trampolines/trampoline_compiler.cc +++ b/compiler/trampolines/trampoline_compiler.cc @@ -62,23 +62,23 @@ static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention switch (abi) { case kInterpreterAbi: // Thread* is first argument (X0) in interpreter ABI. - __ JumpTo(Arm64ManagedRegister::FromCoreRegister(X0), Offset(offset.Int32Value()), - Arm64ManagedRegister::FromCoreRegister(IP1)); + __ JumpTo(Arm64ManagedRegister::FromXRegister(X0), Offset(offset.Int32Value()), + Arm64ManagedRegister::FromXRegister(IP1)); break; case kJniAbi: // Load via Thread* held in JNIEnv* in first argument (X0). - __ LoadRawPtr(Arm64ManagedRegister::FromCoreRegister(IP1), - Arm64ManagedRegister::FromCoreRegister(X0), + __ LoadRawPtr(Arm64ManagedRegister::FromXRegister(IP1), + Arm64ManagedRegister::FromXRegister(X0), Offset(JNIEnvExt::SelfOffset().Int32Value())); - __ JumpTo(Arm64ManagedRegister::FromCoreRegister(IP1), Offset(offset.Int32Value()), - Arm64ManagedRegister::FromCoreRegister(IP0)); + __ JumpTo(Arm64ManagedRegister::FromXRegister(IP1), Offset(offset.Int32Value()), + Arm64ManagedRegister::FromXRegister(IP0)); break; case kPortableAbi: // X18 holds Thread*. case kQuickAbi: // Fall-through. - __ JumpTo(Arm64ManagedRegister::FromCoreRegister(TR), Offset(offset.Int32Value()), - Arm64ManagedRegister::FromCoreRegister(IP0)); + __ JumpTo(Arm64ManagedRegister::FromXRegister(TR), Offset(offset.Int32Value()), + Arm64ManagedRegister::FromXRegister(IP0)); break; } diff --git a/compiler/utils/arm64/assembler_arm64.cc b/compiler/utils/arm64/assembler_arm64.cc index 25e02c35da..1af7374a3e 100644 --- a/compiler/utils/arm64/assembler_arm64.cc +++ b/compiler/utils/arm64/assembler_arm64.cc @@ -52,7 +52,7 @@ void Arm64Assembler::FinalizeInstructions(const MemoryRegion& region) { } void Arm64Assembler::GetCurrentThread(ManagedRegister tr) { - ___ Mov(reg_x(tr.AsArm64().AsCoreRegister()), reg_x(ETR)); + ___ Mov(reg_x(tr.AsArm64().AsXRegister()), reg_x(ETR)); } void Arm64Assembler::GetCurrentThread(FrameOffset offset, ManagedRegister /* scratch */) { @@ -71,11 +71,11 @@ void Arm64Assembler::DecreaseFrameSize(size_t adjust) { AddConstant(SP, adjust); } -void Arm64Assembler::AddConstant(Register rd, int32_t value, Condition cond) { +void Arm64Assembler::AddConstant(XRegister rd, int32_t value, Condition cond) { AddConstant(rd, rd, value, cond); } -void Arm64Assembler::AddConstant(Register rd, Register rn, int32_t value, +void Arm64Assembler::AddConstant(XRegister rd, XRegister rn, int32_t value, Condition cond) { if ((cond == al) || (cond == nv)) { // VIXL macro-assembler handles all variants. @@ -92,7 +92,7 @@ void Arm64Assembler::AddConstant(Register rd, Register rn, int32_t value, } void Arm64Assembler::StoreWToOffset(StoreOperandType type, WRegister source, - Register base, int32_t offset) { + XRegister base, int32_t offset) { switch (type) { case kStoreByte: ___ Strb(reg_w(source), MEM_OP(reg_x(base), offset)); @@ -108,16 +108,16 @@ void Arm64Assembler::StoreWToOffset(StoreOperandType type, WRegister source, } } -void Arm64Assembler::StoreToOffset(Register source, Register base, int32_t offset) { +void Arm64Assembler::StoreToOffset(XRegister source, XRegister base, int32_t offset) { CHECK_NE(source, SP); ___ Str(reg_x(source), MEM_OP(reg_x(base), offset)); } -void Arm64Assembler::StoreSToOffset(SRegister source, Register base, int32_t offset) { +void Arm64Assembler::StoreSToOffset(SRegister source, XRegister base, int32_t offset) { ___ Str(reg_s(source), MEM_OP(reg_x(base), offset)); } -void Arm64Assembler::StoreDToOffset(DRegister source, Register base, int32_t offset) { +void Arm64Assembler::StoreDToOffset(DRegister source, XRegister base, int32_t offset) { ___ Str(reg_d(source), MEM_OP(reg_x(base), offset)); } @@ -128,9 +128,9 @@ void Arm64Assembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) } else if (src.IsWRegister()) { CHECK_EQ(4u, size); StoreWToOffset(kStoreWord, src.AsWRegister(), SP, offs.Int32Value()); - } else if (src.IsCoreRegister()) { + } else if (src.IsXRegister()) { CHECK_EQ(8u, size); - StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value()); + StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); } else if (src.IsSRegister()) { StoreSToOffset(src.AsSRegister(), SP, offs.Int32Value()); } else { @@ -141,41 +141,41 @@ void Arm64Assembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) void Arm64Assembler::StoreRef(FrameOffset offs, ManagedRegister m_src) { Arm64ManagedRegister src = m_src.AsArm64(); - CHECK(src.IsCoreRegister()) << src; - StoreWToOffset(kStoreWord, src.AsOverlappingCoreRegisterLow(), SP, + CHECK(src.IsXRegister()) << src; + StoreWToOffset(kStoreWord, src.AsOverlappingWRegister(), SP, offs.Int32Value()); } void Arm64Assembler::StoreRawPtr(FrameOffset offs, ManagedRegister m_src) { Arm64ManagedRegister src = m_src.AsArm64(); - CHECK(src.IsCoreRegister()) << src; - StoreToOffset(src.AsCoreRegister(), SP, offs.Int32Value()); + CHECK(src.IsXRegister()) << src; + StoreToOffset(src.AsXRegister(), SP, offs.Int32Value()); } void Arm64Assembler::StoreImmediateToFrame(FrameOffset offs, uint32_t imm, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; - LoadImmediate(scratch.AsCoreRegister(), imm); - StoreWToOffset(kStoreWord, scratch.AsOverlappingCoreRegisterLow(), SP, + CHECK(scratch.IsXRegister()) << scratch; + LoadImmediate(scratch.AsXRegister(), imm); + StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP, offs.Int32Value()); } void Arm64Assembler::StoreImmediateToThread64(ThreadOffset<8> offs, uint32_t imm, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; - LoadImmediate(scratch.AsCoreRegister(), imm); - StoreToOffset(scratch.AsCoreRegister(), ETR, offs.Int32Value()); + CHECK(scratch.IsXRegister()) << scratch; + LoadImmediate(scratch.AsXRegister(), imm); + StoreToOffset(scratch.AsXRegister(), ETR, offs.Int32Value()); } void Arm64Assembler::StoreStackOffsetToThread64(ThreadOffset<8> tr_offs, FrameOffset fr_offs, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; - AddConstant(scratch.AsCoreRegister(), SP, fr_offs.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), ETR, tr_offs.Int32Value()); + CHECK(scratch.IsXRegister()) << scratch; + AddConstant(scratch.AsXRegister(), SP, fr_offs.Int32Value()); + StoreToOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value()); } void Arm64Assembler::StoreStackPointerToThread64(ThreadOffset<8> tr_offs) { @@ -189,13 +189,13 @@ void Arm64Assembler::StoreSpanning(FrameOffset dest_off, ManagedRegister m_sourc FrameOffset in_off, ManagedRegister m_scratch) { Arm64ManagedRegister source = m_source.AsArm64(); Arm64ManagedRegister scratch = m_scratch.AsArm64(); - StoreToOffset(source.AsCoreRegister(), SP, dest_off.Int32Value()); - LoadFromOffset(scratch.AsCoreRegister(), SP, in_off.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), SP, dest_off.Int32Value() + 8); + StoreToOffset(source.AsXRegister(), SP, dest_off.Int32Value()); + LoadFromOffset(scratch.AsXRegister(), SP, in_off.Int32Value()); + StoreToOffset(scratch.AsXRegister(), SP, dest_off.Int32Value() + 8); } // Load routines. -void Arm64Assembler::LoadImmediate(Register dest, int32_t value, +void Arm64Assembler::LoadImmediate(XRegister dest, int32_t value, Condition cond) { if ((cond == al) || (cond == nv)) { ___ Mov(reg_x(dest), value); @@ -215,7 +215,7 @@ void Arm64Assembler::LoadImmediate(Register dest, int32_t value, } void Arm64Assembler::LoadWFromOffset(LoadOperandType type, WRegister dest, - Register base, int32_t offset) { + XRegister base, int32_t offset) { switch (type) { case kLoadSignedByte: ___ Ldrsb(reg_w(dest), MEM_OP(reg_x(base), offset)); @@ -239,36 +239,36 @@ void Arm64Assembler::LoadWFromOffset(LoadOperandType type, WRegister dest, // Note: We can extend this member by adding load type info - see // sign extended A64 load variants. -void Arm64Assembler::LoadFromOffset(Register dest, Register base, +void Arm64Assembler::LoadFromOffset(XRegister dest, XRegister base, int32_t offset) { CHECK_NE(dest, SP); ___ Ldr(reg_x(dest), MEM_OP(reg_x(base), offset)); } -void Arm64Assembler::LoadSFromOffset(SRegister dest, Register base, +void Arm64Assembler::LoadSFromOffset(SRegister dest, XRegister base, int32_t offset) { ___ Ldr(reg_s(dest), MEM_OP(reg_x(base), offset)); } -void Arm64Assembler::LoadDFromOffset(DRegister dest, Register base, +void Arm64Assembler::LoadDFromOffset(DRegister dest, XRegister base, int32_t offset) { ___ Ldr(reg_d(dest), MEM_OP(reg_x(base), offset)); } -void Arm64Assembler::Load(Arm64ManagedRegister dest, Register base, +void Arm64Assembler::Load(Arm64ManagedRegister dest, XRegister base, int32_t offset, size_t size) { if (dest.IsNoRegister()) { CHECK_EQ(0u, size) << dest; } else if (dest.IsWRegister()) { CHECK_EQ(4u, size) << dest; ___ Ldr(reg_w(dest.AsWRegister()), MEM_OP(reg_x(base), offset)); - } else if (dest.IsCoreRegister()) { - CHECK_NE(dest.AsCoreRegister(), SP) << dest; + } else if (dest.IsXRegister()) { + CHECK_NE(dest.AsXRegister(), SP) << dest; if (size == 4u) { - ___ Ldr(reg_w(dest.AsOverlappingCoreRegisterLow()), MEM_OP(reg_x(base), offset)); + ___ Ldr(reg_w(dest.AsOverlappingWRegister()), MEM_OP(reg_x(base), offset)); } else { CHECK_EQ(8u, size) << dest; - ___ Ldr(reg_x(dest.AsCoreRegister()), MEM_OP(reg_x(base), offset)); + ___ Ldr(reg_x(dest.AsXRegister()), MEM_OP(reg_x(base), offset)); } } else if (dest.IsSRegister()) { ___ Ldr(reg_s(dest.AsSRegister()), MEM_OP(reg_x(base), offset)); @@ -288,19 +288,19 @@ void Arm64Assembler::LoadFromThread64(ManagedRegister m_dst, ThreadOffset<8> src void Arm64Assembler::LoadRef(ManagedRegister m_dst, FrameOffset offs) { Arm64ManagedRegister dst = m_dst.AsArm64(); - CHECK(dst.IsCoreRegister()) << dst; - LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), SP, offs.Int32Value()); + CHECK(dst.IsXRegister()) << dst; + LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), SP, offs.Int32Value()); } void Arm64Assembler::LoadRef(ManagedRegister m_dst, ManagedRegister m_base, MemberOffset offs) { Arm64ManagedRegister dst = m_dst.AsArm64(); Arm64ManagedRegister base = m_base.AsArm64(); - CHECK(dst.IsCoreRegister() && base.IsCoreRegister()); - LoadWFromOffset(kLoadWord, dst.AsOverlappingCoreRegisterLow(), base.AsCoreRegister(), + CHECK(dst.IsXRegister() && base.IsXRegister()); + LoadWFromOffset(kLoadWord, dst.AsOverlappingWRegister(), base.AsXRegister(), offs.Int32Value()); if (kPoisonHeapReferences) { - WRegister ref_reg = dst.AsOverlappingCoreRegisterLow(); + WRegister ref_reg = dst.AsOverlappingWRegister(); ___ Neg(reg_w(ref_reg), vixl::Operand(reg_w(ref_reg))); } } @@ -308,17 +308,17 @@ void Arm64Assembler::LoadRef(ManagedRegister m_dst, ManagedRegister m_base, void Arm64Assembler::LoadRawPtr(ManagedRegister m_dst, ManagedRegister m_base, Offset offs) { Arm64ManagedRegister dst = m_dst.AsArm64(); Arm64ManagedRegister base = m_base.AsArm64(); - CHECK(dst.IsCoreRegister() && base.IsCoreRegister()); + CHECK(dst.IsXRegister() && base.IsXRegister()); // Remove dst and base form the temp list - higher level API uses IP1, IP0. vixl::UseScratchRegisterScope temps(vixl_masm_); - temps.Exclude(reg_x(dst.AsCoreRegister()), reg_x(base.AsCoreRegister())); - ___ Ldr(reg_x(dst.AsCoreRegister()), MEM_OP(reg_x(base.AsCoreRegister()), offs.Int32Value())); + temps.Exclude(reg_x(dst.AsXRegister()), reg_x(base.AsXRegister())); + ___ Ldr(reg_x(dst.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); } void Arm64Assembler::LoadRawPtrFromThread64(ManagedRegister m_dst, ThreadOffset<8> offs) { Arm64ManagedRegister dst = m_dst.AsArm64(); - CHECK(dst.IsCoreRegister()) << dst; - LoadFromOffset(dst.AsCoreRegister(), ETR, offs.Int32Value()); + CHECK(dst.IsXRegister()) << dst; + LoadFromOffset(dst.AsXRegister(), ETR, offs.Int32Value()); } // Copying routines. @@ -326,15 +326,15 @@ void Arm64Assembler::Move(ManagedRegister m_dst, ManagedRegister m_src, size_t s Arm64ManagedRegister dst = m_dst.AsArm64(); Arm64ManagedRegister src = m_src.AsArm64(); if (!dst.Equals(src)) { - if (dst.IsCoreRegister()) { + if (dst.IsXRegister()) { if (size == 4) { CHECK(src.IsWRegister()); - ___ Mov(reg_x(dst.AsCoreRegister()), reg_w(src.AsWRegister())); + ___ Mov(reg_x(dst.AsXRegister()), reg_w(src.AsWRegister())); } else { - if (src.IsCoreRegister()) { - ___ Mov(reg_x(dst.AsCoreRegister()), reg_x(src.AsCoreRegister())); + if (src.IsXRegister()) { + ___ Mov(reg_x(dst.AsXRegister()), reg_x(src.AsXRegister())); } else { - ___ Mov(reg_x(dst.AsCoreRegister()), reg_w(src.AsWRegister())); + ___ Mov(reg_x(dst.AsXRegister()), reg_w(src.AsWRegister())); } } } else if (dst.IsWRegister()) { @@ -355,41 +355,41 @@ void Arm64Assembler::CopyRawPtrFromThread64(FrameOffset fr_offs, ThreadOffset<8> tr_offs, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; - LoadFromOffset(scratch.AsCoreRegister(), ETR, tr_offs.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), SP, fr_offs.Int32Value()); + CHECK(scratch.IsXRegister()) << scratch; + LoadFromOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value()); + StoreToOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value()); } void Arm64Assembler::CopyRawPtrToThread64(ThreadOffset<8> tr_offs, FrameOffset fr_offs, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; - LoadFromOffset(scratch.AsCoreRegister(), SP, fr_offs.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), ETR, tr_offs.Int32Value()); + CHECK(scratch.IsXRegister()) << scratch; + LoadFromOffset(scratch.AsXRegister(), SP, fr_offs.Int32Value()); + StoreToOffset(scratch.AsXRegister(), ETR, tr_offs.Int32Value()); } void Arm64Assembler::CopyRef(FrameOffset dest, FrameOffset src, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; - LoadWFromOffset(kLoadWord, scratch.AsOverlappingCoreRegisterLow(), + CHECK(scratch.IsXRegister()) << scratch; + LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, src.Int32Value()); - StoreWToOffset(kStoreWord, scratch.AsOverlappingCoreRegisterLow(), + StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP, dest.Int32Value()); } void Arm64Assembler::Copy(FrameOffset dest, FrameOffset src, ManagedRegister m_scratch, size_t size) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; + CHECK(scratch.IsXRegister()) << scratch; CHECK(size == 4 || size == 8) << size; if (size == 4) { - LoadWFromOffset(kLoadWord, scratch.AsOverlappingCoreRegisterLow(), SP, src.Int32Value()); - StoreWToOffset(kStoreWord, scratch.AsOverlappingCoreRegisterLow(), SP, dest.Int32Value()); + LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, src.Int32Value()); + StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), SP, dest.Int32Value()); } else if (size == 8) { - LoadFromOffset(scratch.AsCoreRegister(), SP, src.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), SP, dest.Int32Value()); + LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value()); + StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value()); } else { UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; } @@ -399,16 +399,16 @@ void Arm64Assembler::Copy(FrameOffset dest, ManagedRegister src_base, Offset src ManagedRegister m_scratch, size_t size) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); Arm64ManagedRegister base = src_base.AsArm64(); - CHECK(base.IsCoreRegister()) << base; - CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch; + CHECK(base.IsXRegister()) << base; + CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch; CHECK(size == 4 || size == 8) << size; if (size == 4) { - LoadWFromOffset(kLoadWord, scratch.AsWRegister(), base.AsCoreRegister(), + LoadWFromOffset(kLoadWord, scratch.AsWRegister(), base.AsXRegister(), src_offset.Int32Value()); StoreWToOffset(kStoreWord, scratch.AsWRegister(), SP, dest.Int32Value()); } else if (size == 8) { - LoadFromOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), src_offset.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), SP, dest.Int32Value()); + LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), src_offset.Int32Value()); + StoreToOffset(scratch.AsXRegister(), SP, dest.Int32Value()); } else { UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; } @@ -418,16 +418,16 @@ void Arm64Assembler::Copy(ManagedRegister m_dest_base, Offset dest_offs, FrameOf ManagedRegister m_scratch, size_t size) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); Arm64ManagedRegister base = m_dest_base.AsArm64(); - CHECK(base.IsCoreRegister()) << base; - CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch; + CHECK(base.IsXRegister()) << base; + CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch; CHECK(size == 4 || size == 8) << size; if (size == 4) { LoadWFromOffset(kLoadWord, scratch.AsWRegister(), SP, src.Int32Value()); - StoreWToOffset(kStoreWord, scratch.AsWRegister(), base.AsCoreRegister(), + StoreWToOffset(kStoreWord, scratch.AsWRegister(), base.AsXRegister(), dest_offs.Int32Value()); } else if (size == 8) { - LoadFromOffset(scratch.AsCoreRegister(), SP, src.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), dest_offs.Int32Value()); + LoadFromOffset(scratch.AsXRegister(), SP, src.Int32Value()); + StoreToOffset(scratch.AsXRegister(), base.AsXRegister(), dest_offs.Int32Value()); } else { UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; } @@ -444,25 +444,25 @@ void Arm64Assembler::Copy(ManagedRegister m_dest, Offset dest_offset, Arm64ManagedRegister scratch = m_scratch.AsArm64(); Arm64ManagedRegister src = m_src.AsArm64(); Arm64ManagedRegister dest = m_dest.AsArm64(); - CHECK(dest.IsCoreRegister()) << dest; - CHECK(src.IsCoreRegister()) << src; - CHECK(scratch.IsCoreRegister() || scratch.IsWRegister()) << scratch; + CHECK(dest.IsXRegister()) << dest; + CHECK(src.IsXRegister()) << src; + CHECK(scratch.IsXRegister() || scratch.IsWRegister()) << scratch; CHECK(size == 4 || size == 8) << size; if (size == 4) { if (scratch.IsWRegister()) { - LoadWFromOffset(kLoadWord, scratch.AsWRegister(), src.AsCoreRegister(), + LoadWFromOffset(kLoadWord, scratch.AsWRegister(), src.AsXRegister(), src_offset.Int32Value()); - StoreWToOffset(kStoreWord, scratch.AsWRegister(), dest.AsCoreRegister(), + StoreWToOffset(kStoreWord, scratch.AsWRegister(), dest.AsXRegister(), dest_offset.Int32Value()); } else { - LoadWFromOffset(kLoadWord, scratch.AsOverlappingCoreRegisterLow(), src.AsCoreRegister(), + LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), src.AsXRegister(), src_offset.Int32Value()); - StoreWToOffset(kStoreWord, scratch.AsOverlappingCoreRegisterLow(), dest.AsCoreRegister(), + StoreWToOffset(kStoreWord, scratch.AsOverlappingWRegister(), dest.AsXRegister(), dest_offset.Int32Value()); } } else if (size == 8) { - LoadFromOffset(scratch.AsCoreRegister(), src.AsCoreRegister(), src_offset.Int32Value()); - StoreToOffset(scratch.AsCoreRegister(), dest.AsCoreRegister(), dest_offset.Int32Value()); + LoadFromOffset(scratch.AsXRegister(), src.AsXRegister(), src_offset.Int32Value()); + StoreToOffset(scratch.AsXRegister(), dest.AsXRegister(), dest_offset.Int32Value()); } else { UNIMPLEMENTED(FATAL) << "We only support Copy() of size 4 and 8"; } @@ -514,31 +514,31 @@ void Arm64Assembler::VerifyObject(FrameOffset /*src*/, bool /*could_be_null*/) { void Arm64Assembler::Call(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) { Arm64ManagedRegister base = m_base.AsArm64(); Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(base.IsCoreRegister()) << base; - CHECK(scratch.IsCoreRegister()) << scratch; - LoadFromOffset(scratch.AsCoreRegister(), base.AsCoreRegister(), offs.Int32Value()); - ___ Blr(reg_x(scratch.AsCoreRegister())); + CHECK(base.IsXRegister()) << base; + CHECK(scratch.IsXRegister()) << scratch; + LoadFromOffset(scratch.AsXRegister(), base.AsXRegister(), offs.Int32Value()); + ___ Blr(reg_x(scratch.AsXRegister())); } void Arm64Assembler::JumpTo(ManagedRegister m_base, Offset offs, ManagedRegister m_scratch) { Arm64ManagedRegister base = m_base.AsArm64(); Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(base.IsCoreRegister()) << base; - CHECK(scratch.IsCoreRegister()) << scratch; + CHECK(base.IsXRegister()) << base; + CHECK(scratch.IsXRegister()) << scratch; // Remove base and scratch form the temp list - higher level API uses IP1, IP0. vixl::UseScratchRegisterScope temps(vixl_masm_); - temps.Exclude(reg_x(base.AsCoreRegister()), reg_x(scratch.AsCoreRegister())); - ___ Ldr(reg_x(scratch.AsCoreRegister()), MEM_OP(reg_x(base.AsCoreRegister()), offs.Int32Value())); - ___ Br(reg_x(scratch.AsCoreRegister())); + temps.Exclude(reg_x(base.AsXRegister()), reg_x(scratch.AsXRegister())); + ___ Ldr(reg_x(scratch.AsXRegister()), MEM_OP(reg_x(base.AsXRegister()), offs.Int32Value())); + ___ Br(reg_x(scratch.AsXRegister())); } void Arm64Assembler::Call(FrameOffset base, Offset offs, ManagedRegister m_scratch) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; + CHECK(scratch.IsXRegister()) << scratch; // Call *(*(SP + base) + offset) - LoadWFromOffset(kLoadWord, scratch.AsOverlappingCoreRegisterLow(), SP, base.Int32Value()); - LoadFromOffset(scratch.AsCoreRegister(), scratch.AsCoreRegister(), offs.Int32Value()); - ___ Blr(reg_x(scratch.AsCoreRegister())); + LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, base.Int32Value()); + LoadFromOffset(scratch.AsXRegister(), scratch.AsXRegister(), offs.Int32Value()); + ___ Blr(reg_x(scratch.AsXRegister())); } void Arm64Assembler::CallFromThread64(ThreadOffset<8> /*offset*/, ManagedRegister /*scratch*/) { @@ -550,59 +550,59 @@ void Arm64Assembler::CreateHandleScopeEntry(ManagedRegister m_out_reg, FrameOffs Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); // For now we only hold stale handle scope entries in x registers. - CHECK(in_reg.IsNoRegister() || in_reg.IsCoreRegister()) << in_reg; - CHECK(out_reg.IsCoreRegister()) << out_reg; + CHECK(in_reg.IsNoRegister() || in_reg.IsXRegister()) << in_reg; + CHECK(out_reg.IsXRegister()) << out_reg; if (null_allowed) { // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is // the address in the handle scope holding the reference. // e.g. out_reg = (handle == 0) ? 0 : (SP+handle_offset) if (in_reg.IsNoRegister()) { - LoadWFromOffset(kLoadWord, out_reg.AsOverlappingCoreRegisterLow(), SP, + LoadWFromOffset(kLoadWord, out_reg.AsOverlappingWRegister(), SP, handle_scope_offs.Int32Value()); in_reg = out_reg; } - ___ Cmp(reg_w(in_reg.AsOverlappingCoreRegisterLow()), 0); + ___ Cmp(reg_w(in_reg.AsOverlappingWRegister()), 0); if (!out_reg.Equals(in_reg)) { - LoadImmediate(out_reg.AsCoreRegister(), 0, eq); + LoadImmediate(out_reg.AsXRegister(), 0, eq); } - AddConstant(out_reg.AsCoreRegister(), SP, handle_scope_offs.Int32Value(), ne); + AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), ne); } else { - AddConstant(out_reg.AsCoreRegister(), SP, handle_scope_offs.Int32Value(), al); + AddConstant(out_reg.AsXRegister(), SP, handle_scope_offs.Int32Value(), al); } } void Arm64Assembler::CreateHandleScopeEntry(FrameOffset out_off, FrameOffset handle_scope_offset, ManagedRegister m_scratch, bool null_allowed) { Arm64ManagedRegister scratch = m_scratch.AsArm64(); - CHECK(scratch.IsCoreRegister()) << scratch; + CHECK(scratch.IsXRegister()) << scratch; if (null_allowed) { - LoadWFromOffset(kLoadWord, scratch.AsOverlappingCoreRegisterLow(), SP, + LoadWFromOffset(kLoadWord, scratch.AsOverlappingWRegister(), SP, handle_scope_offset.Int32Value()); // Null values get a handle scope entry value of 0. Otherwise, the handle scope entry is // the address in the handle scope holding the reference. // e.g. scratch = (scratch == 0) ? 0 : (SP+handle_scope_offset) - ___ Cmp(reg_w(scratch.AsOverlappingCoreRegisterLow()), 0); + ___ Cmp(reg_w(scratch.AsOverlappingWRegister()), 0); // Move this logic in add constants with flags. - AddConstant(scratch.AsCoreRegister(), SP, handle_scope_offset.Int32Value(), ne); + AddConstant(scratch.AsXRegister(), SP, handle_scope_offset.Int32Value(), ne); } else { - AddConstant(scratch.AsCoreRegister(), SP, handle_scope_offset.Int32Value(), al); + AddConstant(scratch.AsXRegister(), SP, handle_scope_offset.Int32Value(), al); } - StoreToOffset(scratch.AsCoreRegister(), SP, out_off.Int32Value()); + StoreToOffset(scratch.AsXRegister(), SP, out_off.Int32Value()); } void Arm64Assembler::LoadReferenceFromHandleScope(ManagedRegister m_out_reg, ManagedRegister m_in_reg) { Arm64ManagedRegister out_reg = m_out_reg.AsArm64(); Arm64ManagedRegister in_reg = m_in_reg.AsArm64(); - CHECK(out_reg.IsCoreRegister()) << out_reg; - CHECK(in_reg.IsCoreRegister()) << in_reg; + CHECK(out_reg.IsXRegister()) << out_reg; + CHECK(in_reg.IsXRegister()) << in_reg; vixl::Label exit; if (!out_reg.Equals(in_reg)) { // FIXME: Who sets the flags here? - LoadImmediate(out_reg.AsCoreRegister(), 0, eq); + LoadImmediate(out_reg.AsXRegister(), 0, eq); } - ___ Cbz(reg_x(in_reg.AsCoreRegister()), &exit); - LoadFromOffset(out_reg.AsCoreRegister(), in_reg.AsCoreRegister(), 0); + ___ Cbz(reg_x(in_reg.AsXRegister()), &exit); + LoadFromOffset(out_reg.AsXRegister(), in_reg.AsXRegister(), 0); ___ Bind(&exit); } @@ -611,13 +611,13 @@ void Arm64Assembler::ExceptionPoll(ManagedRegister m_scratch, size_t stack_adjus Arm64ManagedRegister scratch = m_scratch.AsArm64(); Arm64Exception *current_exception = new Arm64Exception(scratch, stack_adjust); exception_blocks_.push_back(current_exception); - LoadFromOffset(scratch.AsCoreRegister(), ETR, Thread::ExceptionOffset<8>().Int32Value()); - ___ Cbnz(reg_x(scratch.AsCoreRegister()), current_exception->Entry()); + LoadFromOffset(scratch.AsXRegister(), ETR, Thread::ExceptionOffset<8>().Int32Value()); + ___ Cbnz(reg_x(scratch.AsXRegister()), current_exception->Entry()); } void Arm64Assembler::EmitExceptionPoll(Arm64Exception *exception) { vixl::UseScratchRegisterScope temps(vixl_masm_); - temps.Exclude(reg_x(exception->scratch_.AsCoreRegister())); + temps.Exclude(reg_x(exception->scratch_.AsXRegister())); vixl::Register temp = temps.AcquireX(); // Bind exception poll entry. @@ -627,7 +627,7 @@ void Arm64Assembler::EmitExceptionPoll(Arm64Exception *exception) { } // Pass exception object as argument. // Don't care about preserving X0 as this won't return. - ___ Mov(reg_x(X0), reg_x(exception->scratch_.AsCoreRegister())); + ___ Mov(reg_x(X0), reg_x(exception->scratch_.AsXRegister())); ___ Ldr(temp, MEM_OP(reg_x(ETR), QUICK_ENTRYPOINT_OFFSET(8, pDeliverException).Int32Value())); // Move ETR(Callee saved) back to TR(Caller saved) reg. We use ETR on calls @@ -646,7 +646,7 @@ void Arm64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, const std::vector<ManagedRegister>& callee_save_regs, const ManagedRegisterEntrySpills& entry_spills) { CHECK_ALIGNED(frame_size, kStackAlignment); - CHECK(X0 == method_reg.AsArm64().AsCoreRegister()); + CHECK(X0 == method_reg.AsArm64().AsXRegister()); // TODO: *create APCS FP - end of FP chain; // *add support for saving a different set of callee regs. @@ -700,8 +700,8 @@ void Arm64Assembler::BuildFrame(size_t frame_size, ManagedRegister method_reg, // only increment stack offset. ManagedRegisterSpill spill = entry_spills.at(i); offset += spill.getSize(); - } else if (reg.IsCoreRegister()) { - StoreToOffset(reg.AsCoreRegister(), SP, offset); + } else if (reg.IsXRegister()) { + StoreToOffset(reg.AsXRegister(), SP, offset); offset += 8; } else if (reg.IsWRegister()) { StoreWToOffset(kStoreWord, reg.AsWRegister(), SP, offset); diff --git a/compiler/utils/arm64/assembler_arm64.h b/compiler/utils/arm64/assembler_arm64.h index cf831f86f1..c144991cfc 100644 --- a/compiler/utils/arm64/assembler_arm64.h +++ b/compiler/utils/arm64/assembler_arm64.h @@ -173,7 +173,7 @@ class Arm64Assembler FINAL : public Assembler { private: static vixl::Register reg_x(int code) { - CHECK(code < kNumberOfCoreRegisters) << code; + CHECK(code < kNumberOfXRegisters) << code; if (code == SP) { return vixl::sp; } else if (code == XZR) { @@ -183,6 +183,7 @@ class Arm64Assembler FINAL : public Assembler { } static vixl::Register reg_w(int code) { + CHECK(code < kNumberOfWRegisters) << code; if (code == WSP) { return vixl::wsp; } else if (code == WZR) { @@ -203,20 +204,20 @@ class Arm64Assembler FINAL : public Assembler { void EmitExceptionPoll(Arm64Exception *exception); void StoreWToOffset(StoreOperandType type, WRegister source, - Register base, int32_t offset); - void StoreToOffset(Register source, Register base, int32_t offset); - void StoreSToOffset(SRegister source, Register base, int32_t offset); - void StoreDToOffset(DRegister source, Register base, int32_t offset); + XRegister base, int32_t offset); + void StoreToOffset(XRegister source, XRegister base, int32_t offset); + void StoreSToOffset(SRegister source, XRegister base, int32_t offset); + void StoreDToOffset(DRegister source, XRegister base, int32_t offset); - void LoadImmediate(Register dest, int32_t value, vixl::Condition cond = vixl::al); - void Load(Arm64ManagedRegister dst, Register src, int32_t src_offset, size_t size); + void LoadImmediate(XRegister dest, int32_t value, vixl::Condition cond = vixl::al); + void Load(Arm64ManagedRegister dst, XRegister src, int32_t src_offset, size_t size); void LoadWFromOffset(LoadOperandType type, WRegister dest, - Register base, int32_t offset); - void LoadFromOffset(Register dest, Register base, int32_t offset); - void LoadSFromOffset(SRegister dest, Register base, int32_t offset); - void LoadDFromOffset(DRegister dest, Register base, int32_t offset); - void AddConstant(Register rd, int32_t value, vixl::Condition cond = vixl::al); - void AddConstant(Register rd, Register rn, int32_t value, vixl::Condition cond = vixl::al); + XRegister base, int32_t offset); + void LoadFromOffset(XRegister dest, XRegister base, int32_t offset); + void LoadSFromOffset(SRegister dest, XRegister base, int32_t offset); + void LoadDFromOffset(DRegister dest, XRegister base, int32_t offset); + void AddConstant(XRegister rd, int32_t value, vixl::Condition cond = vixl::al); + void AddConstant(XRegister rd, XRegister rn, int32_t value, vixl::Condition cond = vixl::al); // Vixl assembler. vixl::MacroAssembler* const vixl_masm_; diff --git a/compiler/utils/arm64/managed_register_arm64.cc b/compiler/utils/arm64/managed_register_arm64.cc index db040e3fa2..47924bf99f 100644 --- a/compiler/utils/arm64/managed_register_arm64.cc +++ b/compiler/utils/arm64/managed_register_arm64.cc @@ -27,7 +27,7 @@ namespace arm64 { // * [W0, W15] // * [D0, D31] // * [S0, S31] -// static const int kNumberOfAvailableCoreRegisters = (X15 - X0) + 1; +// static const int kNumberOfAvailableXRegisters = (X15 - X0) + 1; // static const int kNumberOfAvailableWRegisters = (W15 - W0) + 1; // static const int kNumberOfAvailableDRegisters = kNumberOfDRegisters; // static const int kNumberOfAvailableSRegisters = kNumberOfSRegisters; @@ -48,8 +48,8 @@ bool Arm64ManagedRegister::Overlaps(const Arm64ManagedRegister& other) const { int Arm64ManagedRegister::RegNo() const { CHECK(!IsNoRegister()); int no; - if (IsCoreRegister()) { - no = static_cast<int>(AsCoreRegister()); + if (IsXRegister()) { + no = static_cast<int>(AsXRegister()); } else if (IsWRegister()) { no = static_cast<int>(AsWRegister()); } else if (IsDRegister()) { @@ -63,12 +63,12 @@ int Arm64ManagedRegister::RegNo() const { } int Arm64ManagedRegister::RegIdLow() const { - CHECK(IsCoreRegister() || IsDRegister()); + CHECK(IsXRegister() || IsDRegister()); int low = RegNo(); - if (IsCoreRegister()) { - low += kNumberOfCoreRegIds; + if (IsXRegister()) { + low += kNumberOfXRegIds; } else if (IsDRegister()) { - low += kNumberOfCoreRegIds + kNumberOfWRegIds + kNumberOfDRegIds; + low += kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds; } return low; } @@ -78,7 +78,7 @@ int Arm64ManagedRegister::RegIdHigh() const { CHECK(IsWRegister() || IsSRegister()); int high = RegNo(); if (IsSRegister()) { - high += kNumberOfCoreRegIds + kNumberOfWRegIds; + high += kNumberOfXRegIds + kNumberOfWRegIds; } return high; } @@ -86,8 +86,8 @@ int Arm64ManagedRegister::RegIdHigh() const { void Arm64ManagedRegister::Print(std::ostream& os) const { if (!IsValidManagedRegister()) { os << "No Register"; - } else if (IsCoreRegister()) { - os << "XCore: " << static_cast<int>(AsCoreRegister()); + } else if (IsXRegister()) { + os << "XCore: " << static_cast<int>(AsXRegister()); } else if (IsWRegister()) { os << "WCore: " << static_cast<int>(AsWRegister()); } else if (IsDRegister()) { diff --git a/compiler/utils/arm64/managed_register_arm64.h b/compiler/utils/arm64/managed_register_arm64.h index 2c5250475a..e1d6f3179d 100644 --- a/compiler/utils/arm64/managed_register_arm64.h +++ b/compiler/utils/arm64/managed_register_arm64.h @@ -24,29 +24,29 @@ namespace art { namespace arm64 { -const int kNumberOfCoreRegIds = kNumberOfCoreRegisters; +const int kNumberOfXRegIds = kNumberOfXRegisters; const int kNumberOfWRegIds = kNumberOfWRegisters; const int kNumberOfDRegIds = kNumberOfDRegisters; const int kNumberOfSRegIds = kNumberOfSRegisters; -const int kNumberOfRegIds = kNumberOfCoreRegIds + kNumberOfWRegIds + +const int kNumberOfRegIds = kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds + kNumberOfSRegIds; // Register ids map: -// [0..X[ core registers 64bit (enum Register) +// [0..X[ core registers 64bit (enum XRegister) // [X..W[ core registers 32bit (enum WRegister) // [W..D[ double precision VFP registers (enum DRegister) // [D..S[ single precision VFP registers (enum SRegister) // // where: -// X = kNumberOfCoreRegIds +// X = kNumberOfXRegIds // W = X + kNumberOfWRegIds // D = W + kNumberOfDRegIds // S = D + kNumberOfSRegIds // // An instance of class 'ManagedRegister' represents a single Arm64 // register. A register can be one of the following: -// * core register 64bit context (enum Register) +// * core register 64bit context (enum XRegister) // * core register 32bit context (enum WRegister) // * VFP double precision register (enum DRegister) // * VFP single precision register (enum SRegister) @@ -55,76 +55,74 @@ const int kNumberOfRegIds = kNumberOfCoreRegIds + kNumberOfWRegIds + class Arm64ManagedRegister : public ManagedRegister { public: - Register AsCoreRegister() const { - CHECK(IsCoreRegister()); - return static_cast<Register>(id_); + XRegister AsXRegister() const { + CHECK(IsXRegister()); + return static_cast<XRegister>(id_); } WRegister AsWRegister() const { CHECK(IsWRegister()); - return static_cast<WRegister>(id_ - kNumberOfCoreRegIds); + return static_cast<WRegister>(id_ - kNumberOfXRegIds); } DRegister AsDRegister() const { CHECK(IsDRegister()); - return static_cast<DRegister>(id_ - kNumberOfCoreRegIds - kNumberOfWRegIds); + return static_cast<DRegister>(id_ - kNumberOfXRegIds - kNumberOfWRegIds); } SRegister AsSRegister() const { CHECK(IsSRegister()); - return static_cast<SRegister>(id_ - kNumberOfCoreRegIds - kNumberOfWRegIds - + return static_cast<SRegister>(id_ - kNumberOfXRegIds - kNumberOfWRegIds - kNumberOfDRegIds); } - WRegister AsOverlappingCoreRegisterLow() const { + WRegister AsOverlappingWRegister() const { CHECK(IsValidManagedRegister()); if (IsZeroRegister()) return WZR; - return static_cast<WRegister>(AsCoreRegister()); + return static_cast<WRegister>(AsXRegister()); } - // FIXME: Find better naming. - Register AsOverlappingWRegisterCore() const { + XRegister AsOverlappingXRegister() const { CHECK(IsValidManagedRegister()); - return static_cast<Register>(AsWRegister()); + return static_cast<XRegister>(AsWRegister()); } - SRegister AsOverlappingDRegisterLow() const { + SRegister AsOverlappingSRegister() const { CHECK(IsValidManagedRegister()); return static_cast<SRegister>(AsDRegister()); } - // FIXME: Find better naming. - DRegister AsOverlappingSRegisterD() const { + DRegister AsOverlappingDRegister() const { CHECK(IsValidManagedRegister()); return static_cast<DRegister>(AsSRegister()); } - bool IsCoreRegister() const { + bool IsXRegister() const { CHECK(IsValidManagedRegister()); - return (0 <= id_) && (id_ < kNumberOfCoreRegIds); + return (0 <= id_) && (id_ < kNumberOfXRegIds); } bool IsWRegister() const { CHECK(IsValidManagedRegister()); - const int test = id_ - kNumberOfCoreRegIds; + const int test = id_ - kNumberOfXRegIds; return (0 <= test) && (test < kNumberOfWRegIds); } bool IsDRegister() const { CHECK(IsValidManagedRegister()); - const int test = id_ - (kNumberOfCoreRegIds + kNumberOfWRegIds); + const int test = id_ - (kNumberOfXRegIds + kNumberOfWRegIds); return (0 <= test) && (test < kNumberOfDRegIds); } bool IsSRegister() const { CHECK(IsValidManagedRegister()); - const int test = id_ - (kNumberOfCoreRegIds + kNumberOfWRegIds + + const int test = id_ - (kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds); return (0 <= test) && (test < kNumberOfSRegIds); } bool IsGPRegister() const { - return IsCoreRegister() || IsWRegister(); + return IsXRegister() || IsWRegister(); } bool IsFPRegister() const { @@ -134,7 +132,7 @@ class Arm64ManagedRegister : public ManagedRegister { bool IsSameType(Arm64ManagedRegister test) const { CHECK(IsValidManagedRegister() && test.IsValidManagedRegister()); return - (IsCoreRegister() && test.IsCoreRegister()) || + (IsXRegister() && test.IsXRegister()) || (IsWRegister() && test.IsWRegister()) || (IsDRegister() && test.IsDRegister()) || (IsSRegister() && test.IsSRegister()); @@ -147,29 +145,29 @@ class Arm64ManagedRegister : public ManagedRegister { void Print(std::ostream& os) const; - static Arm64ManagedRegister FromCoreRegister(Register r) { + static Arm64ManagedRegister FromXRegister(XRegister r) { CHECK_NE(r, kNoRegister); return FromRegId(r); } static Arm64ManagedRegister FromWRegister(WRegister r) { CHECK_NE(r, kNoWRegister); - return FromRegId(r + kNumberOfCoreRegIds); + return FromRegId(r + kNumberOfXRegIds); } static Arm64ManagedRegister FromDRegister(DRegister r) { CHECK_NE(r, kNoDRegister); - return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfWRegIds)); + return FromRegId(r + (kNumberOfXRegIds + kNumberOfWRegIds)); } static Arm64ManagedRegister FromSRegister(SRegister r) { CHECK_NE(r, kNoSRegister); - return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfWRegIds + + return FromRegId(r + (kNumberOfXRegIds + kNumberOfWRegIds + kNumberOfDRegIds)); } // Returns the X register overlapping W register r. - static Arm64ManagedRegister FromWRegisterCore(WRegister r) { + static Arm64ManagedRegister FromWRegisterX(WRegister r) { CHECK_NE(r, kNoWRegister); return FromRegId(r); } @@ -177,7 +175,7 @@ class Arm64ManagedRegister : public ManagedRegister { // Return the D register overlapping S register r. static Arm64ManagedRegister FromSRegisterD(SRegister r) { CHECK_NE(r, kNoSRegister); - return FromRegId(r + (kNumberOfCoreRegIds + kNumberOfWRegIds)); + return FromRegId(r + (kNumberOfXRegIds + kNumberOfWRegIds)); } private: @@ -186,11 +184,11 @@ class Arm64ManagedRegister : public ManagedRegister { } bool IsStackPointer() const { - return IsCoreRegister() && (id_ == SP); + return IsXRegister() && (id_ == SP); } bool IsZeroRegister() const { - return IsCoreRegister() && (id_ == XZR); + return IsXRegister() && (id_ == XZR); } int RegId() const { diff --git a/compiler/utils/arm64/managed_register_arm64_test.cc b/compiler/utils/arm64/managed_register_arm64_test.cc index f1a5494e35..32c2e624c3 100644 --- a/compiler/utils/arm64/managed_register_arm64_test.cc +++ b/compiler/utils/arm64/managed_register_arm64_test.cc @@ -29,84 +29,84 @@ TEST(Arm64ManagedRegister, NoRegister) { } // X Register test. -TEST(Arm64ManagedRegister, CoreRegister) { - Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); +TEST(Arm64ManagedRegister, XRegister) { + Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); Arm64ManagedRegister wreg = Arm64ManagedRegister::FromWRegister(W0); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(wreg)); - EXPECT_EQ(X0, reg.AsCoreRegister()); + EXPECT_EQ(X0, reg.AsXRegister()); - reg = Arm64ManagedRegister::FromCoreRegister(X1); + reg = Arm64ManagedRegister::FromXRegister(X1); wreg = Arm64ManagedRegister::FromWRegister(W1); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(wreg)); - EXPECT_EQ(X1, reg.AsCoreRegister()); + EXPECT_EQ(X1, reg.AsXRegister()); - reg = Arm64ManagedRegister::FromCoreRegister(X7); + reg = Arm64ManagedRegister::FromXRegister(X7); wreg = Arm64ManagedRegister::FromWRegister(W7); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(wreg)); - EXPECT_EQ(X7, reg.AsCoreRegister()); + EXPECT_EQ(X7, reg.AsXRegister()); - reg = Arm64ManagedRegister::FromCoreRegister(X15); + reg = Arm64ManagedRegister::FromXRegister(X15); wreg = Arm64ManagedRegister::FromWRegister(W15); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(wreg)); - EXPECT_EQ(X15, reg.AsCoreRegister()); + EXPECT_EQ(X15, reg.AsXRegister()); - reg = Arm64ManagedRegister::FromCoreRegister(X19); + reg = Arm64ManagedRegister::FromXRegister(X19); wreg = Arm64ManagedRegister::FromWRegister(W19); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(wreg)); - EXPECT_EQ(X19, reg.AsCoreRegister()); + EXPECT_EQ(X19, reg.AsXRegister()); - reg = Arm64ManagedRegister::FromCoreRegister(X16); + reg = Arm64ManagedRegister::FromXRegister(X16); wreg = Arm64ManagedRegister::FromWRegister(W16); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(wreg)); - EXPECT_EQ(IP0, reg.AsCoreRegister()); + EXPECT_EQ(IP0, reg.AsXRegister()); - reg = Arm64ManagedRegister::FromCoreRegister(SP); + reg = Arm64ManagedRegister::FromXRegister(SP); wreg = Arm64ManagedRegister::FromWRegister(WZR); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(reg.IsCoreRegister()); + EXPECT_TRUE(reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(!reg.Overlaps(wreg)); - EXPECT_EQ(SP, reg.AsCoreRegister()); + EXPECT_EQ(SP, reg.AsXRegister()); } // W register test. TEST(Arm64ManagedRegister, WRegister) { Arm64ManagedRegister reg = Arm64ManagedRegister::FromWRegister(W0); - Arm64ManagedRegister xreg = Arm64ManagedRegister::FromCoreRegister(X0); + Arm64ManagedRegister xreg = Arm64ManagedRegister::FromXRegister(X0); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); @@ -114,9 +114,9 @@ TEST(Arm64ManagedRegister, WRegister) { EXPECT_EQ(W0, reg.AsWRegister()); reg = Arm64ManagedRegister::FromWRegister(W5); - xreg = Arm64ManagedRegister::FromCoreRegister(X5); + xreg = Arm64ManagedRegister::FromXRegister(X5); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); @@ -124,9 +124,9 @@ TEST(Arm64ManagedRegister, WRegister) { EXPECT_EQ(W5, reg.AsWRegister()); reg = Arm64ManagedRegister::FromWRegister(W6); - xreg = Arm64ManagedRegister::FromCoreRegister(X6); + xreg = Arm64ManagedRegister::FromXRegister(X6); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); @@ -134,9 +134,9 @@ TEST(Arm64ManagedRegister, WRegister) { EXPECT_EQ(W6, reg.AsWRegister()); reg = Arm64ManagedRegister::FromWRegister(W18); - xreg = Arm64ManagedRegister::FromCoreRegister(X18); + xreg = Arm64ManagedRegister::FromXRegister(X18); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); @@ -144,9 +144,9 @@ TEST(Arm64ManagedRegister, WRegister) { EXPECT_EQ(W18, reg.AsWRegister()); reg = Arm64ManagedRegister::FromWRegister(W29); - xreg = Arm64ManagedRegister::FromCoreRegister(FP); + xreg = Arm64ManagedRegister::FromXRegister(FP); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); @@ -154,9 +154,9 @@ TEST(Arm64ManagedRegister, WRegister) { EXPECT_EQ(W29, reg.AsWRegister()); reg = Arm64ManagedRegister::FromWRegister(WZR); - xreg = Arm64ManagedRegister::FromCoreRegister(SP); + xreg = Arm64ManagedRegister::FromXRegister(SP); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(reg.IsWRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); @@ -168,49 +168,49 @@ TEST(Arm64ManagedRegister, DRegister) { Arm64ManagedRegister reg = Arm64ManagedRegister::FromDRegister(D0); Arm64ManagedRegister sreg = Arm64ManagedRegister::FromSRegister(S0); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(sreg)); EXPECT_EQ(D0, reg.AsDRegister()); - EXPECT_EQ(S0, reg.AsOverlappingDRegisterLow()); + EXPECT_EQ(S0, reg.AsOverlappingSRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D0))); reg = Arm64ManagedRegister::FromDRegister(D1); sreg = Arm64ManagedRegister::FromSRegister(S1); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(sreg)); EXPECT_EQ(D1, reg.AsDRegister()); - EXPECT_EQ(S1, reg.AsOverlappingDRegisterLow()); + EXPECT_EQ(S1, reg.AsOverlappingSRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D1))); reg = Arm64ManagedRegister::FromDRegister(D20); sreg = Arm64ManagedRegister::FromSRegister(S20); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(sreg)); EXPECT_EQ(D20, reg.AsDRegister()); - EXPECT_EQ(S20, reg.AsOverlappingDRegisterLow()); + EXPECT_EQ(S20, reg.AsOverlappingSRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D20))); reg = Arm64ManagedRegister::FromDRegister(D31); sreg = Arm64ManagedRegister::FromSRegister(S31); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsDRegister()); EXPECT_TRUE(!reg.IsSRegister()); EXPECT_TRUE(reg.Overlaps(sreg)); EXPECT_EQ(D31, reg.AsDRegister()); - EXPECT_EQ(S31, reg.AsOverlappingDRegisterLow()); + EXPECT_EQ(S31, reg.AsOverlappingSRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromDRegister(D31))); } @@ -219,90 +219,90 @@ TEST(Arm64ManagedRegister, SRegister) { Arm64ManagedRegister reg = Arm64ManagedRegister::FromSRegister(S0); Arm64ManagedRegister dreg = Arm64ManagedRegister::FromDRegister(D0); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsSRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(reg.Overlaps(dreg)); EXPECT_EQ(S0, reg.AsSRegister()); - EXPECT_EQ(D0, reg.AsOverlappingSRegisterD()); + EXPECT_EQ(D0, reg.AsOverlappingDRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); reg = Arm64ManagedRegister::FromSRegister(S5); dreg = Arm64ManagedRegister::FromDRegister(D5); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsSRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(reg.Overlaps(dreg)); EXPECT_EQ(S5, reg.AsSRegister()); - EXPECT_EQ(D5, reg.AsOverlappingSRegisterD()); + EXPECT_EQ(D5, reg.AsOverlappingDRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S5))); reg = Arm64ManagedRegister::FromSRegister(S7); dreg = Arm64ManagedRegister::FromDRegister(D7); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsSRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(reg.Overlaps(dreg)); EXPECT_EQ(S7, reg.AsSRegister()); - EXPECT_EQ(D7, reg.AsOverlappingSRegisterD()); + EXPECT_EQ(D7, reg.AsOverlappingDRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S7))); reg = Arm64ManagedRegister::FromSRegister(S31); dreg = Arm64ManagedRegister::FromDRegister(D31); EXPECT_TRUE(!reg.IsNoRegister()); - EXPECT_TRUE(!reg.IsCoreRegister()); + EXPECT_TRUE(!reg.IsXRegister()); EXPECT_TRUE(!reg.IsWRegister()); EXPECT_TRUE(reg.IsSRegister()); EXPECT_TRUE(!reg.IsDRegister()); EXPECT_TRUE(reg.Overlaps(dreg)); EXPECT_EQ(S31, reg.AsSRegister()); - EXPECT_EQ(D31, reg.AsOverlappingSRegisterD()); + EXPECT_EQ(D31, reg.AsOverlappingDRegister()); EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S31))); } TEST(Arm64ManagedRegister, Equals) { ManagedRegister no_reg = ManagedRegister::NoRegister(); EXPECT_TRUE(no_reg.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromDRegister(D0))); EXPECT_TRUE(!no_reg.Equals(Arm64ManagedRegister::FromSRegister(S0))); - Arm64ManagedRegister reg_X0 = Arm64ManagedRegister::FromCoreRegister(X0); + Arm64ManagedRegister reg_X0 = Arm64ManagedRegister::FromXRegister(X0); EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(reg_X0.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(reg_X0.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg_X0.Equals(Arm64ManagedRegister::FromDRegister(D0))); - Arm64ManagedRegister reg_X1 = Arm64ManagedRegister::FromCoreRegister(X1); + Arm64ManagedRegister reg_X1 = Arm64ManagedRegister::FromXRegister(X1); EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(reg_X1.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(reg_X1.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D0))); EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromDRegister(D1))); EXPECT_TRUE(!reg_X1.Equals(Arm64ManagedRegister::FromSRegister(S1))); - Arm64ManagedRegister reg_SP = Arm64ManagedRegister::FromCoreRegister(SP); + Arm64ManagedRegister reg_SP = Arm64ManagedRegister::FromXRegister(SP); EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromCoreRegister(XZR))); + EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromXRegister(XZR))); EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg_SP.Equals(Arm64ManagedRegister::FromDRegister(D0))); Arm64ManagedRegister reg_W8 = Arm64ManagedRegister::FromWRegister(W8); EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromCoreRegister(X8))); + EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromXRegister(X8))); EXPECT_TRUE(reg_W8.Equals(Arm64ManagedRegister::FromWRegister(W8))); EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromDRegister(D0))); EXPECT_TRUE(!reg_W8.Equals(Arm64ManagedRegister::FromSRegister(S0))); @@ -311,8 +311,8 @@ TEST(Arm64ManagedRegister, Equals) { Arm64ManagedRegister reg_W12 = Arm64ManagedRegister::FromWRegister(W12); EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromCoreRegister(X8))); + EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromXRegister(X8))); EXPECT_TRUE(reg_W12.Equals(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromDRegister(D0))); EXPECT_TRUE(!reg_W12.Equals(Arm64ManagedRegister::FromSRegister(S0))); @@ -321,8 +321,8 @@ TEST(Arm64ManagedRegister, Equals) { Arm64ManagedRegister reg_S0 = Arm64ManagedRegister::FromSRegister(S0); EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg_S0.Equals(Arm64ManagedRegister::FromSRegister(S1))); @@ -331,8 +331,8 @@ TEST(Arm64ManagedRegister, Equals) { Arm64ManagedRegister reg_S1 = Arm64ManagedRegister::FromSRegister(S1); EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(!reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(reg_S1.Equals(Arm64ManagedRegister::FromSRegister(S1))); @@ -341,8 +341,8 @@ TEST(Arm64ManagedRegister, Equals) { Arm64ManagedRegister reg_S31 = Arm64ManagedRegister::FromSRegister(S31); EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(!reg_S31.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(reg_S31.Equals(Arm64ManagedRegister::FromSRegister(S31))); @@ -351,7 +351,7 @@ TEST(Arm64ManagedRegister, Equals) { Arm64ManagedRegister reg_D0 = Arm64ManagedRegister::FromDRegister(D0); EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); + EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromXRegister(X0))); EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg_D0.Equals(Arm64ManagedRegister::FromSRegister(S0))); @@ -361,8 +361,8 @@ TEST(Arm64ManagedRegister, Equals) { Arm64ManagedRegister reg_D15 = Arm64ManagedRegister::FromDRegister(D15); EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::NoRegister())); - EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromCoreRegister(X1))); + EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromXRegister(X1))); EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg_D15.Equals(Arm64ManagedRegister::FromSRegister(S31))); @@ -372,17 +372,17 @@ TEST(Arm64ManagedRegister, Equals) { } TEST(Arm64ManagedRegister, Overlaps) { - Arm64ManagedRegister reg = Arm64ManagedRegister::FromCoreRegister(X0); + Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); Arm64ManagedRegister reg_o = Arm64ManagedRegister::FromWRegister(W0); - EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X0))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP))); + EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromXRegister(X0))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); - EXPECT_EQ(X0, reg_o.AsOverlappingWRegisterCore()); - EXPECT_EQ(W0, reg.AsOverlappingCoreRegisterLow()); + EXPECT_EQ(X0, reg_o.AsOverlappingXRegister()); + EXPECT_EQ(W0, reg.AsOverlappingWRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -394,17 +394,17 @@ TEST(Arm64ManagedRegister, Overlaps) { EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); - reg = Arm64ManagedRegister::FromCoreRegister(X10); + reg = Arm64ManagedRegister::FromXRegister(X10); reg_o = Arm64ManagedRegister::FromWRegister(W10); - EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X10))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP))); + EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromXRegister(X10))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W10))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); - EXPECT_EQ(X10, reg_o.AsOverlappingWRegisterCore()); - EXPECT_EQ(W10, reg.AsOverlappingCoreRegisterLow()); + EXPECT_EQ(X10, reg_o.AsOverlappingXRegister()); + EXPECT_EQ(W10, reg.AsOverlappingWRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -416,17 +416,17 @@ TEST(Arm64ManagedRegister, Overlaps) { EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); - reg = Arm64ManagedRegister::FromCoreRegister(IP1); + reg = Arm64ManagedRegister::FromXRegister(IP1); reg_o = Arm64ManagedRegister::FromWRegister(W17); - EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X17))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP))); + EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromXRegister(X17))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W17))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); - EXPECT_EQ(X17, reg_o.AsOverlappingWRegisterCore()); - EXPECT_EQ(W17, reg.AsOverlappingCoreRegisterLow()); + EXPECT_EQ(X17, reg_o.AsOverlappingXRegister()); + EXPECT_EQ(W17, reg.AsOverlappingWRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -438,15 +438,15 @@ TEST(Arm64ManagedRegister, Overlaps) { EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); - reg = Arm64ManagedRegister::FromCoreRegister(XZR); + reg = Arm64ManagedRegister::FromXRegister(XZR); reg_o = Arm64ManagedRegister::FromWRegister(WZR); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(SP))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(SP))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W19))); - EXPECT_NE(SP, reg_o.AsOverlappingWRegisterCore()); - EXPECT_EQ(XZR, reg_o.AsOverlappingWRegisterCore()); + EXPECT_NE(SP, reg_o.AsOverlappingXRegister()); + EXPECT_EQ(XZR, reg_o.AsOverlappingXRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -458,10 +458,10 @@ TEST(Arm64ManagedRegister, Overlaps) { EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D7))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); - reg = Arm64ManagedRegister::FromCoreRegister(SP); + reg = Arm64ManagedRegister::FromXRegister(SP); reg_o = Arm64ManagedRegister::FromWRegister(WZR); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); @@ -477,15 +477,15 @@ TEST(Arm64ManagedRegister, Overlaps) { EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); reg = Arm64ManagedRegister::FromWRegister(W1); - reg_o = Arm64ManagedRegister::FromCoreRegister(X1); + reg_o = Arm64ManagedRegister::FromXRegister(X1); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); - EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15))); + EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30))); - EXPECT_EQ(W1, reg_o.AsOverlappingCoreRegisterLow()); - EXPECT_EQ(X1, reg.AsOverlappingWRegisterCore()); + EXPECT_EQ(W1, reg_o.AsOverlappingWRegister()); + EXPECT_EQ(X1, reg.AsOverlappingXRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -498,15 +498,15 @@ TEST(Arm64ManagedRegister, Overlaps) { EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromDRegister(D15))); reg = Arm64ManagedRegister::FromWRegister(W21); - reg_o = Arm64ManagedRegister::FromCoreRegister(X21); + reg_o = Arm64ManagedRegister::FromXRegister(X21); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromWRegister(W21))); - EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X21))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15))); + EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromXRegister(X21))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30))); - EXPECT_EQ(W21, reg_o.AsOverlappingCoreRegisterLow()); - EXPECT_EQ(X21, reg.AsOverlappingWRegisterCore()); + EXPECT_EQ(W21, reg_o.AsOverlappingWRegister()); + EXPECT_EQ(X21, reg.AsOverlappingXRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -521,15 +521,15 @@ TEST(Arm64ManagedRegister, Overlaps) { reg = Arm64ManagedRegister::FromSRegister(S1); reg_o = Arm64ManagedRegister::FromDRegister(D1); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X30))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X30))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30))); - EXPECT_EQ(S1, reg_o.AsOverlappingDRegisterLow()); - EXPECT_EQ(D1, reg.AsOverlappingSRegisterD()); + EXPECT_EQ(S1, reg_o.AsOverlappingSRegister()); + EXPECT_EQ(D1, reg.AsOverlappingDRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromSRegister(S1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -544,15 +544,15 @@ TEST(Arm64ManagedRegister, Overlaps) { reg = Arm64ManagedRegister::FromSRegister(S15); reg_o = Arm64ManagedRegister::FromDRegister(D15); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X30))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X30))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30))); - EXPECT_EQ(S15, reg_o.AsOverlappingDRegisterLow()); - EXPECT_EQ(D15, reg.AsOverlappingSRegisterD()); + EXPECT_EQ(S15, reg_o.AsOverlappingSRegister()); + EXPECT_EQ(D15, reg.AsOverlappingDRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); @@ -567,15 +567,15 @@ TEST(Arm64ManagedRegister, Overlaps) { reg = Arm64ManagedRegister::FromDRegister(D15); reg_o = Arm64ManagedRegister::FromSRegister(S15); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X30))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X1))); - EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromCoreRegister(X15))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X30))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X1))); + EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromXRegister(X15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(WZR))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W1))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W12))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromWRegister(W30))); - EXPECT_EQ(S15, reg.AsOverlappingDRegisterLow()); - EXPECT_EQ(D15, reg_o.AsOverlappingSRegisterD()); + EXPECT_EQ(S15, reg.AsOverlappingSRegister()); + EXPECT_EQ(D15, reg_o.AsOverlappingDRegister()); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S0))); EXPECT_TRUE(reg.Overlaps(Arm64ManagedRegister::FromSRegister(S15))); EXPECT_TRUE(!reg.Overlaps(Arm64ManagedRegister::FromSRegister(S2))); diff --git a/runtime/arch/arm64/context_arm64.cc b/runtime/arch/arm64/context_arm64.cc index 0614f1a471..6aacda4d96 100644 --- a/runtime/arch/arm64/context_arm64.cc +++ b/runtime/arch/arm64/context_arm64.cc @@ -31,7 +31,7 @@ namespace arm64 { static constexpr uint64_t gZero = 0; void Arm64Context::Reset() { - for (size_t i = 0; i < kNumberOfCoreRegisters; i++) { + for (size_t i = 0; i < kNumberOfXRegisters; i++) { gprs_[i] = nullptr; } for (size_t i = 0; i < kNumberOfDRegisters; i++) { @@ -52,7 +52,7 @@ void Arm64Context::FillCalleeSaves(const StackVisitor& fr) { if (spill_count > 0) { // Lowest number spill is farthest away, walk registers and fill into context. int j = 1; - for (size_t i = 0; i < kNumberOfCoreRegisters; i++) { + for (size_t i = 0; i < kNumberOfXRegisters; i++) { if (((frame_info.CoreSpillMask() >> i) & 1) != 0) { gprs_[i] = fr.CalleeSaveAddress(spill_count - j, frame_info.FrameSizeInBytes()); j++; @@ -74,7 +74,7 @@ void Arm64Context::FillCalleeSaves(const StackVisitor& fr) { } bool Arm64Context::SetGPR(uint32_t reg, uintptr_t value) { - DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); + DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); DCHECK_NE(reg, static_cast<uint32_t>(XZR)); DCHECK_NE(gprs_[reg], &gZero); // Can't overwrite this static value since they are never reset. if (gprs_[reg] != nullptr) { @@ -147,13 +147,13 @@ void Arm64Context::SmashCallerSaves() { extern "C" void art_quick_do_long_jump(uint64_t*, uint64_t*); void Arm64Context::DoLongJump() { - uint64_t gprs[kNumberOfCoreRegisters]; + uint64_t gprs[kNumberOfXRegisters]; uint64_t fprs[kNumberOfDRegisters]; // The long jump routine called below expects to find the value for SP at index 31. DCHECK_EQ(SP, 31); - for (size_t i = 0; i < kNumberOfCoreRegisters; ++i) { + for (size_t i = 0; i < kNumberOfXRegisters; ++i) { gprs[i] = gprs_[i] != nullptr ? *gprs_[i] : Arm64Context::kBadGprBase + i; } for (size_t i = 0; i < kNumberOfDRegisters; ++i) { diff --git a/runtime/arch/arm64/context_arm64.h b/runtime/arch/arm64/context_arm64.h index 1f69869099..7b6aac9d6c 100644 --- a/runtime/arch/arm64/context_arm64.h +++ b/runtime/arch/arm64/context_arm64.h @@ -47,12 +47,12 @@ class Arm64Context : public Context { } uintptr_t* GetGPRAddress(uint32_t reg) OVERRIDE { - DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); + DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); return gprs_[reg]; } bool GetGPR(uint32_t reg, uintptr_t* val) OVERRIDE { - DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); + DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); if (gprs_[reg] == nullptr) { return false; } else { @@ -82,7 +82,7 @@ class Arm64Context : public Context { private: // Pointers to register locations, initialized to NULL or the specific registers below. - uintptr_t* gprs_[kNumberOfCoreRegisters]; + uintptr_t* gprs_[kNumberOfXRegisters]; uint64_t * fprs_[kNumberOfDRegisters]; // Hold values for sp and pc if they are not located within a stack frame. uintptr_t sp_, pc_; diff --git a/runtime/arch/arm64/registers_arm64.cc b/runtime/arch/arm64/registers_arm64.cc index 3ed6effaff..ea4383a8d0 100644 --- a/runtime/arch/arm64/registers_arm64.cc +++ b/runtime/arch/arm64/registers_arm64.cc @@ -35,8 +35,8 @@ static const char* kWRegisterNames[] = { "w30", "wsp", "wzr" }; -std::ostream& operator<<(std::ostream& os, const Register& rhs) { - if (rhs >= X0 && rhs < kNumberOfCoreRegisters) { +std::ostream& operator<<(std::ostream& os, const XRegister& rhs) { + if (rhs >= X0 && rhs < kNumberOfXRegisters) { os << kRegisterNames[rhs]; } else { os << "XRegister[" << static_cast<int>(rhs) << "]"; diff --git a/runtime/arch/arm64/registers_arm64.h b/runtime/arch/arm64/registers_arm64.h index 5bf8242939..51ae184e7e 100644 --- a/runtime/arch/arm64/registers_arm64.h +++ b/runtime/arch/arm64/registers_arm64.h @@ -23,7 +23,7 @@ namespace art { namespace arm64 { // Values for GP XRegisters - 64bit registers. -enum Register { +enum XRegister { X0 = 0, X1 = 1, X2 = 2, @@ -58,7 +58,7 @@ enum Register { SP = 31, // SP and XZR are encoded in instructions using the register XZR = 32, // code `31`, the context deciding which is used. We use a // different enum value to distinguish between the two. - kNumberOfCoreRegisters = 33, + kNumberOfXRegisters = 33, // Aliases. TR = X18, // ART Thread Register - Managed Runtime (Caller Saved Reg) ETR = X21, // ART Thread Register - External Calls (Callee Saved Reg) @@ -68,7 +68,7 @@ enum Register { LR = X30, kNoRegister = -1, }; -std::ostream& operator<<(std::ostream& os, const Register& rhs); +std::ostream& operator<<(std::ostream& os, const XRegister& rhs); // Values for GP WRegisters - 32bit registers. enum WRegister { |