Ensure stack maps are 4 byte aligned.

With the recent move to gcc 4.9, we are hitting alignment
SIGBUS on ARM. The reason is that gcc will optimize two consecutive
32bits loads into one 64bits load, and the instruction (ldrd)
will fail if the data is not aligned.

Also removed the emission of mapping table when a method is optimized.
The information can be found in the StackMap itself.

Change-Id: Icf79406c18a3f4db3c05d52fc2c0dd2e35bf0f8f

1 files changed, 7 insertions, 1 deletions

diff --git a/runtime/stack_map.h b/runtime/stack_map.h
index a58ecab17d..7cc3e57895 100644
--- a/runtime/stack_map.h
+++ b/runtime/stack_map.h
@@ -19,6 +19,7 @@
 
 #include "base/bit_vector.h"
 #include "memory_region.h"
+#include "utils.h"
 
 namespace art {
 
@@ -199,6 +200,11 @@ class StackMap {
        && region_.size() == other.region_.size();
   }
 
+  static size_t ComputeAlignedStackMapSize(size_t stack_mask_size) {
+    // On ARM, the stack maps must be 4-byte aligned.
+    return RoundUp(StackMap::kFixedSize + stack_mask_size, 4);
+  }
+
  private:
   static constexpr int kDexPcOffset = 0;
   static constexpr int kNativePcOffsetOffset = kDexPcOffset + sizeof(uint32_t);
@@ -262,7 +268,7 @@ class CodeInfo {
   }
 
   size_t StackMapSize() const {
-    return StackMap::kFixedSize + GetStackMaskSize();
+    return StackMap::ComputeAlignedStackMapSize(GetStackMaskSize());
   }
 
   DexRegisterMap GetDexRegisterMapOf(StackMap stack_map, uint32_t number_of_dex_registers) {