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| author | Udayan Banerji <udayan.banerji@intel.com> | 2014-07-08 19:59:43 -0700 |
|---|---|---|
| committer | Udayan Banerji <udayan.banerji@intel.com> | 2014-07-08 19:59:43 -0700 |
| commit | 60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43 (patch) | |
| tree | 496acee66205218843ed6bddc300ae3653794e75 /disassembler | |
| parent | cecec712e1e05aab1fe3469077016320b7bf9583 (diff) | |
| download | android_art-60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43.tar.gz android_art-60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43.tar.bz2 android_art-60bfe7b3e8f00f0a8ef3f5d8716adfdf86b71f43.zip | |
X86 Backend support for vectorized float and byte 16x16 operations
Add support for reserving vector registers for the duration of vector loop.
Add support for 16x16 multiplication, shifts, and add reduce.
Changed the vectorization implementation to be able to use the dataflow
elements for SSA recreation and fixed a few implementation details.
Change-Id: I2f358f05f574fc4ab299d9497517b9906f234b98
Signed-off-by: Jean Christophe Beyler <jean.christophe.beyler@intel.com>
Signed-off-by: Olivier Come <olivier.come@intel.com>
Signed-off-by: Udayan Banerji <udayan.banerji@intel.com>
Diffstat (limited to 'disassembler')
| -rw-r--r-- | disassembler/disassembler_x86.cc | 20 |
1 files changed, 17 insertions, 3 deletions
diff --git a/disassembler/disassembler_x86.cc b/disassembler/disassembler_x86.cc index e6cbf05744..80ddbd5809 100644 --- a/disassembler/disassembler_x86.cc +++ b/disassembler/disassembler_x86.cc @@ -426,6 +426,20 @@ DISASSEMBLER_ENTRY(cmp, instr++; if (prefix[2] == 0x66) { switch (*instr) { + case 0x01: + opcode << "phaddw"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; + case 0x02: + opcode << "phaddd"; + prefix[2] = 0; + has_modrm = true; + load = true; + src_reg_file = dst_reg_file = SSE; + break; case 0x40: opcode << "pmulld"; prefix[2] = 0; @@ -449,7 +463,7 @@ DISASSEMBLER_ENTRY(cmp, prefix[2] = 0; has_modrm = true; store = true; - dst_reg_file = SSE; + src_reg_file = SSE; immediate_bytes = 1; break; case 0x16: @@ -457,7 +471,7 @@ DISASSEMBLER_ENTRY(cmp, prefix[2] = 0; has_modrm = true; store = true; - dst_reg_file = SSE; + src_reg_file = SSE; immediate_bytes = 1; break; default: @@ -742,7 +756,7 @@ DISASSEMBLER_ENTRY(cmp, prefix[2] = 0; has_modrm = true; store = true; - src_reg_file = dst_reg_file = SSE; + src_reg_file = SSE; immediate_bytes = 1; } else { opcode << StringPrintf("unknown opcode '0F %02X'", *instr); |