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| author | Serguei Katkov <serguei.i.katkov@intel.com> | 2014-05-19 15:45:42 +0700 |
|---|---|---|
| committer | buzbee <buzbee@google.com> | 2014-05-22 22:25:53 -0700 |
| commit | d293fb40cf1cd23ead34f6002da037cead69cba2 (patch) | |
| tree | 13d4460b5d8ff1fdf05c1b234c655c6266e3fbf8 /compiler | |
| parent | 15e1b7e18bede88986373dcb425389ceb93ee665 (diff) | |
| download | android_art-d293fb40cf1cd23ead34f6002da037cead69cba2.tar.gz android_art-d293fb40cf1cd23ead34f6002da037cead69cba2.tar.bz2 android_art-d293fb40cf1cd23ead34f6002da037cead69cba2.zip | |
x86: For integer ALU operation handle v+=v case
When destination and operand are the same Virtual Register
we should ensure that destination RegLocation is updated after
operand is loaded with LoadValue in physical register.
Change-Id: I59da106471b0c494203af01c99583f51dbc0f9ee
Signed-off-by: Serguei Katkov <serguei.i.katkov@intel.com>
Diffstat (limited to 'compiler')
| -rw-r--r-- | compiler/dex/quick/x86/int_x86.cc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/compiler/dex/quick/x86/int_x86.cc b/compiler/dex/quick/x86/int_x86.cc index b70922c2bf..48bff6e6af 100644 --- a/compiler/dex/quick/x86/int_x86.cc +++ b/compiler/dex/quick/x86/int_x86.cc @@ -2198,6 +2198,10 @@ void X86Mir2Lir::GenArithOpInt(Instruction::Code opcode, RegLocation rl_dest, } } rl_rhs = LoadValue(rl_rhs, kCoreReg); + // It might happen rl_rhs and rl_dest are the same VR + // in this case rl_dest is in reg after LoadValue while + // rl_result is not updated yet, so do this + rl_result = UpdateLocTyped(rl_dest, kCoreReg); if (rl_result.location != kLocPhysReg) { // Okay, we can do this into memory. OpMemReg(op, rl_result, rl_rhs.reg.GetReg()); |