AArch64: Fix the usage of IP0, IP1 as temporary registers

This patch fixes the usage of temporary registers by using VIXL's
UseScratchRegisterScope. For the primitives used by the trampoline
compiler we explicitly exclude IP0, IP1 from the temporary list.

Change-Id: Icf9afbabd93214302891ddd536ce03a9c181463b
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>

1 files changed, 0 insertions, 3 deletions

diff --git a/compiler/trampolines/trampoline_compiler.cc b/compiler/trampolines/trampoline_compiler.cc
index fb909a80f8..d03b99ff5a 100644
--- a/compiler/trampolines/trampoline_compiler.cc
+++ b/compiler/trampolines/trampoline_compiler.cc
@@ -62,18 +62,15 @@ static const std::vector<uint8_t>* CreateTrampoline(EntryPointCallingConvention
 
   switch (abi) {
     case kInterpreterAbi:  // Thread* is first argument (X0) in interpreter ABI.
-      // FIXME IPx used by VIXL - this is unsafe.
       __ JumpTo(Arm64ManagedRegister::FromCoreRegister(X0), Offset(offset.Int32Value()),
           Arm64ManagedRegister::FromCoreRegister(IP1));
 
       break;
     case kJniAbi:  // Load via Thread* held in JNIEnv* in first argument (X0).
-
       __ LoadRawPtr(Arm64ManagedRegister::FromCoreRegister(IP1),
                       Arm64ManagedRegister::FromCoreRegister(X0),
                       Offset(JNIEnvExt::SelfOffset().Int32Value()));
 
-      // FIXME IPx used by VIXL - this is unsafe.
       __ JumpTo(Arm64ManagedRegister::FromCoreRegister(IP1), Offset(offset.Int32Value()),
                 Arm64ManagedRegister::FromCoreRegister(IP0));