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author | Alexandre Rames <alexandre.rames@arm.com> | 2014-10-23 10:03:10 +0100 |
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committer | Nicolas Geoffray <ngeoffray@google.com> | 2014-10-23 13:44:42 +0100 |
commit | 5319defdf502fc4569316473846b83180ec08035 (patch) | |
tree | 909c6b29f065c79c8368a283946947cbb582d1c7 /compiler/optimizing/codegen_test.cc | |
parent | 37a7188810e865a1ee0a7bdc2d01d62c1f1ea49e (diff) | |
download | android_art-5319defdf502fc4569316473846b83180ec08035.tar.gz android_art-5319defdf502fc4569316473846b83180ec08035.tar.bz2 android_art-5319defdf502fc4569316473846b83180ec08035.zip |
ART: optimizing compiler: initial support for ARM64.
The ARM64 port uses VIXL for code generation, to which it defers work
like label binding and branch resolving, register type coherency
checking, and immediate values handling.
Change-Id: I0a44508c0c991f472a63e67b3469cdd878fe1a68
Signed-off-by: Serban Constantinescu <serban.constantinescu@arm.com>
Signed-off-by: Alexandre Rames <alexandre.rames@arm.com>
Diffstat (limited to 'compiler/optimizing/codegen_test.cc')
-rw-r--r-- | compiler/optimizing/codegen_test.cc | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/compiler/optimizing/codegen_test.cc b/compiler/optimizing/codegen_test.cc index 29ad3de6b3..34d8bfeeae 100644 --- a/compiler/optimizing/codegen_test.cc +++ b/compiler/optimizing/codegen_test.cc @@ -18,6 +18,7 @@ #include "builder.h" #include "code_generator_arm.h" +#include "code_generator_arm64.h" #include "code_generator_x86.h" #include "code_generator_x86_64.h" #include "common_compiler_test.h" @@ -93,6 +94,12 @@ static void RunCodeBaseline(HGraph* graph, bool has_result, int32_t expected) { if (kRuntimeISA == kX86_64) { Run(allocator, codegenX86_64, has_result, expected); } + + arm64::CodeGeneratorARM64 codegenARM64(graph); + codegenARM64.CompileBaseline(&allocator, true); + if (kRuntimeISA == kArm64) { + Run(allocator, codegenARM64, has_result, expected); + } } static void RunCodeOptimized(CodeGenerator* codegen, @@ -395,10 +402,16 @@ TEST(CodegenTest, NonMaterializedCondition) { TestCode(data, true, 12); \ } +#if !defined(__aarch64__) MUL_TEST(INT, MulInt); MUL_TEST(LONG, MulLong); +#endif +#if defined(__aarch64__) +TEST(CodegenTest, DISABLED_ReturnMulIntLit8) { +#else TEST(CodegenTest, ReturnMulIntLit8) { +#endif const uint16_t data[] = ONE_REGISTER_CODE_ITEM( Instruction::CONST_4 | 4 << 12 | 0 << 8, Instruction::MUL_INT_LIT8, 3 << 8 | 0, @@ -407,7 +420,11 @@ TEST(CodegenTest, ReturnMulIntLit8) { TestCode(data, true, 12); } +#if defined(__aarch64__) +TEST(CodegenTest, DISABLED_ReturnMulIntLit16) { +#else TEST(CodegenTest, ReturnMulIntLit16) { +#endif const uint16_t data[] = ONE_REGISTER_CODE_ITEM( Instruction::CONST_4 | 4 << 12 | 0 << 8, Instruction::MUL_INT_LIT16, 3, |