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authorMark Mendell <mark.p.mendell@intel.com>2015-01-13 09:20:58 -0500
committerMark Mendell <mark.p.mendell@intel.com>2015-01-15 11:21:37 -0500
commitf85a9ca9859ad843dc03d3a2b600afbaf2e9bbdd (patch)
treea802042fa7a3a8cb820916d558e630596daaa9b4 /compiler/optimizing/code_generator_arm64.h
parent8fccea249b1a6f1469eeea42c2b2cca06ce1c70d (diff)
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[optimizing compiler] Compute live spill size
The current stack frame calculation assumes that each live register to be saved/restored has the word size of the machine. This fails for X86, where a double in an XMM register takes up 8 bytes. Change the calculation to keep track of the number of core registers and number of fp registers to handle this distinction. This is slightly pessimal, as the registers may not be active at the same time, but the only way to handle this would be to allocate both classes of registers simultaneously, or remember all the active intervals, matching them up and compute the size of each safepoint interval. Change-Id: If7860aa319b625c214775347728cdf49a56946eb Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'compiler/optimizing/code_generator_arm64.h')
-rw-r--r--compiler/optimizing/code_generator_arm64.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/compiler/optimizing/code_generator_arm64.h b/compiler/optimizing/code_generator_arm64.h
index e4da07be43..590bc1d778 100644
--- a/compiler/optimizing/code_generator_arm64.h
+++ b/compiler/optimizing/code_generator_arm64.h
@@ -191,6 +191,11 @@ class CodeGeneratorARM64 : public CodeGenerator {
return kArm64WordSize;
}
+ size_t GetFloatingPointSpillSlotSize() const OVERRIDE {
+ // Allocated in D registers, which are word sized.
+ return kArm64WordSize;
+ }
+
uintptr_t GetAddressOf(HBasicBlock* block) const OVERRIDE {
vixl::Label* block_entry_label = GetLabelOf(block);
DCHECK(block_entry_label->IsBound());