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| author | Goran Jakovljevic <Goran.Jakovljevic@imgtec.com> | 2015-04-03 15:45:21 +0200 |
|---|---|---|
| committer | Andreas Gampe <agampe@google.com> | 2015-04-06 15:43:02 -0700 |
| commit | 75c40d419b621342ac834e5b61abcdcd84537063 (patch) | |
| tree | 2066ed8e4c6bad6221d2512132444696bdde89b1 /compiler/jni | |
| parent | 9104503b4053231d518c3e796033ee01f02bcdf1 (diff) | |
| download | android_art-75c40d419b621342ac834e5b61abcdcd84537063.tar.gz android_art-75c40d419b621342ac834e5b61abcdcd84537063.tar.bz2 android_art-75c40d419b621342ac834e5b61abcdcd84537063.zip | |
Fix JNI compiler for mips64
Fix assembly instructions in JNI stub to store the right size. Fix
callee-saves in JNI calling convention to reflect return registers.
Fix pointer size in mips64 assembler.
Change-Id: I4eccd1f56f62fa9119918192ec424e9073398bc7
Diffstat (limited to 'compiler/jni')
| -rw-r--r-- | compiler/jni/quick/mips64/calling_convention_mips64.cc | 7 |
1 files changed, 1 insertions, 6 deletions
diff --git a/compiler/jni/quick/mips64/calling_convention_mips64.cc b/compiler/jni/quick/mips64/calling_convention_mips64.cc index 17325d6d49..d446867d32 100644 --- a/compiler/jni/quick/mips64/calling_convention_mips64.cc +++ b/compiler/jni/quick/mips64/calling_convention_mips64.cc @@ -126,25 +126,20 @@ const ManagedRegisterEntrySpills& Mips64ManagedRuntimeCallingConvention::EntrySp Mips64JniCallingConvention::Mips64JniCallingConvention(bool is_static, bool is_synchronized, const char* shorty) : JniCallingConvention(is_static, is_synchronized, shorty, kFramePointerSize) { - callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S0)); - callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S1)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S2)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S3)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S4)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S5)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S6)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S7)); - callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(GP)); - callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(SP)); callee_save_regs_.push_back(Mips64ManagedRegister::FromGpuRegister(S8)); } uint32_t Mips64JniCallingConvention::CoreSpillMask() const { // Compute spill mask to agree with callee saves initialized in the constructor uint32_t result = 0; - result = 1 << S0 | 1 << S1 | 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | - 1 << S7 | 1 << GP | 1 << SP | 1 << S8; + result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << GP | 1 << S8 | 1 << RA; return result; } |