diff options
| author | Ian Rogers <irogers@google.com> | 2014-03-14 17:43:00 -0700 |
|---|---|---|
| committer | Ian Rogers <irogers@google.com> | 2014-04-01 08:24:16 -0700 |
| commit | dd7624d2b9e599d57762d12031b10b89defc9807 (patch) | |
| tree | c972296737f992a84b1552561f823991d28403f0 /compiler/dex/quick/x86/codegen_x86.h | |
| parent | 8464a64a50190c06e95015a932eda9511fa6473d (diff) | |
| download | android_art-dd7624d2b9e599d57762d12031b10b89defc9807.tar.gz android_art-dd7624d2b9e599d57762d12031b10b89defc9807.tar.bz2 android_art-dd7624d2b9e599d57762d12031b10b89defc9807.zip | |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
Diffstat (limited to 'compiler/dex/quick/x86/codegen_x86.h')
| -rw-r--r-- | compiler/dex/quick/x86/codegen_x86.h | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/compiler/dex/quick/x86/codegen_x86.h b/compiler/dex/quick/x86/codegen_x86.h index 6d427e7bcf..56b64ddba4 100644 --- a/compiler/dex/quick/x86/codegen_x86.h +++ b/compiler/dex/quick/x86/codegen_x86.h @@ -30,7 +30,7 @@ class X86Mir2Lir : public Mir2Lir { bool SmallLiteralDivRem(Instruction::Code dalvik_opcode, bool is_div, RegLocation rl_src, RegLocation rl_dest, int lit); LIR* CheckSuspendUsingLoad() OVERRIDE; - RegStorage LoadHelper(ThreadOffset offset); + RegStorage LoadHelper(ThreadOffset<4> offset); LIR* LoadBaseDisp(RegStorage r_base, int displacement, RegStorage r_dest, OpSize size, int s_reg); LIR* LoadBaseDispWide(RegStorage r_base, int displacement, RegStorage r_dest, int s_reg); @@ -245,14 +245,14 @@ class X86Mir2Lir : public Mir2Lir { LIR* OpRegRegImm(OpKind op, RegStorage r_dest, RegStorage r_src1, int value); LIR* OpRegRegReg(OpKind op, RegStorage r_dest, RegStorage r_src1, RegStorage r_src2); LIR* OpTestSuspend(LIR* target); - LIR* OpThreadMem(OpKind op, ThreadOffset thread_offset); + LIR* OpThreadMem(OpKind op, ThreadOffset<4> thread_offset); LIR* OpVldm(RegStorage r_base, int count); LIR* OpVstm(RegStorage r_base, int count); void OpLea(RegStorage r_base, RegStorage reg1, RegStorage reg2, int scale, int offset); void OpRegCopyWide(RegStorage dest, RegStorage src); - void OpTlsCmp(ThreadOffset offset, int val); + void OpTlsCmp(ThreadOffset<4> offset, int val); - void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset thread_offset); + void OpRegThreadMem(OpKind op, int r_dest, ThreadOffset<4> thread_offset); void SpillCoreRegs(); void UnSpillCoreRegs(); static const X86EncodingMap EncodingMap[kX86Last]; |