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| author | Ian Rogers <irogers@google.com> | 2014-03-14 17:43:00 -0700 |
|---|---|---|
| committer | Ian Rogers <irogers@google.com> | 2014-04-01 08:24:16 -0700 |
| commit | dd7624d2b9e599d57762d12031b10b89defc9807 (patch) | |
| tree | c972296737f992a84b1552561f823991d28403f0 /compiler/dex/quick/mips/target_mips.cc | |
| parent | 8464a64a50190c06e95015a932eda9511fa6473d (diff) | |
| download | android_art-dd7624d2b9e599d57762d12031b10b89defc9807.tar.gz android_art-dd7624d2b9e599d57762d12031b10b89defc9807.tar.bz2 android_art-dd7624d2b9e599d57762d12031b10b89defc9807.zip | |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
Diffstat (limited to 'compiler/dex/quick/mips/target_mips.cc')
| -rw-r--r-- | compiler/dex/quick/mips/target_mips.cc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/dex/quick/mips/target_mips.cc b/compiler/dex/quick/mips/target_mips.cc index 67a44fa74d..1fe2beadc4 100644 --- a/compiler/dex/quick/mips/target_mips.cc +++ b/compiler/dex/quick/mips/target_mips.cc @@ -514,14 +514,14 @@ void MipsMir2Lir::FreeRegLocTemps(RegLocation rl_keep, RegLocation rl_free) { * ensure that all branch instructions can be restarted if * there is a trap in the shadow. Allocate a temp register. */ -RegStorage MipsMir2Lir::LoadHelper(ThreadOffset offset) { +RegStorage MipsMir2Lir::LoadHelper(ThreadOffset<4> offset) { LoadWordDisp(rs_rMIPS_SELF, offset.Int32Value(), rs_rT9); return rs_rT9; } LIR* MipsMir2Lir::CheckSuspendUsingLoad() { RegStorage tmp = AllocTemp(); - LoadWordDisp(rs_rMIPS_SELF, Thread::ThreadSuspendTriggerOffset().Int32Value(), tmp); + LoadWordDisp(rs_rMIPS_SELF, Thread::ThreadSuspendTriggerOffset<4>().Int32Value(), tmp); LIR *inst = LoadWordDisp(tmp, 0, tmp); FreeTemp(tmp); return inst; |