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authorAndreas Gampe <agampe@google.com>2014-07-15 23:02:11 -0700
committerAndreas Gampe <agampe@google.com>2014-07-17 10:02:10 -0700
commit90969af6deb19b1dbe356d62fe68d8f5698d3d8f (patch)
tree6d144bcd219ce718ba9d17240eade0bec51f3400 /compiler/dex/quick/mips/int_mips.cc
parentaab012d6196bd29b3167963ec8acb0b9780672b2 (diff)
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ART: Refactor GenSelect, refactor gen_common accordingly
This adds a GenSelect method meant for selection of constants. The general-purpose GenInstanceof code is refactored to take advantage of this. This cleans up code and squashes a branch-over on ARM64 to a cset. Also add a slow-path for type initialization in GenInstanceof. Change-Id: Ie4494858bb8c26d386cf2e628172b81bba911ae5
Diffstat (limited to 'compiler/dex/quick/mips/int_mips.cc')
-rw-r--r--compiler/dex/quick/mips/int_mips.cc12
1 files changed, 12 insertions, 0 deletions
diff --git a/compiler/dex/quick/mips/int_mips.cc b/compiler/dex/quick/mips/int_mips.cc
index c3a4c1714c..1f8f9ece8d 100644
--- a/compiler/dex/quick/mips/int_mips.cc
+++ b/compiler/dex/quick/mips/int_mips.cc
@@ -215,6 +215,18 @@ void MipsMir2Lir::OpRegCopyWide(RegStorage r_dest, RegStorage r_src) {
}
}
+void MipsMir2Lir::GenSelectConst32(RegStorage left_op, RegStorage right_op, ConditionCode code,
+ int32_t true_val, int32_t false_val, RegStorage rs_dest,
+ int dest_reg_class) {
+ // Implement as a branch-over.
+ // TODO: Conditional move?
+ LoadConstant(rs_dest, false_val); // Favors false.
+ LIR* ne_branchover = OpCmpBranch(code, left_op, right_op, NULL);
+ LoadConstant(rs_dest, true_val);
+ LIR* target_label = NewLIR0(kPseudoTargetLabel);
+ ne_branchover->target = target_label;
+}
+
void MipsMir2Lir::GenSelect(BasicBlock* bb, MIR* mir) {
UNIMPLEMENTED(FATAL) << "Need codegen for select";
}