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| author | Ian Rogers <irogers@google.com> | 2014-03-14 17:43:00 -0700 |
|---|---|---|
| committer | Ian Rogers <irogers@google.com> | 2014-04-01 08:24:16 -0700 |
| commit | dd7624d2b9e599d57762d12031b10b89defc9807 (patch) | |
| tree | c972296737f992a84b1552561f823991d28403f0 /compiler/dex/quick/mips/call_mips.cc | |
| parent | 8464a64a50190c06e95015a932eda9511fa6473d (diff) | |
| download | android_art-dd7624d2b9e599d57762d12031b10b89defc9807.tar.gz android_art-dd7624d2b9e599d57762d12031b10b89defc9807.tar.bz2 android_art-dd7624d2b9e599d57762d12031b10b89defc9807.zip | |
Allow mixing of thread offsets between 32 and 64bit architectures.
Begin a more full implementation x86-64 REX prefixes.
Doesn't implement 64bit thread offset support for the JNI compiler.
Change-Id: If9af2f08a1833c21ddb4b4077f9b03add1a05147
Diffstat (limited to 'compiler/dex/quick/mips/call_mips.cc')
| -rw-r--r-- | compiler/dex/quick/mips/call_mips.cc | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/compiler/dex/quick/mips/call_mips.cc b/compiler/dex/quick/mips/call_mips.cc index 972457aa70..a938478b3d 100644 --- a/compiler/dex/quick/mips/call_mips.cc +++ b/compiler/dex/quick/mips/call_mips.cc @@ -244,7 +244,7 @@ void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) { GenBarrier(); NewLIR0(kMipsCurrPC); // Really a jal to .+8 // Now, fill the branch delay slot with the helper load - RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(pHandleFillArrayData)); + RegStorage r_tgt = LoadHelper(QUICK_ENTRYPOINT_OFFSET(4, pHandleFillArrayData)); GenBarrier(); // Scheduling barrier // Construct BaseLabel and set up table base register @@ -260,7 +260,7 @@ void MipsMir2Lir::GenFillArrayData(DexOffset table_offset, RegLocation rl_src) { } void MipsMir2Lir::GenMoveException(RegLocation rl_dest) { - int ex_offset = Thread::ExceptionOffset().Int32Value(); + int ex_offset = Thread::ExceptionOffset<4>().Int32Value(); RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); RegStorage reset_reg = AllocTemp(); LoadWordDisp(rs_rMIPS_SELF, ex_offset, rl_result.reg); @@ -277,7 +277,7 @@ void MipsMir2Lir::MarkGCCard(RegStorage val_reg, RegStorage tgt_addr_reg) { RegStorage reg_card_base = AllocTemp(); RegStorage reg_card_no = AllocTemp(); LIR* branch_over = OpCmpImmBranch(kCondEq, val_reg, 0, NULL); - LoadWordDisp(rs_rMIPS_SELF, Thread::CardTableOffset().Int32Value(), reg_card_base); + LoadWordDisp(rs_rMIPS_SELF, Thread::CardTableOffset<4>().Int32Value(), reg_card_base); OpRegRegImm(kOpLsr, reg_card_no, tgt_addr_reg, gc::accounting::CardTable::kCardShift); StoreBaseIndexed(reg_card_base, reg_card_no, reg_card_base, 0, kUnsignedByte); LIR* target = NewLIR0(kPseudoTargetLabel); @@ -310,7 +310,7 @@ void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) RegStorage new_sp = AllocTemp(); if (!skip_overflow_check) { /* Load stack limit */ - LoadWordDisp(rs_rMIPS_SELF, Thread::StackEndOffset().Int32Value(), check_reg); + LoadWordDisp(rs_rMIPS_SELF, Thread::StackEndOffset<4>().Int32Value(), check_reg); } /* Spill core callee saves */ SpillCoreRegs(); @@ -331,7 +331,7 @@ void MipsMir2Lir::GenEntrySequence(RegLocation* ArgLocs, RegLocation rl_method) m2l_->LoadWordDisp(rs_rMIPS_SP, 0, rs_rRA); m2l_->OpRegImm(kOpAdd, rs_rMIPS_SP, sp_displace_); m2l_->ClobberCallerSave(); - ThreadOffset func_offset = QUICK_ENTRYPOINT_OFFSET(pThrowStackOverflow); + ThreadOffset<4> func_offset = QUICK_ENTRYPOINT_OFFSET(4, pThrowStackOverflow); RegStorage r_tgt = m2l_->CallHelperSetup(func_offset); // Doesn't clobber LR. m2l_->CallHelper(r_tgt, func_offset, false /* MarkSafepointPC */, false /* UseLink */); } |