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authorSerban Constantinescu <serban.constantinescu@arm.com>2014-07-15 17:44:21 +0100
committerSerban Constantinescu <serban.constantinescu@arm.com>2014-07-28 19:17:30 +0100
commit63999683329612292d534e6be09dbde9480f1250 (patch)
tree4412a387d3fc4313f98138764ce9197f58f9825c /compiler/dex/quick/arm64/codegen_arm64.h
parent3f49507c333b7c8d36620870522a7a1055987ef8 (diff)
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Revert "Revert "Enable Load Store Elimination for ARM and ARM64""
This patch refactors the implementation of the LoadStoreElimination optimisation pass. Please note that this pass was disabled and not functional for any of the backends. The current implementation tracks aliases and handles DalvikRegs as well as Heap memory regions. It has been tested and it is known to optimise out the following: * Load - Load * Store - Load * Store - Store * Load Literals Change-Id: I3aadb12a787164146a95bc314e85fa73ad91e12b
Diffstat (limited to 'compiler/dex/quick/arm64/codegen_arm64.h')
-rw-r--r--compiler/dex/quick/arm64/codegen_arm64.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/compiler/dex/quick/arm64/codegen_arm64.h b/compiler/dex/quick/arm64/codegen_arm64.h
index ac3651942d..fd2f541bfd 100644
--- a/compiler/dex/quick/arm64/codegen_arm64.h
+++ b/compiler/dex/quick/arm64/codegen_arm64.h
@@ -297,6 +297,7 @@ class Arm64Mir2Lir FINAL : public Mir2Lir {
bool WideFPRsAreAliases() OVERRIDE {
return true; // 64b architecture.
}
+ size_t GetInstructionOffset(LIR* lir);
LIR* InvokeTrampoline(OpKind op, RegStorage r_tgt, QuickEntrypointEnum trampoline) OVERRIDE;
@@ -381,6 +382,7 @@ class Arm64Mir2Lir FINAL : public Mir2Lir {
RegLocation GenDivRem(RegLocation rl_dest, RegLocation rl_src1, RegLocation rl_src2,
bool is_div, bool check_zero);
RegLocation GenDivRemLit(RegLocation rl_dest, RegLocation rl_src1, int lit, bool is_div);
+ size_t GetLoadStoreSize(LIR* lir);
};
} // namespace art