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authorAndreas Gampe <agampe@google.com>2014-08-06 20:05:02 +0000
committerGerrit Code Review <noreply-gerritcodereview@google.com>2014-08-06 02:12:31 +0000
commit1b192268f167f603fc372f02f9067f3ce5d82daf (patch)
treef9be17e2b42f5949e8d4f2aa19aab5f8c6d5fa60 /compiler/dex/quick/arm/codegen_arm.h
parente71d59715a2f0adb0aa539639b83b8d410fc679f (diff)
parent48971b3242e5126bcd800cc9c68df64596b43d13 (diff)
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Merge "ART: Generate chained compare-and-branch for short switches"
Diffstat (limited to 'compiler/dex/quick/arm/codegen_arm.h')
-rw-r--r--compiler/dex/quick/arm/codegen_arm.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/compiler/dex/quick/arm/codegen_arm.h b/compiler/dex/quick/arm/codegen_arm.h
index 21322a6f15..072acbeaa7 100644
--- a/compiler/dex/quick/arm/codegen_arm.h
+++ b/compiler/dex/quick/arm/codegen_arm.h
@@ -130,8 +130,8 @@ class ArmMir2Lir FINAL : public Mir2Lir {
int first_bit, int second_bit);
void GenNegDouble(RegLocation rl_dest, RegLocation rl_src);
void GenNegFloat(RegLocation rl_dest, RegLocation rl_src);
- void GenPackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
- void GenSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
+ void GenLargePackedSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
+ void GenLargeSparseSwitch(MIR* mir, DexOffset table_offset, RegLocation rl_src);
// Required for target - single operation generators.
LIR* OpUnconditionalBranch(LIR* target);