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author | Mark Mendell <mark.p.mendell@intel.com> | 2014-04-29 16:55:20 -0400 |
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committer | buzbee <buzbee@google.com> | 2014-05-16 11:04:27 -0700 |
commit | d65c51a556e6649db4e18bd083c8fec37607a442 (patch) | |
tree | 97fcb17ae74a587c6ef756dda6f4b03db5e9950f /compiler/dex/compiler_enums.h | |
parent | 1e97c4a4ab9f17d1394b952882d59d894b1e3c74 (diff) | |
download | android_art-d65c51a556e6649db4e18bd083c8fec37607a442.tar.gz android_art-d65c51a556e6649db4e18bd083c8fec37607a442.tar.bz2 android_art-d65c51a556e6649db4e18bd083c8fec37607a442.zip |
ART: Add support for constant vector literals
Add in some vector instructions. Implement the ConstVector
instruction, which takes 4 words of data and loads it into
an XMM register.
Initially, only the ConstVector MIR opcode is implemented. Others will
be added after this one goes in.
Change-Id: I5c79bc8b7de9030ef1c213fc8b227debc47f6337
Signed-off-by: Mark Mendell <mark.p.mendell@intel.com>
Diffstat (limited to 'compiler/dex/compiler_enums.h')
-rw-r--r-- | compiler/dex/compiler_enums.h | 98 |
1 files changed, 98 insertions, 0 deletions
diff --git a/compiler/dex/compiler_enums.h b/compiler/dex/compiler_enums.h index 05ab8ca3fb..5b4492f48c 100644 --- a/compiler/dex/compiler_enums.h +++ b/compiler/dex/compiler_enums.h @@ -126,6 +126,104 @@ enum ExtendedMIROpcode { kMirOpCheck, kMirOpCheckPart2, kMirOpSelect, + + // Vector opcodes: + // TypeSize is an encoded field giving the element type and the vector size. + // It is encoded as OpSize << 16 | (number of bits in vector) + // + // Destination and source are integers that will be interpreted by the + // backend that supports Vector operations. Backends are permitted to support only + // certain vector register sizes. + // + // At this point, only two operand instructions are supported. Three operand instructions + // could be supported by using a bit in TypeSize and arg[0] where needed. + + // @brief MIR to move constant data to a vector register + // vA: number of bits in register + // vB: destination + // args[0]~args[3]: up to 128 bits of data for initialization + kMirOpConstVector, + + // @brief MIR to move a vectorized register to another + // vA: TypeSize + // vB: destination + // vC: source + kMirOpMoveVector, + + // @brief Packed multiply of units in two vector registers: vB = vB .* vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: source + kMirOpPackedMultiply, + + // @brief Packed addition of units in two vector registers: vB = vB .+ vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: source + kMirOpPackedAddition, + + // @brief Packed subtraction of units in two vector registers: vB = vB .- vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: source + kMirOpPackedSubtract, + + // @brief Packed shift left of units in two vector registers: vB = vB .<< vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: immediate + kMirOpPackedShiftLeft, + + // @brief Packed signed shift right of units in two vector registers: vB = vB .>> vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: immediate + kMirOpPackedSignedShiftRight, + + // @brief Packed unsigned shift right of units in two vector registers: vB = vB .>>> vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: immediate + kMirOpPackedUnsignedShiftRight, + + // @brief Packed bitwise and of units in two vector registers: vB = vB .& vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: source + kMirOpPackedAnd, + + // @brief Packed bitwise or of units in two vector registers: vB = vB .| vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: source + kMirOpPackedOr, + + // @brief Packed bitwise xor of units in two vector registers: vB = vB .^ vC using vA to know the type of the vector. + // vA: TypeSize + // vB: destination and source + // vC: source + kMirOpPackedXor, + + // @brief Reduce a 128-bit packed element into a single VR by taking lower bits + // @details Instruction does a horizontal addition of the packed elements and then adds it to VR + // vA: TypeSize + // vB: destination and source VR (not vector register) + // vC: source (vector register) + kMirOpPackedAddReduce, + + // @brief Extract a packed element into a single VR. + // vA: TypeSize + // vB: destination VR (not vector register) + // vC: source (vector register) + // arg[0]: The index to use for extraction from vector register (which packed element) + kMirOpPackedReduce, + + // @brief Create a vector value, with all TypeSize values equal to vC + // vA: TypeSize + // vB: destination vector register + // vC: source VR (not vector register) + kMirOpPackedSet, + kMirOpLast, }; |