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* Merge changes from topic "av/console-register" into integrationAntonio Niño Díaz2019-04-241-5/+3
|\ | | | | | | | | | | * changes: Console: Remove Arm console unregister on suspend Console: Allow to register multiple times
| * Console: Remove Arm console unregister on suspendAmbroise Vincent2019-04-241-5/+3
| | | | | | | | | | Change-Id: Ie649b3c367a93db057eeaee7e83fa3e43f8c2607 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge changes from topic "k3-sequence-fix" into integrationAntonio Niño Díaz2019-04-242-42/+48
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: ti: k3: drivers: ti_sci: Retry message receive on bad sequence ID ti: k3: drivers: ti_sci: Cleanup sequence ID usage ti: k3: drivers: sec_proxy: Use direction definitions ti: k3: drivers: sec_proxy: Fix printf format specifiers
| * | ti: k3: drivers: ti_sci: Retry message receive on bad sequence IDAndrew F. Davis2019-04-231-12/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we get a sequence ID that does not match what we expect then the we are looking at is not the one we are expecting and so we error out. We can also assume this message is a stale message left in the queue, in this case we can read in the next message and check again for our message. Switch to doing that here. We only retry a set number of times so we don't lock the system if our message is actually lost and will never show up. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I6c8186ccc45e646d3ba9d431f7d4c451dcd70c5c
| * | ti: k3: drivers: ti_sci: Cleanup sequence ID usageAndrew F. Davis2019-04-231-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The sequence ID can be set with a message to identify it when it is responded to in the response queue. We assign each message a number and check for this same number to detect response mismatches. Start this at 0 and increase it by one for each message sent, even ones that do not request or wait for a response as one may still be delivered in some cases and we want to detect this. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I72b4d1ef98bf1c1409d9db9db074af8dfbcd83ea
| * | ti: k3: drivers: sec_proxy: Use direction definitionsAndrew F. Davis2019-04-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | The direction of a thread should be explicitly compared to avoid confusion. Also fixup message wording based on this direction. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ia3cf9413cd23af476bb5d2e6d70bee15234cbd11
| * | ti: k3: drivers: sec_proxy: Fix printf format specifiersAndrew F. Davis2019-04-231-22/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | The ID of a thread is not used outside for printing it out when something goes wrong. The specifier used is also not consistent. Instead of storing the thread ID, store its name and print that. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Id137c2f8dfdd5c599e220193344ece903f80af7b
* | | Merge changes from topic "k3-cleanups" into integrationAntonio Niño Díaz2019-04-244-24/+17
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | * changes: ti: k3: common: Align elements of map region table ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by default ti: k3: common: Remove shared RAM space ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other defines
| * | ti: k3: common: Align elements of map region tableAndrew F. Davis2019-04-191-10/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is only a formatting change but makes it instantly clear how each region is set. This is over 80 chars and the MT_RO are not strictly needed but this section very important to get right so make readability the priority here. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I2432deda05d4502b3478170296b5da43f26ad8e6
| * | ti: k3: common: Enable SEPARATE_CODE_AND_RODATA by defaultAndrew F. Davis2019-04-193-2/+4
| | | | | | | | | | | | | | | | | | | | | This should be more secure and looks a bit cleaner. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Ie5eaf0234b211ba02631cf5eab5faa1402a34461
| * | ti: k3: common: Remove shared RAM spaceAndrew F. Davis2019-04-192-9/+3
| | | | | | | | | | | | | | | | | | | | | We don't use this for anything right now, remove it. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I11505d01834f7ff1fdba46fda0acbb3b56fc9b66
| * | ti: k3: common: Drop _ADDRESS from K3_USART_BASE to match other definesAndrew F. Davis2019-04-193-5/+5
| |/ | | | | | | | | | | | | This makes definitions more consistent, plus helps alignment. Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: I38fcdd76207586613d9934c9dc83d7a347e9e0fc
* | Merge changes from topic "yg/optee" into integrationAntonio Niño Díaz2019-04-238-110/+366
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: stm32mp1: add OP-TEE support stm32mp1: fix TZC400 configuration against non-secure DDR stm32mp1: remove useless define stm32mp: split stm32mp_io_setup function
| * | stm32mp1: add OP-TEE supportYann Gautier2019-04-238-2/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support booting OP-TEE as BL32 boot stage and secure runtime service. OP-TEE executes in internal RAM and uses a secure DDR area to store the pager pagestore. Memory mapping and TZC are configured accordingly prior OP-TEE boot. OP-TEE image is expected in OP-TEE v2 format where a header file describes the effective boot images. This change post processes header file content to get OP-TEE load addresses and set OP-TEE boot arguments. Change-Id: I02ef8b915e4be3e95b27029357d799d70e01cd44 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
| * | stm32mp1: fix TZC400 configuration against non-secure DDRYann Gautier2019-04-231-21/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change disables secure accesses to non-secure DDR which are useless. TF-A already maps non-secure memory with non-secure permissions thanks to the MMU. This change also corrects some inline comments. Change-Id: Id4c20c9ee5c95a666dae6b7446ed80baf2d53fb0 Signed-off-by: Yann Gautier <yann.gautier@st.com> Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com>
| * | stm32mp1: remove useless defineYann Gautier2019-04-231-1/+0
| | | | | | | | | | | | | | | | | | | | | Remove STM32MP_DDR_SPEED_DFLT that is not used in STM32MP1 TF-A code. Change-Id: I780cdc4e93a8a9d997d50f67cfc582acd4a353d6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | stm32mp: split stm32mp_io_setup functionYann Gautier2019-04-231-86/+89
| |/ | | | | | | | | | | | | | | A new static function boot_mmc is created to simplify code maintenance of stm32mp_io_setup. Change-Id: I5c416e567e7e174fb1c2b435925a983c9c55fc40 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* / plat/arm: introduce wrapper functions to setup secure watchdogAditya Angadi2019-04-1715-10/+87
|/ | | | | | | | | | | | | | | The BL1 stage setup code for ARM platforms sets up the SP805 watchdog controller as the secure watchdog. But not all ARM platforms use SP805 as the secure watchdog controller. So introduce two new ARM platform code specific wrapper functions to start and stop the secure watchdog. These functions then replace the calls to SP805 driver in common BL1 setup code. All the ARM platforms implement these wrapper functions by either calling into SP805 driver or the SBSA watchdog driver. Change-Id: I1a9a11b124cf3fac2a84f22ca40acd440a441257 Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* Temporarily disable shared Mbed TLS heap for SGMJohn Tsichritzis2019-04-161-5/+3
| | | | | | | | There is a bug in the shared heap implementation for SGM. Until the bug is solved, the default implementation is used. Change-Id: I010911a3f00ed860f742b14daad1d99b9e7ce711 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge changes from topic "av/tls-heap" into integrationAntonio Niño Díaz2019-04-128-12/+51
|\ | | | | | | | | | | * changes: Mbed TLS: Remove weak heap implementation sgm: Fix bl2 sources
| * Mbed TLS: Remove weak heap implementationAmbroise Vincent2019-04-127-7/+45
| | | | | | | | | | | | | | | | | | | | | | | | The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * sgm: Fix bl2 sourcesAmbroise Vincent2019-04-111-5/+6
| | | | | | | | | | | | | | The weak version of plat_get_mbedtls_heap() was being used. Change-Id: I6da331a098dd1af5bb64729d5b914cfb74b8869e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge changes from topic "pb/tbbr-oid" into integrationAntonio Niño Díaz2019-04-121-12/+0
|\ \ | | | | | | | | | | | | | | | * changes: doc: Clarify cert_create build when USE_TBBR_DEFS=0 plat/sgm: Remove redundant platform_oid.h
| * | plat/sgm: Remove redundant platform_oid.hPaul Beesley2019-04-111-12/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This file is used when building the cert_create tool without using the 'standard' set of Arm OID values as defined in the TBBR specification (see tbbr_oid.h). This configuration is enabled by setting USE_TBBR_DEFS to 0 during build. At the moment this will fail because the header file included by this file was removed in commit bb41eb7a9dc3 ("cert: move platform_oid.h to include/tools_share for all platforms"). For the SGM platform this means that there is no current use for this file. Change-Id: I3c82983ada62330f1ab6be6d6c0cf489adabae7b Signed-off-by: Paul Beesley <paul.beesley@arm.com>
* | Merge changes from topic "renesas-bsp203" into integrationAntonio Niño Díaz2019-04-123-10/+4
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3 rcar_gen3: drivers: Change to restore timer counter value at resume rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2 rcar_gen3: drivers: ddr: Update DDR setting rev.0.35 rcar_gen3: drivers: qos: change subslot cycle rcar_gen3: drivers: board: Add new board revision for H3ULCB rcar_gen3: plat: Change periodic write DQ training option.
| * | rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3Toshiyuki Ogasahara2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: If8918efad0fcbe6f91b66c0c7438406b1d4fb759
| * | rcar_gen3: drivers: Change to restore timer counter value at resumeToshiyuki Ogasahara2019-04-111-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed to save and restore cntpct_el0 using memory mapped register for generic timer when System Suspend and Resume. Reported by: Volodymyr Babchuk <volodymyr_babchuk@epam.com> Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I40fd9f5434c4d52b320cd1d20322b9b8e4e67155
| * | rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2Toshiyuki Ogasahara2019-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Update the revision number in the revision management file. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I239f4d9f58d38515a49fa1a22cece48b59710d15
| * | rcar_gen3: plat: Change periodic write DQ training option.Toshiyuki Ogasahara2019-04-111-1/+1
| |/ | | | | | | | | | | | | | | Periodic write DQ training available as default. Signed-off-by: Toshiyuki Ogasahara <toshiyuki.ogasahara.bo@hitachi.com> Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Change-Id: I649cfe538e4e2c7e19145ce7d1938ce4361b2529
* | Merge "hikey960: Fix race condition between hotplug and idles" into integrationAntonio Niño Díaz2019-04-123-10/+29
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| * hikey960: Fix race condition between hotplug and idlesWei Yu2019-04-103-10/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From the hotplug testing on Hikey960, in some case cores fail to become online in the system. When some cores are hotplugged off, if other cores in the same cluster enter into CPU idle states at the meantime, the cluster will be powered off. This introduces the state machine malfunction in the power controller, thus when hotplug on the core afterwards, it fails to boot up the core because the power controller thinks the cluster is powered on. This patch is to avoid race condition between hotplug and idles by preventing cluster power off when some of cores in the cluster are hotplugged off, if all cores in the same cluster are hotplugged off, the cluster can be powered off. Change-Id: Ib2feeb093357c70409a3536cb4f9da9b504fdcbe Signed-off-by: Wei Yu <yuwei3@hisilicon.com> Signed-off-by: Leo Yan <leo.yan@linaro.org>
* | Merge "Add support for Cortex-A76AE CPU" into integrationAntonio Niño Díaz2019-04-091-0/+1
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| * | Add support for Cortex-A76AE CPUAlexei Fedorov2019-04-081-0/+1
| |/ | | | | | | | | Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* / plat: imx8m: remove deprecated code includeJacky Bai2019-04-082-2/+0
|/ | | | | | | | | The 'drivers/console/aarch64/console.S' is not needed, so remove it from build to fix the build error when 'ERROR_DEPRECATED'set. Change-Id: Id047a355f82fd33298b7e2b49eff289d28eb5b56 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
* Makefile: remove extra include paths in INCLUDESAmbroise Vincent2019-04-0317-28/+28
| | | | | | | | | | Now it is needed to use the full path of the common header files. Commit 09d40e0e0828 ("Sanitise includes across codebase") provides more information. Change-Id: Ifedc79d9f664d208ba565f5736612a3edd94c647 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Console: remove deprecated finish_console_registerAmbroise Vincent2019-04-034-4/+0
| | | | | | | | | | The old version of the macro is deprecated. Commit cc5859ca19ff ("Multi-console: Deprecate the `finish_console_register` macro") provides more details. Change-Id: I3d1cdf6496db7d8e6cfbb5804f508ff46ae7e67e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Remove deprecated plat_crash_console_*Ambroise Vincent2019-04-036-61/+48
| | | | | | | | | | The default implementations are defined in crash_console_helpers.S. The platforms have to define plat_crash_console_*. Implemented placeholders for platforms that were missing helpers. Change-Id: Iea60b6f851956916e421dfd8c34a62d96eb9148e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Merge pull request #1917 from marex/arm/master/v3meagle-v2.0.1Antonio Niño Díaz2019-04-035-2/+94
|\ | | | | rcar_gen3: plat: Add R-Car V3M support
| * rcar_gen3: plat: Add R-Car V3M supportValentine Barshak2019-04-025-2/+94
| | | | | | | | | | | | | | | | | | | | | | Add R-Car V3M support. This is based on the original V3M support patch for Yocto v2.23.1 by Vladimir Barinov. Signed-off-by: Vladimir Barinov <vladimir.barinov@cogentembedded.com> Signed-off-by: Valentine Barshak <valentine.barshak@cogentembedded.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> --- Marek: Update on top of mainline ATF/master
* | meson/gxl: Add tool to create bl31 bootable imagesRemi Pommarel2019-04-021-0/+16
| | | | | | | | | | | | | | | | GXL platforms need to have a specific header at the beginning of bl31 image to be able to boot. This adds a tool to create that and calls it at build time. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
* | meson/gxl: Configure and boot SCPRemi Pommarel2019-04-023-5/+97
| | | | | | | | | | | | | | On Amlogic gxl (s905x) SOC, in order to use SCP, bl31 has to send bl30 and bl301 firmware along with their SHA256 hash over scpi. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
* | meson/gxl: Add support for SHA256 DMA engineRemi Pommarel2019-04-021-2/+4
| | | | | | | | | | | | | | | | | | | | In order to configure and boot SCP, BL31 has to compute and send the SHA-256 of the firmware data via scpi. Luckily Amlogic GXL SOC has a DMA facility that could be used to offload SHA-256 computations. This adds basic support of this hardware SHA-256 engine. Signed-off-by: Remi Pommarel <repk@triplefau.lt>
* | meson/gxl: Initial port of Amlogic Meson S905x (GXL)Antonio Nino Diaz2019-04-0215-0/+1310
|/ | | | | | | | | | | | | | | | | | The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested on a lepotato. Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
* rcar_gen3: plat: Add initial D3 supportMarek Vasut2019-04-028-10/+138
| | | | | | | Add R-Car D3 SoC platform specifics. Driver, PFC, QoS, DDR init code will be added separately. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* rcar_gen3: plat: Print DRAM bank size in MiB if below 1 GiBMarek Vasut2019-04-021-2/+4
| | | | | | | | Print the DRAM bank size in MiB instead of GiB in case the bank size is smaller than 1 GiB. This prevents printing zeroes on systems with small DRAM sizes. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
* Merge pull request #1886 from ambroise-arm/av/static-checksAntonio Niño Díaz2019-04-0112-13/+22
|\ | | | | Fix extra compilation warnings
| * Remove several warnings reported with W=2Ambroise Vincent2019-04-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Improved support for W=2 compilation flag by solving some nested-extern and sign-compare warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed. Change-Id: I06b1923857f2a6a50e93d62d0274915b268cef05 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * Remove several warnings reported with W=1Ambroise Vincent2019-04-0111-12/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Improved support for W=1 compilation flag by solving missing-prototypes and old-style-definition warnings. The libraries are compiling with warnings (which turn into errors with the Werror flag). Outside of libraries, some warnings cannot be fixed without heavy structural changes. Change-Id: I1668cf99123ac4195c2a6a1d48945f7a64c67f16 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge pull request #1913 from marex/arm/master/m3wulcb-v2.0.1Antonio Niño Díaz2019-04-011-0/+6
|\ \ | | | | | | rcar_gen3: plat: Set M3W ULCB DRAM size to 2 GiB
| * | rcar_gen3: plat: Set M3W ULCB DRAM size to 2 GiBMarek Vasut2019-03-271-0/+6
| |/ | | | | | | | | | | The M3W ULCB board has 2 GiB of DRAM, set it so. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
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