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| author | Antonio Niño Díaz <antonio.ninodiaz@arm.com> | 2019-04-12 09:38:03 +0000 |
|---|---|---|
| committer | TrustedFirmware Code Review <review@review.trustedfirmware.org> | 2019-04-12 09:38:03 +0000 |
| commit | 4b9d01d5b2dde5fb3e3608001e8d1b5b4546a48b (patch) | |
| tree | 4965dd9030b6aa087bcae050d5973992fb615fc9 /plat | |
| parent | 2d212479978cb9b1c68acc987e52931b2fe09753 (diff) | |
| parent | b028f2c5ab0451516b6f74f1a784034e7c60bf55 (diff) | |
| download | platform_external_arm-trusted-firmware-4b9d01d5b2dde5fb3e3608001e8d1b5b4546a48b.tar.gz platform_external_arm-trusted-firmware-4b9d01d5b2dde5fb3e3608001e8d1b5b4546a48b.tar.bz2 platform_external_arm-trusted-firmware-4b9d01d5b2dde5fb3e3608001e8d1b5b4546a48b.zip | |
Merge changes from topic "renesas-bsp203" into integration
* changes:
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.3
rcar_gen3: drivers: Change to restore timer counter value at resume
rcar_gen3: drivers: pwrc: Add DBSC4 setting before self-refresh mode
rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.2
rcar_gen3: drivers: ddr: Update DDR setting rev.0.35
rcar_gen3: drivers: qos: change subslot cycle
rcar_gen3: drivers: board: Add new board revision for H3ULCB
rcar_gen3: plat: Change periodic write DQ training option.
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/renesas/rcar/include/rcar_version.h | 2 | ||||
| -rw-r--r-- | plat/renesas/rcar/plat_pm.c | 10 | ||||
| -rw-r--r-- | plat/renesas/rcar/platform.mk | 2 |
3 files changed, 4 insertions, 10 deletions
diff --git a/plat/renesas/rcar/include/rcar_version.h b/plat/renesas/rcar/include/rcar_version.h index e43632407..ff56f9277 100644 --- a/plat/renesas/rcar/include/rcar_version.h +++ b/plat/renesas/rcar/include/rcar_version.h @@ -9,7 +9,7 @@ #include <arch_helpers.h> -#define VERSION_OF_RENESAS "2.0.1" +#define VERSION_OF_RENESAS "2.0.3" #define VERSION_OF_RENESAS_MAXLEN (128) extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN]; diff --git a/plat/renesas/rcar/plat_pm.c b/plat/renesas/rcar/plat_pm.c index f41c172a9..e678da5dc 100644 --- a/plat/renesas/rcar/plat_pm.c +++ b/plat/renesas/rcar/plat_pm.c @@ -1,5 +1,5 @@ /* - * Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved. + * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -35,8 +35,6 @@ #define CLUSTER_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL1]) #define CORE_PWR_STATE(s) ((s)->pwr_domain_state[MPIDR_AFFLVL0]) -uint64_t rcar_stack_generic_timer[5] __attribute__ ((section("data"))); - extern void rcar_pwrc_restore_generic_timer(uint64_t *stack); extern void plat_rcar_gic_driver_init(void); extern void plat_rcar_gic_init(void); @@ -150,11 +148,7 @@ static void rcar_pwr_domain_suspend_finish(const psci_power_state_t if (cluster_type == RCAR_CLUSTER_A53A57) plat_cci_init(); - rcar_pwrc_restore_generic_timer(rcar_stack_generic_timer); - - /* start generic timer */ - write_cntfrq_el0(plat_get_syscnt_freq2()); - mmio_write_32(RCAR_CNTC_BASE + CNTCR_OFF, CNTCR_FCREQ(U(0)) | CNTCR_EN); + rcar_pwrc_restore_timer_state(); rcar_pwrc_setup(); rcar_pwrc_code_copy_to_system_ram(); diff --git a/plat/renesas/rcar/platform.mk b/plat/renesas/rcar/platform.mk index ca5623d68..85cbe0701 100644 --- a/plat/renesas/rcar/platform.mk +++ b/plat/renesas/rcar/platform.mk @@ -265,7 +265,7 @@ $(eval $(call add_define,RCAR_REF_INT)) # Process RCAR_REWT_TRAINING flag ifndef RCAR_REWT_TRAINING -RCAR_REWT_TRAINING := 0 +RCAR_REWT_TRAINING := 1 endif $(eval $(call add_define,RCAR_REWT_TRAINING)) |