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* Standardise header guards across codebaseAntonio Nino Diaz2018-11-08242-732/+746
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1668 from ldts/rcar_gen3/e3_buildSoby Mathew2018-11-072-1/+12
|\ | | | | rcar_gen3: E3 target: fix compilation issues
| * rcar_gen3: E3 target: fix compilation issuesldts2018-11-061-1/+2
| | | | | | | | | | | | Target builds but has not been tested. Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
| * plat: rcar: support plat_crash_console_flushldts2018-11-061-0/+10
| | | | | | | | Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
* | Merge pull request #1670 from antonio-nino-diaz-arm/an/misra-armSoby Mathew2018-11-075-28/+25
|\ \ | | | | | | plat/arm: Fix MISRA defects in common code
| * | plat/arm: Fix MISRA defects in common codeAntonio Nino Diaz2018-11-065-28/+25
| | | | | | | | | | | | | | | Change-Id: I2419416fadfcdf64da8b7690a348007591c4edf3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1666 from pmanish87/mp2/manish_localSoby Mathew2018-11-072-5/+21
|\ \ \ | |/ / |/| | plat/arm: Support direct Linux kernel boot in AArch32
| * | plat/arm: Support direct Linux kernel boot in AArch32Manish Pandey2018-11-052-5/+21
| |/ | | | | | | | | | | | | | | | | | | | | | | This option allows the Trusted Firmware to directly jump to Linux kernel for aarch32 without the need of an intermediate loader such as U-Boot. Similar to AArch64 ARM_LINUX_KERNEL_AS_BL33 only available with RESET_TO_SP_MIN=1 as well as BL33 and DTB are preloaded in memory. Change-Id: I908bc1633696be1caad0ce2f099c34215c8e0633 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | Merge pull request #1661 from hzhuang1/emmc_delaySoby Mathew2018-11-061-0/+2
|\ \ | |/ |/| hikey: add delay after eMMC initialized
| * hikey: add delay after eMMC initializedHaojian Zhuang2018-10-311-0/+2
| | | | | | | | | | | | | | It boots failure on CircuitCo HiKey board. The delay could fix the hang issue. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
* | Merge pull request #1663 from sudeep-holla/scpi_build_fixAntonio Niño Díaz2018-11-021-0/+2
|\ \ | | | | | | plat: juno: fix build for !CSS_USE_SCMI_DRIVER
| * | plat: juno: fix build for !CSS_USE_SCMI_DRIVERSudeep Holla2018-11-011-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CSS_USE_SCMI_DRIVER is not defined or set to 0, we get the following build error. plat/arm/board/juno/juno_topology.c:16:19: error: ‘CSS_SCMI_PAYLOAD_BASE’ undeclared here (not in a function) .scmi_mbx_mem = CSS_SCMI_PAYLOAD_BASE, ^~~~~~~~~~~~~~~~~~~~~ plat/arm/board/juno/juno_topology.c:17:38: error: ‘CSS_SCMI_MHU_DB_REG_OFF’ undeclared here (not in a function) .db_reg_addr = PLAT_CSS_MHU_BASE + CSS_SCMI_MHU_DB_REG_OFF, ^~~~~~~~~~~~~~~~~~~~~~~ CSS_CPU_PWR_STATE_OFF Fix the error in order to get function legacy SCPI support functional. Change-Id: I00cb80db9968aa0be546e33a3a682a2db87719be Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
* | | plat/arm: Fix MISRA defects in dyn configAntonio Nino Diaz2018-11-011-8/+7
| | | | | | | | | | | | | | | Change-Id: Iae6758ca6395560131d1e1a69a1ecfe50ca8bf83 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | plat/arm: Fix types of constants in headersAntonio Nino Diaz2018-11-014-142/+142
| | | | | | | | | | | | | | | Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | context_mgmt: Fix MISRA defectsAntonio Nino Diaz2018-11-017-8/+8
|/ / | | | | | | | | | | | | | | The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1658 from glneo/plat-arm-removeAntonio Niño Díaz2018-11-012-8/+4
|\ \ | | | | | | ti: k3: common: Remove use of ARM platform code
| * | ti: k3: common: Remove use of ARM platform codeAndrew F. Davis2018-10-302-8/+4
| |/ | | | | | | | | | | | | | | | | | | A recent patch[0] has made setting up page tables into generic code, complete the conversion for TI platforms by removing the use of plat_arm_get_mmap() and using the mmap table directly. [0] 0916c38deca4 ("Convert arm_setup_page_tables into a generic helper") Signed-off-by: Andrew F. Davis <afd@ti.com>
* | Merge pull request #1656 from masahir0y/uniphierAntonio Niño Díaz2018-11-014-29/+6
|\ \ | | | | | | uniphier: clean-up and improve SCP handling code
| * | uniphier: revise SCP protocol handshakeDai Okamura2018-10-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the SoC issues a command IRQ to SCP, SCP sets STMTOBEIRQ as ACK. The SoC must wait for it before issuing the next command. This commit makes sure to meet the requirement. Signed-off-by: Dai Okamura <okamura.dai@socionext.com> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | uniphier: terminate boot if SCP_BL2 image is missing in SCP boot modeMasahiro Yamada2018-10-303-29/+0
| | | | | | | | | | | | | | | | | | | | | Skipping SCP_BL2 image is just a temporary workaround. If on-chip SCP needs to work, BL2 should load the SCP_BL2 image. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | Merge pull request #1623 from MISL-EBU-System-SW/a3700-supportAntonio Niño Díaz2018-11-0128-4/+2737
|\ \ \ | | | | | | | | Add support for Armada 3700 and COMPHY porting layer
| * | | plat: marvell: Add support for Armada-37xx SoC platformKonstantin Porotchkin2018-10-3121-1/+2547
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | tools: Move doimage to marvell folder for future add-onsKonstantin Porotchkin2018-10-221-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Move doimage utility from toos/doimage to tools/marvell/doimage. This is done for supporting mode Marvell tools in the future. Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | | mvebu: cp110: introduce COMPHY porting layerGrzegorz Jaszczyk2018-10-187-1/+188
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of COMPHY parameters depends on the hw connection between the SoC and the PHY, which can vary on different boards e.g. due to different wires length. Define the "porting layer" with some defaults parameters. It ease updating static values which needs to be updated due to board differences, which are now grouped in one place. Example porting layer for a8k-db is under: plat/marvell/a8k/a80x0/board/phy-porting-layer.h If for some boards parameters are not defined (missing phy-porting-layer.h), the default values are used (drivers/marvell/comphy/phy-default-porting-layer.h) and the following compilation warning is show: "Using default comphy params - you may need to suit them to your board". The common COMPHY driver code is extracted in order to be shared with future COMPHY driver for A3700 SoC platforms Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | | | Merge pull request #1650 from chandnich/sgiclark-ares-supportAntonio Niño Díaz2018-10-318-4/+193
|\ \ \ \ | | | | | | | | | | Sgiclark ares support
| * | | | plat/arm/sgi: add support for SGI-Clark.Ares platformChandni Cherukuri2018-10-264-0/+102
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SGI-Clark.Ares platform is a variant of the SGI-Clark platform. It has two clusters of four Ares CPUs each. Though very similar to the SGI575 platform, there are subtle differences. HW_CONFIG and TB_FW_CONFIG dts files have been added. Change-Id: I740a33cbd1c3b1f1984cb56243b46ad379bab3e6 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | plat/arm/sgi: add support for SGI-Clark platformChandni Cherukuri2018-10-263-4/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SGI-Clark platform is the next version in the Arm's SGI platform series. One of the primary difference between the SGI-575 platform and the SGI-Clark platform is the MHU version (MHUv2 in case of SGI-Clark). Add the required base support for SGI-Clark platform. Change-Id: If396e5279fdf801d586662dad0b55195e81371e4 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | plat/arm/sgi: disable Ares cpu power down bit in reset handlerChandni Cherukuri2018-10-261-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SGI platforms that include Ares CPUs, the 'CORE_PWRDN_EN' bit of 'CPUPWRCTLR_EL1' register requires an explicit write to clear it to enable hotplug and idle to function correctly. The reset value of the CORE_PWRDN_EN bit is zero but it still requires this explicit clear to zero. This indicates that this could be a model related issue but for now this issue can be fixed be clearing the CORE_PWRDN_EN bit in the platform specific reset handler function. Change-Id: I8b9884ae27a2986d789bfec2e9ae792ef930944e Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | | Merge pull request #1655 from deepan02/deepak-arm/introduce-n1sdpAntonio Niño Díaz2018-10-319-0/+382
|\ \ \ \ \ | | | | | | | | | | | | plat/arm: Introduce the N1SDP.
| * | | | | plat/arm: Introduce the N1SDP.Deepak Pandey2018-10-299-0/+382
| | |_|/ / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the N1SDP (NeoVerse N1 System Development Platform). It is an initial port and additional features are expected to be added later. The port includes only BL31 support as the System Control Processor (SCP) is expected to take the role of primary boatloader Change-Id: Ife17d8215a7bfcc1420204a72205e7ef920d0c10 Signed-off-by: Deepak Pandey <Deepak.Pandey@arm.com>
* | | | | Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2Antonio Niño Díaz2018-10-3118-172/+883
|\ \ \ \ \ | |_|_|_|/ |/| | | | Allwinner/pmic v2
| * | | | allwinner: Use the arisc to turn off ARM coresAndre Przywara2018-10-205-7/+237
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSCI requires a core to turn itself off, which we can't do properly by just executing an algorithm on that very core. As a consequence we just put a core into WFI on CPU_OFF right now. To fix this let's task the "arisc" management processor (an OpenRISC core) with that task of asserting reset and turning off the core's power domain. We use a handcrafted sequence of OpenRISC instructions to achieve this, and hand this data over to the new sunxi_execute_arisc_code() routine. The commented source code for this routine is provided in a separate file, but the ATF code contains the already encoded instructions as data. The H6 uses the same algorithm, but differs in the MMIO addresses, so provide a SoC (family) specific copy of that code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Prepare for executing code on the management processorAndre Przywara2018-10-202-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The more recent Allwinner SoCs contain an OpenRISC management controller (called arisc or CPUS), which shares the bus with the ARM cores, but runs on a separate power domain. This is meant to handle power management with the ARM cores off. There are efforts to run sophisticated firmware on that core (communicating via SCPI with the ARM world), but for now can use it for the rather simple task of helping to turn the ARM cores off. As this cannot be done by ARM code itself (because execution stops at the first of the three required steps), we can offload some instructions to this management processor. This introduces a helper function to hand over a bunch of instructions and triggers execution. We introduce a bakery lock to avoid two cores trying to use that (single) arisc core. The arisc code is expected to put itself into reset after is has finished execution. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: PMIC: AXP803: Delay activation of DC1SW switchAndre Przywara2018-10-201-2/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are reports that activating the DC1SW before certain other regulators leads to the PMIC overheating and consequently shutting down. To avoid this situation, delay the activation of the DC1SW line until the very end, so those other lines are always activated earlier. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: PMIC: AXP803: Setup basic voltage railsAndre Przywara2018-10-201-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on the just introduced PMIC FDT framework, we check the DT for more voltage rails that need to be setup early: - DCDC1 is typically the main board power rail, used for I/O pins, for instance. The PMIC's default is 3.0V, but 3.3V is what most boards use, so this needs to be adjusted as soon as possible. - DCDC5 is supposed to be connected to the DRAM. The AXP has some configurable reset voltage, but some boards get that wrong, so we better set up this here to avoid over- or under-volting. - DLDO1,2,3 and FLDO1 mostly drive some graphics related IP, some boards need this to be up to enable HDMI or the LCD screen, so we get screen output in U-Boot. To get the right setup, but still being flexible, we query the DT for the required voltage and whether that regulator is actually used. That gives us some robust default setup U-Boot is happy with. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Scan AXP803 FDT node to setup initial power railsAndre Przywara2018-10-201-0/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have a pointer to the device tree blob, let's use that to do some initial setup of the PMIC: - We scan the DT for the compatible string to find the PMIC node. - We switch the N_VBUSEN pin if the DT property tells us so. - We scan over all regulator subnodes, and switch DC1SW if there is at least one other node referencing it (judging by the existence of a phandle property in that subnode). This is just the first part of the setup, a follow up patch will setup voltages. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Pass FDT address to sunxi_pmic_setup()Andre Przywara2018-10-204-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Allwinner boards we now use some heuritistics to find a preloaded .dtb file. Pass this address on to the PMIC setup routine, so that it can use the information contained therein to setup some initial power rails. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Find DTB in BL33 imageAndre Przywara2018-10-203-1/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial PMIC setup for the Allwinner platform is quite board specific, and used to be guarded by reading the .dtb stub *name* from the SPL image in the legacy ATF port. This doesn't scale particularly well, and requires constant maintainance. Instead having the actual .dtb available would be much better, as the PMIC setup requirements could be read from there directly. The only available BL33 for Allwinner platforms so far is U-Boot, and fortunately U-Boot comes with the full featured .dtb, appended to the end of the U-Boot image. Introduce some code that scans the beginning of the BL33 image to look for the load address, which is followed by the image size. Adding those two values together gives us the end of the image and thus the .dtb address. Verify that this heuristic is valid by sanitising some values and checking the DTB magic. Print out the DTB address and the model name, if specified in the root node. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: A64: Add AXP803 PMIC support to power off the boardAndre Przywara2018-10-202-0/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Boards with the Allwinner A64 SoC are mostly paired with an AXP803 PMIC, which allows to programmatically power down the board. Use the newly introduced RSB driver to detect and program the PMIC on boot, then later to turn off the main voltage rails when receiving a PSCI SYSTEM_POWER_OFF command. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: H6: Factor out I2C platform setupAndre Przywara2018-10-203-32/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the H6 platform code there is a routine to do the platform initialisation of the R_I2C controller. We will need a very similar setup routine to initialise the RSB controller on the A64. Move this code to sunxi_common.c and generalise it to support all SoCs and also to cover the related RSB bus. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: H5: Implement power down for H5 reference design boardsAndre Przywara2018-10-201-1/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allwinner produces reference board designs, which apparently most board vendors copy from. So every H5 board I checked uses regulators which are controlled by the same PortL GPIO pins to power the ARM CPU cores, the DRAM and the I/O ports. Add a SoC specific power down routine, which turns those regulators off when ATF detects running on an H5 SoC and the rich OS triggers a SYSTEM_POWEROFF PSCI call. NOTE: It sounds very tempting to turn the CPU power off, but this is not working as expected, instead the system is rebooting. Most probably this is due to VCC-SYS also being controlled by the same GPIO line, and turning this off requires an elaborate and not fully understood setup. Apparently not even Allwinner reference code is turning this regulator off. So for now we refrain to pulling down PL8, the power consumption is quite low anyway, so we are as close to poweroff as reasonably possible. Many thanks to Samuel for doing some research on that topic. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Introduce GPIO helper functionAndre Przywara2018-10-202-0/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many boards without a dedicated PMIC contain simple regulators, which can be controlled via GPIO pins. To later allow turning them off easily, introduce a simple function to configure a given pin as a GPIO out pin and set it to the desired level. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Export sunxi_private.hAndre Przywara2018-10-208-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we have a sunxi_private.h header file in the common code directory. This holds the prototypes of various functions we share in *common* code. However we will need some of those in the platform specific code parts as well, and want to introduce new functions shared across the whole platform port. So move the sunxi_private.h file into the common/include directory, so that it becomes visible to all parts of the platform code. Fix up the existing #includes and add missing ones, also add the sunxi_read_soc_id() prototype here. This will be used in follow up patches. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: A64/H5: Add basic and generic shutdown methodAndre Przywara2018-10-201-4/+96
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some boards don't have a PMIC, so they can't easily turn their power off. To cover those boards anyway, let's turn off as many devices and clocks as possible, so that the power consumption is reduced. Then halt the last core, as before. This will later be extended with proper PMIC support for supported boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Pass SoC ID to sunxi_pmic_setup()Andre Przywara2018-10-204-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the BL31 platform setup we read the Allwinner SoC ID to identify the chip and print its name. In addition to that we will need to differentiate the power setup between the SoCs, to pass on the SoC ID to the PMIC setup routine. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Introduce names for SoC IDsAndre Przywara2018-10-202-3/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We will soon make more use of the Allwinner SoC ID, to differentiate the platform setup. Introduce definitions to avoid dealing with magic numbers and make the code more readable. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: H6: Fix SRAM sizeAndre Przywara2018-10-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SRAM in the Allwinner H6 SoC starts at 0x2000, with the last part ending at 0x117fff (although with gaps in between). So SUNXI_SRAM_SIZE should be 0xf8000, not 0x98000. Fix this to map the arisc exception vector area, which we will need shortly. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Disable USE_COHERENT_MEMAndre Przywara2018-10-203-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the documentation, platforms may choose to trade memory footprint for performance (and elegancy) by not providing a separately mapped coherent page. Since a debug build is getting close to the SRAM size limit already, this allows us to save about 3.5KB of BSS and have some room for future enhancements. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Adjust memory mapping to fit into 256MBAndre Przywara2018-10-204-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At the moment we map as much of the DRAM into EL3 as possible, however we actually don't use it. The only exception is the secure DRAM for BL32 (if that is configured). To decrease the memory footprint of ATF, we save on some page tables by reducing the memory mapping to the actually required regions: SRAM, device MMIO, secure DRAM and U-Boot (to be used later). This introduces a non-identity mapping for the DRAM regions. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | | allwinner: Unify platform.mk filesAndre Przywara2018-10-203-97/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the two different platforms we support in the Allwinner port we mostly rely on header files covering the differences. This leads to the platform.mk files in the respective directories to be almost identical. To avoid further divergence and make sure that one platform doesn't break accidentally, let's create a shared allwinner-common.mk file and include that from the platform directory. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-14 21:10:26 +0000