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| author | Chandni Cherukuri <chandni.cherukuri@arm.com> | 2018-08-07 14:52:55 +0530 |
|---|---|---|
| committer | Chandni Cherukuri <chandni.cherukuri@arm.com> | 2018-10-26 12:14:03 +0530 |
| commit | 20a8f7a862fe018ead697f6dee46ee1db03951ad (patch) | |
| tree | 36f458d4e4c17efa7a9d909d6d24a1f7ca9d9630 /plat | |
| parent | 31abc7c45428398a330a3a940fe4dd7efa6c96f2 (diff) | |
| download | platform_external_arm-trusted-firmware-20a8f7a862fe018ead697f6dee46ee1db03951ad.tar.gz platform_external_arm-trusted-firmware-20a8f7a862fe018ead697f6dee46ee1db03951ad.tar.bz2 platform_external_arm-trusted-firmware-20a8f7a862fe018ead697f6dee46ee1db03951ad.zip | |
plat/arm/sgi: disable Ares cpu power down bit in reset handler
On SGI platforms that include Ares CPUs, the 'CORE_PWRDN_EN' bit of
'CPUPWRCTLR_EL1' register requires an explicit write to clear it to
enable hotplug and idle to function correctly.
The reset value of the CORE_PWRDN_EN bit is zero but it still requires
this explicit clear to zero. This indicates that this could be a model
related issue but for now this issue can be fixed be clearing the
CORE_PWRDN_EN bit in the platform specific reset handler function.
Change-Id: I8b9884ae27a2986d789bfec2e9ae792ef930944e
Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/arm/css/sgi/aarch64/sgi_helper.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/plat/arm/css/sgi/aarch64/sgi_helper.S b/plat/arm/css/sgi/aarch64/sgi_helper.S index 27bae43cf..d79f1aa21 100644 --- a/plat/arm/css/sgi/aarch64/sgi_helper.S +++ b/plat/arm/css/sgi/aarch64/sgi_helper.S @@ -8,6 +8,7 @@ #include <asm_macros.S> #include <platform_def.h> #include <cortex_a75.h> +#include <cortex_ares.h> #include <cpu_macros.S> .globl plat_arm_calc_core_pos @@ -58,6 +59,7 @@ endfunc plat_arm_calc_core_pos */ func plat_reset_handler jump_if_cpu_midr CORTEX_A75_MIDR, A75 + jump_if_cpu_midr CORTEX_ARES_MIDR, ARES ret /* ----------------------------------------------------- @@ -70,4 +72,11 @@ A75: msr CORTEX_A75_CPUPWRCTLR_EL1, x0 isb ret + +ARES: + mrs x0, CORTEX_ARES_CPUPWRCTLR_EL1 + bic x0, x0, #CORTEX_ARES_CORE_PWRDN_EN_MASK + msr CORTEX_ARES_CPUPWRCTLR_EL1, x0 + isb + ret endfunc plat_reset_handler |