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* Merge "plat: imx8m: Add caam module init on imx8m" into integrationSandrine Bailleux2019-07-098-11/+86
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| * plat: imx8m: Add caam module init on imx8mJacky Bai2019-07-048-11/+86
| | | | | | | | | | | | | | | | CAAM module must be initialized in secure world before it can be used in non-secure world. Change-Id: I042893667ddef99d8b6fc3902847d516d8591996 Signed-off-by: Jacky Bai <ping.bai@nxp.com>
* | rpi3: Fix compilation error when stack protector is enabledMadhukar Pappireddy2019-07-081-1/+2
| | | | | | | | | | | | | | Include necessary header file to use ARRAY_SIZE() macro Change-Id: I5b7caccd02c14c598b7944cf4f347606c1e7a8e7 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | Merge "uniphier: support console based on multi-console" into integrationSandrine Bailleux2019-07-055-179/+144
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| * | uniphier: support console based on multi-consoleMasahiro Yamada2019-07-055-179/+144
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The legacy console is gone. Re-add the console support based on the multi-console framework. I am still keeping the putc, getc, and flush callbacks in uniphier_console.S to use plat/common/aarch64/crash_console_helpers.S The console registration code already relies on that C environment has been set up. So, I just filled the struct console fields with the callback pointers, then called console_register() directly. I also re-implemented the init function in C to improve the readability. Removing the custom crash console implementation has one disadvantage; we cannot use the crash console on very early crashes because crash_console_helpers.S works only after the console is registered. I can live with this limitation. Tested on my boards, and confirmed this worked like before. Change-Id: Ieab9c849853ff6c525c15ea894a85944f257db59 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* / ti: k3: common: Trap all asynchronous bus errors to EL3Andrew F. Davis2019-07-041-0/+3
|/ | | | | | | | | | These errors are asynchronous and cannot be directly correlated with the exact current running software, so handling them in the same EL is not critical. Handling them in TF-A allows for more platform specific decoding of the implementation defined exception registers Signed-off-by: Andrew F. Davis <afd@ti.com> Change-Id: Iee7a38c9fc9c698fa0ad42dafa598bcbed6a4fda
* Merge "zynqmp: add support for multi console interface" into integrationSandrine Bailleux2019-07-025-15/+25
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| * zynqmp: add support for multi console interfaceAmbroise Vincent2019-07-015-15/+25
| | | | | | | | | | | | | | | | | | | | This patch addds multi console interface for ZynqMP platform Change-Id: I508a61412df2b71d04bca6a1139c8f32cbd7dccd Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Tested-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
* | Merge changes from topic "banned_api_list" into integrationSoby Mathew2019-07-011-2/+2
|\ \ | |/ |/| | | | | | | * changes: Fix the License header template in imx_aipstz.c docs: Add the list of banned/use with caution APIs
| * Fix the License header template in imx_aipstz.cSoby Mathew2019-07-011-2/+2
| | | | | | | | | | Signed-off-by: Soby Mathew <soby.mathew@arm.com> Change-Id: I2281b3c1b8a0f2caa751c746b7835f998183e0af
* | Merge changes from topic "av/console-port" into integrationPaul Beesley2019-06-2837-197/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: qemu: use new console interface in aarch32 warp7: remove old console from makefile Remove MULTI_CONSOLE_API flag and references to it Console: removed legacy console API
| * | qemu: use new console interface in aarch32Ambroise Vincent2019-06-282-6/+5
| | | | | | | | | | | | | | | Change-Id: Iab788e3e7cb2f83144255c4eb830712fd5cb6240 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | warp7: remove old console from makefileAmbroise Vincent2019-06-281-2/+1
| | | | | | | | | | | | | | | Change-Id: I87818b220568cc34838726b32ddf29ee6cf31ed7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Remove MULTI_CONSOLE_API flag and references to itAmbroise Vincent2019-06-2835-189/+0
| |/ | | | | | | | | | | | | The new API becomes the default one. Change-Id: Ic1d602da3dff4f4ebbcc158b885295c902a24fec Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Merge "Tegra: Fix typo in comment" into integrationPaul Beesley2019-06-271-1/+1
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| * | Tegra: Fix typo in commentAndreas Färber2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | initilise -> initialise Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: Ib129e6bd48623b6565b669bc674208893a2f7668
* | | Merge "Tegra: Extend NS address check error output" into integrationPaul Beesley2019-06-271-2/+2
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| * | Tegra: Extend NS address check error outputAndreas Färber2019-06-201-2/+2
| |/ | | | | | | | | | | | | Let bl31_check_ns_address() print the address it doesn't like. Signed-off-by: Andreas Färber <afaerber@suse.de> Change-Id: I29a4fb33c24e9f7464ccd2ea44a4608f5cfe5be6
* | Merge "n1sdp: add code for DDR ECC enablement and BL33 copy to DDR" into ↵Paul Beesley2019-06-2712-6/+266
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| * | n1sdp: add code for DDR ECC enablement and BL33 copy to DDRManoj Kumar2019-06-2612-6/+266
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | N1SDP platform supports RDIMMs with ECC capability. To use the ECC capability, the entire DDR memory space has to be zeroed out before enabling the ECC bits in DMC620. Zeroing out several gigabytes of memory from SCP is quite time consuming so functions are added that zeros out the DDR memory from application processor which is much faster compared to SCP. BL33 binary cannot be copied to DDR memory before enabling ECC so this is also done by TF-A from IOFPGA-DDR3 memory to main DDR4 memory after ECC is enabled. Original PLAT_PHY_ADDR_SPACE_SIZE was limited to 36-bits with which the entire DDR space cannot be accessed as DRAM2 starts in base 0x8080000000. So these macros are redefined for all ARM platforms. Change-Id: If09524fb65b421b7a368b1b9fc52c49f2ddb7846 Signed-off-by: Manoj Kumar <manoj.kumar3@arm.com>
* | Merge changes from topic "pull-out-drivers" into integrationPaul Beesley2019-06-268-28/+264
|\ \ | | | | | | | | | | | | | | | | | | | | | * changes: intel: Add ncore ccu driver intel: Fix watchdog driver structure intel: Fix qspi driver write config intel: Pull out common drivers into platform common
| * | intel: Add ncore ccu driverHadi Asyrafi2019-06-262-0/+234
| | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0544315986ee28b23157fdfec3fe5aebae6b860f
| * | intel: Fix watchdog driver structureHadi Asyrafi2019-06-262-8/+2
| | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I0ffccca7ea83bff35c9f149d7054cd610a59ec01
| * | intel: Fix qspi driver write configHadi Asyrafi2019-06-262-12/+19
| | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: I5241ed97697b0280b590b47b9173d102d23f305a
| * | intel: Pull out common drivers into platform commonHadi Asyrafi2019-06-266-8/+9
| | | | | | | | | | | | | | | Signed-off-by: Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com> Change-Id: Ib79e2c6fe6e66dec5004701133ad6a5f4c78f2fa
* | | rcar_gen3: drivers: pfc: Move PFC drivers out of stagingMarek Vasut2019-06-221-1/+1
| |/ |/| | | | | | | | | | | Now that PFC drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: Ie594b53558c2bfb8e5d88e5b0354752c17a2487e
* | Merge changes from topic "yg/clk_syscfg_dt" into integrationJohn Tsichritzis2019-06-199-65/+328
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: fdts: stm32mp1: realign device tree files with internal devs stm32mp1: increase device tree size to 20kB stm32mp1: make dt_get_stdout_node_offset() static stm32mp1: use unsigned values for SDMMC defines stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCES stm32mp1: update doc for U-Boot compilation stm32mp1: add general SYSCFG management stm32mp1: move stm32_get_gpio_bank_clock() to private file clk: stm32mp1: correctly handle Clock Spreading Generator clk: stm32mp1: use defines for mask values in stm32mp1_clk_sel array clk: stm32mp1: move oscillator functions to generic file arch: add some defines for generic timer registers
| * stm32mp1: increase device tree size to 20kBYann Gautier2019-06-171-1/+1
| | | | | | | | | | Change-Id: Idee966b6434aa038e54b6e7176749a7b65bdbe84 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: make dt_get_stdout_node_offset() staticYann Gautier2019-06-172-44/+46
| | | | | | | | | | | | | | | | Do not export function dt_get_stdout_node_offset() that is used only inside stm32mp_dt.c source file. Change-Id: I9dd3dbfab21d42ed81c68723e71fe5a7586dce93 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: use unsigned values for SDMMC definesYann Gautier2019-06-171-5/+5
| | | | | | | | | | | | | | | | Correct SDMMC macros to define unsigned values as expected by the driver implementation. Change-Id: Ib009f3df2cf26a9759d129eb571a27b2564770ce Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: remove useless LIBFDT_SRCS from PLAT_BL_COMMON_SOURCESYann Gautier2019-06-171-2/+1
| | | | | | | | | | | | | | | | Remove inclusion of libfdt source files in source file list since these are already included from generic libfdt.mk makefile. Change-Id: If42624557c4d88ca85d70f83b1b08c58f50afe72 Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: add general SYSCFG managementYann Gautier2019-06-177-1/+262
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The system configuration controller is mainly used to manage the compensation cell and other IOs and system related settings. The SYSCFG driver is in charge of configuring masters on the interconnect, IO compensation, low voltage boards, or pull-ups for boot pins. All other configurations should be handled in Linux drivers requiring it. Device tree files are also updated to manage vdd-supply regulator. Change-Id: I10fb513761a7d1f2b7afedca9c723ad9d1bccf42 Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * stm32mp1: move stm32_get_gpio_bank_clock() to private fileYann Gautier2019-06-172-11/+13
| | | | | | | | | | | | | | | | | | GPIOx clocks are specific to each STM32MP platforms. This change moves function stm32_get_gpio_bank_clock() from stm32mp common source files to platform private stm32mp1_private.c source file. Change-Id: I9616c0d3fe4d10af715d6f2d1550c13ab62c829a Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * clk: stm32mp1: move oscillator functions to generic fileYann Gautier2019-06-171-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Those functions are generic for parsing nodes from device tree hence could be located in generic source file. The oscillators description structure is also moved to STM32MP1 clock driver, as it is no more used in stm32mp1_clkfunc and cannot be in a generic file. Change-Id: I93ba74f4eea916440fef9b160d306af1b39f17c6 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge changes If61ab215,I3e8b0251,I1757eee9,I81b48475,I46b445a7, ... into ↵John Tsichritzis2019-06-176-17/+58
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | integration * changes: rcar_gen3: drivers: qos: Move QoS drivers out of staging rcar_gen3: drivers: qos: V3M: Configure DBSC QoS from a table rcar_gen3: drivers: qos: E3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: D3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3N: Configure DBSC QoS from a table rcar_gen3: drivers: qos: M3W: Configure DBSC QoS from a table rcar_gen3: drivers: qos: H3: Configure DBSC QoS from a table rcar_gen3: drivers: qos: Add function to configure DBSC QoS settings from a table rcar_gen3: drivers: qos: Fix checkpatch issues rcar_gen3: drivers: qos: V3M: Drop useless comments rcar_gen3: drivers: qos: V3M: Convert mstat table to uint64_t rcar_gen3: drivers: qos: V3M: Factor out mstat fix into separate file rcar_gen3: drivers: qos: V3M: Use common register definition rcar_gen3: drivers: qos: E3: Drop extra level of nesting rcar_gen3: drivers: qos: E3: Use common register definition rcar_gen3: drivers: qos: D3: Replace ad-hoc register addresses with macros rcar_gen3: drivers: qos: D3: Drop MD pin check rcar_gen3: drivers: qos: D3: Make DBSC settings local to dbsc_setting() rcar_gen3: drivers: qos: D3: Drop useless comments rcar_gen3: drivers: qos: D3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: D3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: D3: Use common register definition rcar_gen3: drivers: qos: M3N: Fix checkpatch issues rcar_gen3: drivers: qos: M3N: Drop MD pin check rcar_gen3: drivers: qos: M3N: Drop useless comments rcar_gen3: drivers: qos: M3N: Drop extra level of nesting rcar_gen3: drivers: qos: M3N: Use common register definition rcar_gen3: drivers: qos: M3W: Fix checkpatch issues rcar_gen3: drivers: qos: M3W: Drop MD pin check rcar_gen3: drivers: qos: M3W: Drop useless comments rcar_gen3: drivers: qos: M3W: Drop extra level of nesting rcar_gen3: drivers: qos: M3W: Convert mstat table to uint64_t rcar_gen3: drivers: qos: M3W: Factor out mstat fix into separate file rcar_gen3: drivers: qos: M3W: Use common register definition rcar_gen3: drivers: qos: H3: Fix checkpatch issues rcar_gen3: drivers: qos: H3: Drop MD pin check rcar_gen3: drivers: qos: H3: Drop useless comments rcar_gen3: drivers: qos: H3: Drop extra level of nesting rcar_gen3: drivers: qos: H3: Convert mstat table to uint64_t rcar_gen3: drivers: qos: H3: Factor out mstat fix into separate file rcar_gen3: drivers: qos: H3: Use common register definition rcar_gen3: console: Convert to multi-console API
| * | rcar_gen3: drivers: qos: Move QoS drivers out of stagingMarek Vasut2019-06-171-2/+2
| | | | | | | | | | | | | | | | | | | | | Now that QoS drivers are cleaned up , move them out of staging. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: If61ab2157c30b8f5a6b91d2c56ddbb9098ef99e8
| * | rcar_gen3: console: Convert to multi-console APIMarek Vasut2019-06-146-15/+56
| |/ | | | | | | | | | | | | | | Convert the R-Car Gen3 platform and both SCIF and Log drivers to multi-console API. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Change-Id: I18556973937d150b60453f9150d54ee612571e35
* | Merge "allwinner: Disable unused features to save space" into integrationJohn Tsichritzis2019-06-171-0/+9
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| * allwinner: Disable unused features to save spaceSamuel Holland2019-06-081-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As all Allwinner platforms are single-cluster A53 chips, we can disable support for newer, unsupported architecture extensions. We can also avoid some cache maintenance code, since no platform-specific setup is required to enable coherency. These changes reduce the size of .text on a default build with GCC 9.1 enough that .vectors again fits in the second half of a page, instead of requiring its own page. This commit was boot-tested on the Pinebook. Signed-off-by: Samuel Holland <samuel@sholland.org> Change-Id: Ib90454ef0c798d5e714b7780c585be0b1ed49c6d
* | plat/arm: Skip BL2U if RESET_TO_SP_MIN flag is setLouis Mayencourt2019-06-111-3/+3
| | | | | | | | | | | | | | | | BL2U should not build when RESET_TO_SP_MIN flag is set, like BL1 and BL2. Change-Id: Iac516121f98611ca1f58d2b5efdec6525b06ce4e Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Merge changes from topic "jts/ti_fix" into integrationSoby Mathew2019-06-102-24/+2
|\ \ | |/ |/| | | | | | | * changes: ti: k3: common: Remove coherency workaround for AM65x ti: k3: common: Use coherent memory for shared data
| * ti: k3: common: Remove coherency workaround for AM65xAndrew F. Davis2019-06-062-22/+0
| | | | | | | | | | | | | | | | | | | | | | We previously left our caches on during power-down to prevent any non-caching accesses to memory that is cached by other cores. Now with the last accessed areas all being marked as non-cached by USE_COHERENT_MEM we can rely on that to workaround our interconnect issues. Remove the old workaround. Change-Id: Idadb7696d1449499d1edff4f6f62ab3b99d1efb7 Signed-off-by: Andrew F. Davis <afd@ti.com>
| * ti: k3: common: Use coherent memory for shared dataAndrew F. Davis2019-06-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | HW_ASSISTED_COHERENCY implies something stronger than just hardware coherent interconnect, specifically a DynamIQ capable ARM core. For K3, lets use WARMBOOT_ENABLE_DCACHE_EARLY to enable caches early and then let the caches get shut off on powerdown, to prevent data corruption we also need to USE_COHERENT_MEM so that any accesses to shared memory after this point is only to memory that is set as non-cached for all cores. Change-Id: Ib9337f012df0e0388237942607c501b6f3e2a949 Signed-off-by: Andrew F. Davis <afd@ti.com>
* | Merge "FVP: Remove GIC initialisation from secondary core cold boot" into ↵John Tsichritzis2019-06-061-38/+1
|\ \ | | | | | | | | | integration
| * | FVP: Remove GIC initialisation from secondary core cold bootJohn Tsichritzis2019-06-051-38/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During the secondary cores' cold boot path, the cores initialise the GIC CPU interface. However this is a redundant action since 1) the cores are powered down immediately after that, 2) the GIC CPU interface is initialised from scratch when the secondary cores are powered up again later. Moreover, this part of code was introducing a bug. In a GICv3 system, the GIC's CPU interface system registers must not be written without the core being marked as "awake" in the redistributor. However, this sequence was performing such accesses and this would cause those cores to hang. The hang was caused by the DSB instruction that would never complete because of the GIC not recognising those writes. For the two aforementioned reasons, the entire part of the GIC CPU interface initialisation is removed. Change-Id: I6c33a1edda69dd5b6add16a27390a70731b5532a Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* | mediatek: mt8183: add mcsi driverkenny liang2019-06-066-4/+370
| | | | | | | | | | | | | | add mcsi driver to support cache coherence. Change-Id: I94f5922783e5dbc6b7e92aa06464bc1f0177f00a Signed-off-by: kenny liang <kenny.liang@mediatek.com>
* | mediatek: mt8183: add GIC driverkenny liang2019-06-065-5/+193
| | | | | | | | | | | | | | Add Mediatek GIC driver to support interrupt functions. Signed-off-by: kenny liang <kenny.liang@mediatek.com> Change-Id: I967a18f2e45b7bbc88c506dd4f1f40a745227ad9
* | Apply compile-time check for AArch64-only coresJohn Tsichritzis2019-06-041-10/+15
|/ | | | | | | | | | | | | | | | | Some cores support only AArch64 mode. In those cores, only a limited subset of the AArch32 system registers are implemented. Hence, if TF-A is supposed to run on AArch64-only cores, it must be compiled with CTX_INCLUDE_AARCH32_REGS=0. Currently, the default settings for compiling TF-A are with the AArch32 system registers included. So, if we compile TF-A the default way and attempt to run it on an AArch64-only core, we only get a runtime panic. Now a compile-time check has been added to ensure that this flag has the appropriate value when AArch64-only cores are included in the build. Change-Id: I298ec550037fafc9347baafb056926d149197d4c Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge "rockchip: drop rockchip-specific imported linker symbols for bl31" ↵Paul Beesley2019-05-301-13/+4
|\ | | | | | | into integration
| * rockchip: drop rockchip-specific imported linker symbols for bl31Heiko Stuebner2019-05-291-13/+4
| | | | | | | | | | | | | | | | | | | | | | In the rockchip bl31 setup the __RO_START__ and __RO_END__ symbols are currently imported into special BL31_RO_* constants while the general code also imports them as BL_CODE_BASE and BL_CODE_END. So we can just use the general symbols and can drop the duplication. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Change-Id: Ibf1b48ad80bed897247a1690a32711030479262d
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