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* DynamIQ: Enable MMU without using stackJeenu Viswambharan2018-06-272-12/+22
| | | | | | | | | | | | | | | | | | | Having an active stack while enabling MMU has shown coherency problems. This patch builds on top of translation library changes that introduces MMU-enabling without using stacks. Previously, with HW_ASSISTED_COHERENCY, data caches were disabled while enabling MMU only because of active stack. Now that we can enable MMU without using stack, we can enable both MMU and data caches at the same time. NOTE: Since this feature depends on using translation table library v2, disallow using translation table library v1 with HW_ASSISTED_COHERENCY. Fixes ARM-software/tf-issues#566 Change-Id: Ie55aba0c23ee9c5109eb3454cb8fa45d74f8bbb2 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Merge pull request #1445 from danielboulby-arm/db/DynamicAuthenticationDimitris Papastamos2018-06-251-1/+1
|\ | | | | Set FVP DYN_DISABLE_AUTH authentication default to 0
| * Set FVP DYN_DISABLE_AUTH authentication default to 0Daniel Boulby2018-06-251-1/+1
| | | | | | | | | | | | | | | | Set the ability to dynamically disable Trusted Boot Board authentication to be off by default Change-Id: Ibd2aa179179f7d9b0e7731c6e450f200a8c67529 Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* | Merge pull request #1448 from npoushin/npoushin/sgi575-coverity-fixesDimitris Papastamos2018-06-253-6/+18
|\ \ | |/ |/| npoushin/sgi575 coverity fixes
| * plat/arm: css: Sanitize the input to css_validate_power_stateNariman Poushin2018-06-231-1/+13
| | | | | | | | | | | | | | | | | | | | In the case of the platform max power level being less than the system power level, make sure to not overrun the array of power states. This fixes Coverity Scan OVERRUN defect CID 267021. Change-Id: I52646ab9be2fceeb5c331b5dad7a6267991f4197 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
| * plat/arm: css: Convert CSS_SYSTEM_PWR_STATE from macro to inline functionNariman Poushin2018-06-233-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This is to fix a number of Coverity Scan DEADCODE defects, CID numbers listed below, as reported from https://scan.coverity.com/projects/arm-software-arm-trusted-firmware CID 267023 CID 267022 CID 267020 Change-Id: I2963a799b210149e84ccab5c5b9082267ddfe337 Signed-off-by: Nariman Poushin <nariman.poushin@linaro.org>
* | Merge pull request #1441 from robertovargas-arm/mem_protect_boardDimitris Papastamos2018-06-223-0/+34
|\ \ | | | | | | Move mem-protect definitions to board specific files
| * | Move mem-protect definitions to board specific filesRoberto Vargas2018-06-183-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Having these definitions in board_arm_def.h forces to all the arm platforms to use the same definition for PLAT_ARM_MEM_PROT_ADDR. This macro also enables the mem-protect mechanism, which means that all the arm platform has enabled mem-protect and they cannot get rid of it. Change-Id: Id29d2c51cbe6edc15f010a9f5a20c42266c48a08 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1406 from robertovargas-arm/uuidDimitris Papastamos2018-06-226-19/+18
|\ \ \ | |_|/ |/| | Make TF UUID RFC 4122 compliant
| * | Make TF UUID RFC 4122 compliantRoberto Vargas2018-06-146-19/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | RFC4122 defines that fields are stored in network order (big endian), but TF-A stores them in machine order (little endian by default in TF-A). We cannot change the future UUIDs that are already generated, but we can store all the bytes using arrays and modify fiptool to generate the UUIDs with the correct byte order. Change-Id: I97be2d3168d91f4dee7ccfafc533ea55ff33e46f Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* | | Merge pull request #1437 from jeenu-arm/ras-remainingDimitris Papastamos2018-06-224-18/+21
|\ \ \ | | | | | | | | SDEI dispatch changes to enable RAS use cases
| * | | Arm platforms: Remove common RAS configuration sourceJeenu Viswambharan2018-06-214-18/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The file arm_ras.c intended to provide common platform-specific RAS configuration for Arm platforms. Because this file has symbol definitions, it's proving difficult to provide a common definition. This patch therefore renames and makes the file specific to FVP. Other platforms shall provide their own configuration in similar fashion. Change-Id: I766fd238946e3e49cdb659680e1b45f41b237901 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* | | | Merge pull request #1427 from b49020/integrationDimitris Papastamos2018-06-2215-0/+1287
|\ \ \ \ | |/ / / |/| | | Add support for Socionext Synquacer SC2A11 SoC based Developerbox platform.
| * | | synquacer: Add platform makefile and documentationSumit Garg2018-06-211-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Makefile and plaform definations file. My thanks to Daniel Thompson and Ard Biesheuvel for the bits and pieces I've taken from their earlier work regarding build and deploy steps for Developerbox based on Synquacer SoCs. They deserve much of the credit for this work although, since I assembled and tested things, any blame is probably mine. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Tested-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
| * | | synquacer: Enable PSCI frameworkSumit Garg2018-06-212-0/+198
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PSCI framework uses SCPI driver to communicate to SCP firmware for various power management operations. Following PSCI operations are supported: - CPU ON - CPU OFF - CPU STANDBY - SYSTEM RESET - SYSTEM OFF Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Retrieve DRAM info from SCP firmwareArd Biesheuvel2018-06-214-0/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Retrieve DRAM info from SCP firmware using SCPI driver. Board supports multiple DRAM slots so its required to fetch DRAM info from SCP firmware and pass this info to UEFI via non-secure SRAM. Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Add SCPI driverSumit Garg2018-06-213-0/+255
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add System Control and Power Interface (SCPI) driver which provides APIs for PSCI framework to work. SCPI driver uses MHU driver APIs to communicate with SCP firmware for various system control and power operations. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Add MHU driverSumit Garg2018-06-215-0/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Message Handling Unit (MHU) driver used to communicate among Application Processors (AP) and System Control Processor (SCP). Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Enable MMU using xlat_tables_v2 librarySumit Garg2018-06-214-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BL31 runs from SRAM which is a non-coherent memory on synquacer. So enable MMU with SRAM memory marked as Non-Cacheable and mark page tables kept on SRAM as Non-Cacheable via XLAT_TABLE_NC flag. Also add page tables for Device address space. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Enable System level Generic timerSumit Garg2018-06-212-0/+41
| | | | | | | | | | | | | | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Enable GICv3 supportSumit Garg2018-06-214-0/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | synquacer uses GICv3 compliant GIC500. So enable proper GICv3 driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Enable CCN driver supportSumit Garg2018-06-214-0/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | synquacer has CCN-512 interconnect. So enable proper CCN driver initialization. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Implement topology functionsSumit Garg2018-06-213-0/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Populate BL32 and BL33 entrypointsSumit Garg2018-06-211-0/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | As this platform supports direct entry to BL31 and no BL2, so populate BL32 and BL33 entrypoints with static memory load info. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Enable PL011 UART ConsoleSumit Garg2018-06-213-0/+55
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Add platform core management helpersSumit Garg2018-06-213-0/+90
| | | | | | | | | | | | | | | | Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
| * | | synquacer: Introduce basic platform supportSumit Garg2018-06-212-0/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | synquacer supports direct entry to BL31 without BL1 and BL2 as SCP firmware does similar work. So this patch adds BL31 stub APIs. Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
* | | | Merge pull request #1434 from soby-mathew/sm/fix_cntfrqDimitris Papastamos2018-06-211-0/+20
|\ \ \ \ | | | | | | | | | | ARM Platforms: Update CNTFRQ register in CNTCTLBase frame
| * | | | ARM Platforms: Update CNTFRQ register in CNTCTLBase frameSoby Mathew2018-06-201-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently TF-A doesn't initialise CNTFRQ register in CNTCTLBase frame of the system timer. ARM ARM states that "The instance of the register in the CNTCTLBase frame must be programmed with this value as part of system initialization." The psci_arch_setup() updates the CNTFRQ system register but according to the ARM ARM, this instance of the register is independent of the memory mapped instance. This is only an issue for Normal world software which relies on the memory mapped instance rather than the system register one. This patch resolves the issue for ARM platforms. The patch also solves a related issue on Juno, wherein CNTBaseN.CNTFRQ can be written and does not reflect the value of the register in CNTCTLBase frame. Hence this patch additionally updates CNTFRQ register in the Non Secure frame of the CNTBaseN. Fixes ARM-Software/tf-issues#593 Change-Id: I09cebb6633688b34d5b1bc349fbde4751025b350 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* | | | | Merge pull request #1433 from sivadur/integrationDimitris Papastamos2018-06-212-4/+13
|\ \ \ \ \ | |_|/ / / |/| | | | xilinx: fix zynqmp build when tsp is enabled
| * | | | plat: xilinx: zynqmp: Get chipid from registers for BL32Siva Durga Prasad Paladugu2018-06-211-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reads the chipid registers directly instead of making pm call when running at BL32. User should ensure that these registers should always be accessed from APU in their system configuration. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
| * | | | plat: xilinx: zynqmp: Build for DDR if SPD is enabledSiva Durga Prasad Paladugu2018-06-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch builds ATF to DDR if SPD is enabled as it cant fit in On chip memory(OCM) with SPD enabled. This solves the issue of build failure with SPD enabled for ZynqMP platform. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
* | | | | Merge pull request #1403 from glneo/for-upstream-k3Dimitris Papastamos2018-06-2014-0/+907
|\ \ \ \ \ | | | | | | | | | | | | TI K3 platform support
| * | | | | ti: k3: Introduce basic generic board supportNishanth Menon2018-06-193-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | While it would be useful to have a device tree based build, the required components are not in place yet, so support just a simple statically defined configuration to begin with. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Add PSCI stubsBenjamin Fair2018-06-192-0/+100
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions are used for the PSCI implementation and are needed to build BL31, but we cannot implement them until we add several more drivers related to ti-sci so these are only stubs for now. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Enable GICv3 supportNishanth Menon2018-06-195-1/+142
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Do proper initialization of GIC V3. This will allow CP15 access to GIC from "normal world" (aka HLOS) via mrc/mcr calls. K3 SoC family uses GICv3 compliant GIC500 without compatibility for legacy GICv2. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Program A53 arch timer frequencyNishanth Menon2018-06-192-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide K3_TIMER_FREQUENCY for the platform configuration if the GTC clock is selected statically and override option if the platform has a different configuration. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com>
| * | | | | ti: k3: common: Add console initialization baseNishanth Menon2018-06-196-0/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Enable MMU using xlat_tables_v2 libraryNishanth Menon2018-06-193-1/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This library will be used to properly set up mappings from different bootloaders at different exception levels. It ensures that memory mapped devices such as UARTs are still accessible and memory regions have the correct access permissions. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Implement topology functionsBenjamin Fair2018-06-192-0/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These functions describe the layout of the cores and clusters in order to support the PSCI framework. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Populate BL32 and BL33 entrypointBenjamin Fair2018-06-191-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because there is no BL2, BL31 must determine the entrypoint and memory location of BL32 and BL33 on its own. BL32_BASE and PRELOADED_BL33_BASE will be set in the corresponding board makefile. We also allow a DTB address to be specified for cases when BL33 is a Linux image. NOTE: It is possible to pull in this information from device tree as well, however libfdt does not contain the required hooks to make this happen at this point in time. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: common: Add platform core management helpersBenjamin Fair2018-06-193-0/+135
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The K3 family of SoCs has multiple interconnects. The key interconnect for high performance processors is the MSMC3 interconnect. This is an io-coherent interconnect which exports multiple ports for each processor cluster. Sometimes, port 0 of the MSMC may not have an ARM cluster OR is isolated such that the instance of ATF does not manage it. Define macros in platform_def.h to help handle this. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
| * | | | | ti: k3: Setup initial files for platformNishanth Menon2018-06-195-0/+193
| | |/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create the baseline Makefile, platform definitions file and platform specific assembly macros file. This includes first set of constants for the platform including cache sizes and linker format and a stub for BL31 and the basic memory layout K3 SoC family of processors do not use require a BL1 or BL2 binary, since such functions are provided by an system controller on the SoC. This lowers the burden of ATF to purely managing the local ARM cores themselves. Signed-off-by: Benjamin Fair <b-fair@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Andrew F. Davis <afd@ti.com>
* | | | | Merge pull request #1413 from grandpaul/paulliu-rpi3-0Dimitris Papastamos2018-06-206-0/+86
|\ \ \ \ \ | |_|/ / / |/| | | | rpi3: BL32 optee support
| * | | | rpi3: add OPTEE supportYing-Chun Liu (PaulLiu)2018-06-196-0/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support for loading optee images as BL32 secure payload. Signed-off-by: Ying-Chun Liu (PaulLiu) <paul.liu@linaro.org>
* | | | | Merge pull request #1423 from chandnich/sgi-575/dyncfgDimitris Papastamos2018-06-206-63/+127
|\ \ \ \ \ | |_|/ / / |/| | | | Sgi 575/dyncfg
| * | | | sgi/mmap: Remove SGI specific MMAP functionsChandni Cherukuri2018-06-151-47/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the redundant SGI functions which map memory for BL1 and BL2. Change-Id: I651a06d0eb6d28263a56f59701bb3815f1ba93dc Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | sgi/dyncfg: add system-id node in hw-config dtbChandni Cherukuri2018-06-152-1/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Append a node to hw-config dtb which will include a property to hold the value of the SSC_VERSION register. This will be used by the BL33 stage to determine the platform-id and the config-id of the platform it is executing on. Change-Id: Ie7b1e5d8c1bbe0efdb7ef0714f14b7794ec6058e Signed-off-by: Amit Daniel Kachhap <amit.kachhap@arm.com> Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | | | sgi/dyncfg: add dts files to enable support for dynamic configChandni Cherukuri2018-06-154-15/+38
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the existing method of populating the platform id in arg2 of BL33 which is no longer needed with dynamic configuration feature enabled as the BL33 will get this information directly via the config files. Add the tb_fw_config and hw_config dts files. Change-Id: I3c93fec2aedf9ef1f774a5f0969d2d024e47ed2c Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | Merge pull request #1410 from Anson-Huang/masterDimitris Papastamos2018-06-1938-0/+7207
|\ \ \ \ | | | | | | | | | | Add NXP's i.MX8QX and i.MX8QM SoC support
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