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* plat: imx: imx8qx: provide debug uart num as build paramIgor Opaniuk2020-03-233-9/+54
| | | | | | | | | | | | | | | | | | | | | | 1. This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag. Also for Colibri i.MX8QXP different pinmux configuration is applied for UART3, FLEXCAN2_RX/TX pads are muxed to ADMA_UART3_RX/TX. 2. Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A35 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A35 is enabled. Check similar commit for i.MX8QM 98a69dfd4a("plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE")). Usage: $ make PLAT=imx8qx IMX_DEBUG_UART=3 DEBUG_CONSOLE=1 bl31 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I5d04939b2e8ee1a5f4b2f3c6241977d3c6e91760
* Merge changes I8ca411d5,Ib5f5dd81,I0488e22c into integrationManish Pandey2020-03-234-24/+56
|\ | | | | | | | | | | | | * changes: plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLE plat: imx: imx8qm: provide debug uart num as build param plat: imx: imx8_iomux: fix shift-overflow errors
| * plat: imx: imx8qm: apply clk/pinmux configuration for DEBUG_CONSOLEIgor Opaniuk2020-03-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | Having DEBUG_CONSOLE enabled without enabling DEBUG_CONSOLE_A53 doesn't make sense (since UART pinmux/clock configuration is applied for UART only when DEBUG_CONSOLE_A53 is enabled). Enable DEBUG_CONSOLE_A53 if DEBUG_CONSOLE is enabled. Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I8ca411d5544658b9bcc39e5340ec042c51088b96
| * plat: imx: imx8qm: provide debug uart num as build paramIgor Opaniuk2020-03-163-9/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | This removes hardcoded iomux/clk/addr configuration for debug uart, provides possibility (as a workaround, till that information isn't provided via DT) to set this configuration during compile time via IMX_DEBUG_UART build flag. Usage: $ make PLAT=imx8qm IMX_DEBUG_UART=1 bl31 Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: Ib5f5dd81ba0c8ad2b2dc5647ec75629072f511c5
| * plat: imx: imx8_iomux: fix shift-overflow errorsIgor Opaniuk2020-03-161-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | This fixes shift overflow errors, when compiled with CONSOLE_DEBUG support: plat/imx/common/include/imx8_iomux.h:11:35: error: result of ‘1 << 31’ requires 33 bits to represent, but ‘int’ only has 32 bits [-Werror=shift-overflow=] Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com> Change-Id: I0488e22c30314ba27caabc5c767164baa1e8004c
* | Merge "fvp: use two instances of Cactus at S-EL1" into integrationManish Pandey2020-03-201-2/+2
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| * | fvp: use two instances of Cactus at S-EL1Manish Pandey2020-03-191-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To demonstrate communication between SP's two instances of Cactus at S-EL1 has been used. This patch replaces Ivy SP with cactus-secondary SP which aligns with changes in tf-a-tests repository. Signed-off-by: Manish Pandey <manish.pandey2@arm.com> Change-Id: Iee84f1f7f023b7c4f23fbc13682a42614a7f3707
* | | Merge "spmc: manifest changes to support two sample cactus secure ↵Manish Pandey2020-03-202-2/+50
|\ \ \ | | | | | | | | | | | | partitions" into integration
| * | | spmc: manifest changes to support two sample cactus secure partitionsOlivier Deprez2020-03-192-2/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When using the SPM Dispatcher, the SPMC sits as a BL32 component (BL32_IMAGE_ID). The SPMC manifest is passed as the TOS fw config component (TOS_FW_CONFIG_ID). It defines platform specific attributes (memory range and physical CPU layout) as well as the attributes for each secure partition (mostly load address). This manifest is passed to the SPMC on boot up. An SP package contains the SP dtb in the SPCI defined partition manifest format. As the SPMC manifest was enriched it needs an increase of tos_fw-config max-size in fvp_fw_config dts. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: Ia1dce00c6c4cbaa118fa56617980d32e2956a94e
* | | | Tegra: assembly version of the 'plat_core_pos_by_mpidr' handlerVarun Wadekar2020-03-183-50/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'plat_core_pos_by_mpidr' handler gets called very early during boot and the compiler generated code overwrites the caller's registers. This patch converts the 'plat_core_pos_by_mpidr' handler into an assembly function and uses registers x0-x3, to fix this anomaly. Change-Id: I8d974e007a0bad039defaf77b11a180d899ead3c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra194: reset power state info for CPUsVarun Wadekar2020-03-181-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We set deepest power state when offlining a core but that may not be requested by non-secure sw which controls idle states. It will re-init this info from non-secure software when the core come online. This patch resets the power state in the non-secure world context to allow it to start with a clean slate. Change-Id: Iafd92cb2a49571aa6eeb9580beaaff4ba55a87dc Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra186: system resume from TZSRAM memoryVarun Wadekar2020-03-186-118/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TZSRAM loses power during System suspend, so the entire contents are copied to TZDRAM before Sysem Suspend entry. The warmboot code verifies and restores the contents to TZSRAM during System Resume. This patch removes the code that sets up CPU vector to point to TZSRAM during System Resume as a result. The trampoline code can also be completely removed as a result. Change-Id: I2830eb1db16efef3dfd96c4e3afc41a307588ca1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra186: disable PROGRAMMABLE_RESET_ADDRESSVarun Wadekar2020-03-185-55/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch disables the code to program reset vector for secondary CPUs to a different entry point, than cold boot. The cold boot entry point has the ability to differentiate between a cold boot and a warm boot, that is controlled by the PROGRAMMABLE_RESET_ADDRESS macro. By reusing the same entry point, we can lock the CPU reset vector during cold boot. Change-Id: Iad400841d57c139469e1d29b5d467197e11958c4 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra210: SE: switch SE clock source to CLK_MLeo He2020-03-181-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In SE suspend, switch SE clock source to CLK_M, to make sure SE clock is on when saving SE context Change-Id: I57c559825a3ec8e0cc35f7a389afc458a5eed0cb Signed-off-by: Leo He <leoh@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra: increase platform assert logging level to VERBOSEVarun Wadekar2020-03-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch increases the assert logging level for all Tegra platforms to VERBOSE, to print the actual assertion condition to the console, improving debuggability. Change-Id: If3399bde63fa4261522cab984cc9c49cd2073358 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra194: enable dual execution for EL2 and EL3Kalyani Chidambaram2020-03-183-6/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables dual execution optimized translations for EL2 and EL3 CPU exception levels. Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra: aarch64: calculate core position from one placeKalyani Chidambaram2020-03-181-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates 'plat_my_core_pos' handler to call 'plat_core_pos_from_mpidr' instead of implementing the same logic at two places. Change-Id: I1e56adaa10dc2fe3440e5507e0e260d8932e6657 Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
* | | | Tegra194: Update t194_nvg.h to v6.7Kalyani Chidambaram2020-03-181-16/+21
| |/ / |/| | | | | | | | | | | | | | | | | | | | This patch updates the t194_nvg.h header file received from the CPU team to v6.7. Change-Id: I5d25dfc60448e14b7085250946bd002fcb80a774 Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
* | | Merge changes from topic "rpix-multi-console" into integrationSandrine Bailleux2020-03-1814-57/+72
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: rpi: docs: Update maintainers file to new RPi directory scheme rpi: console: Autodetect Mini-UART vs. PL011 configuration rpi3: build: Include GPIO driver in all BL stages rpi: Allow using PL011 UART for RPi3/RPi4 rpi3: console: Use same "clock-less" setup scheme as RPi4 rpi3: gpio: Simplify GPIO setup
| * | | rpi: console: Autodetect Mini-UART vs. PL011 configurationAndre Przywara2020-03-172-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Raspberry Pi has two different UART devices pin-muxed to GPIO 14&15: One ARM PL011 one and the 8250 compatible "Mini-UART". A dtoverlay parameter in config.txt will tell the firmware to switch between the two: it will setup the right clocks and will configure the pinmuxes accordingly. To autodetect the user's choice, we read the pinmux register and check its setting: ALT5 (0x2) means the Mini-UART is used, ALT0 (0x4) points to the PL011. Based on that we select the UART driver to initialise. This will allow console output in any case. Change-Id: I620d3ce68de6c6576599f2a405636020e1fd1376 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
| * | | rpi3: build: Include GPIO driver in all BL stagesAndre Przywara2020-03-171-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the Raspberry Pi 3 build needs the GPIO driver just for BL2. Upcoming changes will require some GPIO code in BL1 and BL31 also, so move those driver files into the common source section. This does not affect BL31 code size at all, and bl1.bin just increases by 144 bytes, but doesn't affect the padded binary size at all. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I7639746dc241c1e69099d85d2671c65fa0108555
| * | | rpi: Allow using PL011 UART for RPi3/RPi4Andre Przywara2020-03-177-6/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Broadcom 283x SoCs feature multiple UARTs: the mostly used "Mini-UART", which is an 8250 compatible IP, and at least one PL011. While the 8250 is usually used for serial console purposes, it suffers from a design flaw, where its clock depends on the VPU clock, which can change at runtime. This will reliably mess up the baud rate. To avoid this problem, people might choose to use the PL011 UART for the serial console, which is pin-mux'ed to the very same GPIO pins. This can be done by adding "miniuart-bt" to the "dtoverlay=" line in config.txt. To prepare for this situation, use the newly gained freedom of sharing one console_t pointer across different UART drivers, to introduce the option of choosing the PL011 for the console. This is for now hard-coded to choose the Mini-UART by default. A follow-up patch will introduce automatic detection. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: I8cf2522151e09ff4ff94a6d396aec6fc4b091a05
| * | | rpi3: console: Use same "clock-less" setup scheme as RPi4Andre Przywara2020-03-1712-40/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the wake of the upcoming unification of the console setup code between RPi3 and RPi4, extend the "clock-less" setup scheme to the RPi3. This avoid programming any clocks or baud rate registers, which makes the port more robust against GPU firmware changes. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Change-Id: Ida83a963bb18a878997e9cbd55f8ceac6a2e1c1f
| * | | rpi3: gpio: Simplify GPIO setupAndre Przywara2020-03-171-12/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is really no reason to use and pass around a struct when its only member is the (fixed) base address. Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically. This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore. Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | Merge "Implement SMCCC_ARCH_SOC_ID SMC call" into integrationManish Pandey2020-03-182-0/+35
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| * | | Implement SMCCC_ARCH_SOC_ID SMC callManish V Badarkhe2020-03-172-0/+35
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information: 1. SOC revision 2. SOC version Implementation done using below SMCCC specification document: https://developer.arm.com/docs/den0028/c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b
* | | Merge "FVP: In BL31/SP_MIN, map only the needed DRAM region statically" into ↵Olivier Deprez2020-03-184-6/+17
|\ \ \ | | | | | | | | | | | | integration
| * | | FVP: In BL31/SP_MIN, map only the needed DRAM region staticallyMadhukar Pappireddy2020-03-174-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than creating entry in plat_arm_mmap array to map the entire DRAM region in BL31/SP_MIN, only map a smaller region holding HW_CONFIG DTB. Consequently, an increase in number of sub-translation tables(level-2 and level-3) i.e., MAX_XLAT_TABLES is necessary to map the new region in memory. In order to accommodate the increased code size in BL31 i.e., PROGBITS, the max size of BL31 image is increased by 0x1000(4K). Change-Id: I540b8ee550588e22a3a9fb218183d2ab8061c851 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | Merge "board/rddaniel: add NSAID sources for TZC400 driver" into integrationManish Pandey2020-03-171-1/+11
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| * | | board/rddaniel: add NSAID sources for TZC400 driverAditya Angadi2020-03-121-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CLCD, HDLCD, PCI and VIRTIO devices as source interfaces for TZC filter unit to enable DMA for these devices. Change-Id: Ifad2e56b18605311936e03cfcccda573cac7e60a Signed-off-by: Aditya Angadi <aditya.angadi@arm.com>
* | | | Merge "SPMD: Add support for SPCI_ID_GET" into integrationSandrine Bailleux2020-03-132-0/+8
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| * | | | SPMD: Add support for SPCI_ID_GETMax Shvetsov2020-03-122-0/+8
| | |_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the SPCI component ID as specified in the manifest for secure world requests. Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
* | | | Merge "juno/sgm: Maximize space allocated to SCP_BL2" into integrationSandrine Bailleux2020-03-132-18/+10
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| * | | | juno/sgm: Maximize space allocated to SCP_BL2Chris Kay2020-03-122-18/+10
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To accommodate the increasing size of the SCP_BL2 binary, the base address of the memory region allocated to SCP_BL2 has been moved downwards from its current (mostly) arbitrary address to the beginning of the non-shared trusted SRAM. Change-Id: I086a3765bf3ea88f45525223d765dc0dbad6b434 Signed-off-by: Chris Kay <chris.kay@arm.com>
* | | | Merge changes from topic "mp/enhanced_pal_hw" into integrationMark Dykes2020-03-1214-21/+324
|\ \ \ \ | |_|/ / |/| | / | | |/ | |/| | | | | | | | | | * changes: plat/arm/fvp: populate pwr domain descriptor dynamically fconf: Extract topology node properties from HW_CONFIG dtb fconf: necessary modifications to support fconf in BL31 & SP_MIN fconf: enhancements to firmware configuration framework
| * | plat/arm/fvp: populate pwr domain descriptor dynamicallyMadhukar Pappireddy2020-03-111-10/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The motivation behind this patch and following patches is to extract information about the platform in runtime rather than depending on compile time macros such as FVP_CLUSTER_COUNT. This partially enables us to use a single binary for a family of platforms which all have similar hardware capabilities but differ in configurations. we populate the data structure describing the power domain hierarchy of the platform dynamically by querying the number of clusters and cpus using fconf getter APIs. Compile time macro such as FVP_CLUSTER_COUNT is still needed as it determines the size of related data structures. Note that the cpu-map node in HW_CONFIG dts represents a logical hierarchy of power domains of CPU. However, in reality, the power domains may not have been physically built in such hierarchy. Change-Id: Ibcbb5ca7b2c969f8ad03ab2eab289725245af7a9 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | fconf: Extract topology node properties from HW_CONFIG dtbMadhukar Pappireddy2020-03-113-0/+129
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Create, register( and implicitly invoke) fconf_populate_topology() function which extracts the topology related properties from dtb into the newly created fconf based configuration structure 'soc_topology'. Appropriate libfdt APIs are added to jmptbl.i file for use with USE_ROMLIB build feature. A new property which describes the power domain levels is added to the HW_CONFIG device tree source files. This patch also fixes a minor bug in the common device tree file fvp-base-gicv3-psci-dynamiq-common.dtsi As this file includes fvp-base-gicv3-psci-common.dtsi, it is necessary to delete all previous cluster node definitons because DynamIQ based models have upto 8 CPUs in each cluster. If not deleted, the final dts would have an inaccurate description of SoC topology, i.e., cluster0 with 8 or more core nodes and cluster1 with 4 core nodes. Change-Id: I9eb406da3ba4732008a66c01afec7c9fa8ef59bf Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | fconf: necessary modifications to support fconf in BL31 & SP_MINMadhukar Pappireddy2020-03-119-8/+156
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN. Created few populator() functions which parse HW_CONFIG device tree and registered them with fconf framework. Many of the changes are only applicable for fvp platform. This patch: 1. Adds necessary symbols and sections in BL31, SP_MIN linker script 2. Adds necessary memory map entry for translation in BL31, SP_MIN 3. Creates an abstraction layer for hardware configuration based on fconf framework 4. Adds necessary changes to build flow (makefiles) 5. Minimal callback to read hw_config dtb for capturing properties related to GIC(interrupt-controller node) 6. updates the fconf documentation Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | fconf: enhancements to firmware configuration frameworkMadhukar Pappireddy2020-03-113-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A populate() function essentially captures the value of a property, defined by a platform, into a fconf related c structure. Such a callback is usually platform specific and is associated to a specific configuration source. For example, a populate() function which captures the hardware topology of the platform can only parse HW_CONFIG DTB. Hence each populator function must be registered with a specific 'config_type' identifier. It broadly represents a logical grouping of configuration properties which is usually a device tree source file. Example: > TB_FW: properties related to trusted firmware such as IO policies, base address of other DTBs, mbedtls heap info etc. > HW_CONFIG: properties related to hardware configuration of the SoC such as topology, GIC controller, PSCI hooks, CPU ID etc. This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate() to register and invoke the appropriate callbacks selectively based on configuration type. Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | Merge "n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flag" into integrationManish Pandey2020-03-121-0/+3
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| * | | n1sdp: Enable the NEOVERSE_N1_EXTERNAL_LLC flagChandni Cherukuri2020-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since N1SDP has a system level cache which is an external LLC enable the NEOVERSE_N1_EXTERNAL_LLC flag. Change-Id: Idb34274e61e7fd9db5485862a0caa497f3e290c7 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | Tegra210: Remove "unsupported func ID" error msgKalyani Chidambaram2020-03-111-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform sip is reporting a "unsupported function ID" if the smc function id is not pmc command. When actually the smc function id could be specific to the tegra sip handler. This patch removes the error reported. Change-Id: Ia3c8545d345746c5eea6d75b9e6957ca23ae9ca3 Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
* | | | Tegra210: support for secure physical timerVarun Wadekar2020-03-112-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch enables on-chip timer1 interrupts for Tegra210 platforms. Change-Id: Ic7417dc0e69264d7c28aa012fe2322cd30838f3e Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra: smmu: export handlers to read/write SMMU registersVarun Wadekar2020-03-112-55/+56
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch exports the SMMU register read/write handlers for platforms. Change-Id: If92f0d3ce820e4997c090b48be7614407bb582da Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra: smmu: remove context save sequencePritesh Raithatha2020-03-1116-1351/+578
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SMMU and MC registers are saved as part of the System Suspend sequence. The register list includes some NS world SMMU registers that need to be saved by NS world software instead. All that remains as a result are the MC registers. This patch moves code to MC file as a result and renames all the variables and defines to use the MC prefix instead of SMMU. The Tegra186 and Tegra194 platform ports are updated to provide the MC context register list to the parent driver. The memory required for context save is reduced due to removal of the SMMU registers. Change-Id: I83a05079039f52f9ce91c938ada6cd6dfd9c843f Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
* | | | Tegra: bpmp: fixup TEGRA_CLK_SE values for Tegra186/Tegra194Varun Wadekar2020-03-116-13/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the SE clock ID being used for Tegra186 and Tegra194 SoCs. Previous assumption, that both SoCs use the same clock ID, was incorrect. Change-Id: I1ef0da5547ff2e14151b53968cad9cc78fee63bd Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | | Tegra194: memctrl: lock some more MC SID security configsPritesh Raithatha2020-03-111-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The platform code already contains the initial set of MC SID security configs to be locked during boot. This patch adds some more configs to the list. Since the reset value of these registers is already as per expectations, there is no need to change it. MC SID security configs - PTCR, - MIU6R, MIU6W, MIU7R, MIU7W, - MPCORER, MPCOREW, - NVDEC1SRD, NVDEC1SRD1, NVDEC1SWR. Change-Id: Ia9a1f6a6b6d34fb2787298651f7a4792a40b88ab Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
* | | | Tegra194: add SE support to generate SHA256 of TZRAMJeetesh Burman2020-03-115-3/+396
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BL3-1 firmware code is stored in TZSRAM on Tegra194 platforms. This memory loses power when we enter System Suspend and so its contents are stored to TZDRAM, before entry. This opens up an attack vector where the TZDRAM contents might be tampered with when we are in the System Suspend mode. To mitigate this attack the SE engine calculates the hash of entire TZSRAM and stores it in PMC scratch, before we copy data to TZDRAM. The WB0 code will validate the TZDRAM and match the hash with the one in PMC scratch. This patch adds driver for the SE engine, with APIs to calculate the hash and store to PMC scratch registers. Change-Id: I04cc0eb7f54c69d64b6c34fc2ff62e4cfbdd43b2 Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
* | | | Tegra194: store TZDRAM base/size to scratch registersJeetesh Burman2020-03-112-2/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch saves the TZDRAM base and size values to secure scratch registers, for the WB0. The WB0 reads these values and uses them to verify integrity of the TZDRAM aperture. Change-Id: I2f5fd11c87804d20e2698de33be977991c9f6f33 Signed-off-by: Jeetesh Burman <jburman@nvidia.com>
* | | | Tegra194: fix warnings for extra parentheseskalyani chidambaram2020-03-111-1/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | armclang displays warnings for extra parentheses, leading to build failures as warnings are treated as errors. This patch removes the extra parentheses to fix this issue. Change-Id: Id2fd6a3086590436eecabc55502f40752a018131 Signed-off-by: Kalyani Chidambaram <kalyanic@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2025-06-15 08:16:15 +0000