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| author | Leo He <leoh@nvidia.com> | 2018-07-12 17:36:12 +0800 |
|---|---|---|
| committer | Varun Wadekar <vwadekar@nvidia.com> | 2020-03-18 17:47:17 -0700 |
| commit | 35aa1c1e51b62467ac31958983a67ef0d5646acb (patch) | |
| tree | db857eac4fe80e40cf2b6c9e2593c956cbcd7504 /plat | |
| parent | 61c418ba751eb38b599e162393dfac501ca912b8 (diff) | |
| download | platform_external_arm-trusted-firmware-35aa1c1e51b62467ac31958983a67ef0d5646acb.tar.gz platform_external_arm-trusted-firmware-35aa1c1e51b62467ac31958983a67ef0d5646acb.tar.bz2 platform_external_arm-trusted-firmware-35aa1c1e51b62467ac31958983a67ef0d5646acb.zip | |
Tegra210: SE: switch SE clock source to CLK_M
In SE suspend, switch SE clock source to CLK_M,
to make sure SE clock is on when saving SE context
Change-Id: I57c559825a3ec8e0cc35f7a389afc458a5eed0cb
Signed-off-by: Leo He <leoh@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Diffstat (limited to 'plat')
| -rw-r--r-- | plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c | 17 |
1 files changed, 6 insertions, 11 deletions
diff --git a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c index 635018dbc..48608583d 100644 --- a/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c +++ b/plat/nvidia/tegra/soc/t210/drivers/se/security_engine.c @@ -927,17 +927,12 @@ static void tegra_se_enable_clocks(void) val &= ~ENTROPY_RESET_BIT; mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_RST_DEVICES_W, val); - if (!tegra_chipid_is_t210_b01()) { - - /* - * T210 SE clock source is turned off in kernel, to simplify - * SE clock source setting, we switch SE clock source to - * CLK_M, SE_CLK_DIVISOR = 0. T210 B01 SE clock source is - * always on, so don't need this setting. - */ - mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, - SE_CLK_SRC_CLK_M); - } + /* + * Switch SE clock source to CLK_M, to make sure SE clock + * is on when saving SE context + */ + mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_RST_CTL_CLK_SRC_SE, + SE_CLK_SRC_CLK_M); /* Enable SE clock */ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V); |