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* Mbed TLS: Remove weak heap implementationAmbroise Vincent2019-04-121-1/+6
| | | | | | | | | | | | The implementation of the heap function plat_get_mbedtls_heap() becomes mandatory for platforms supporting TRUSTED_BOARD_BOOT. The shared Mbed TLS heap default weak function implementation is converted to a helper function get_mbedtls_heap_helper() which can be used by the platforms for their own function implementation. Change-Id: Ic8f2994e25e3d9fcd371a21ac459fdcafe07433e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Remove deprecated plat_crash_console_*Ambroise Vincent2019-04-031-1/+15
| | | | | | | | | | The default implementations are defined in crash_console_helpers.S. The platforms have to define plat_crash_console_*. Implemented placeholders for platforms that were missing helpers. Change-Id: Iea60b6f851956916e421dfd8c34a62d96eb9148e Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* Remove unneeded include paths in PLAT_INCLUDESAntonio Nino Diaz2019-02-011-5/+1
| | | | | | | | Also, update platform_def.h guidelines about includes in the porting guide. Change-Id: I1ae338c9dd3242b309f6d53687ba2cb755d488c3 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Remove duplicated definitions of linker symbolsAntonio Nino Diaz2019-02-012-33/+1
| | | | | | | | | | | | Many parts of the code were duplicating symbols that are defined in include/common/bl_common.h. It is better to only use the definitions in this header. As all the symbols refer to virtual addresses, they have to be uintptr_t, not unsigned long. This has also been fixed in bl_common.h. Change-Id: I204081af78326ced03fb05f69846f229d324c711 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Move BL1 and BL2 private defines to bl_common.hAntonio Nino Diaz2019-01-151-2/+0
| | | | | | | | The definitions in bl1/bl1_private.h and bl2/bl2_private.h are useful for platforms that may need to access them. Change-Id: Ifd1880f855ddafcb3bfcaf1ed4a4e0f121eda174 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-0415-60/+90
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Standardise header guards across codebaseAntonio Nino Diaz2018-11-082-6/+6
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* context_mgmt: Fix MISRA defectsAntonio Nino Diaz2018-11-011-2/+2
| | | | | | | | The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* xlat: Fix compatibility between v1 and v2Antonio Nino Diaz2018-10-262-14/+3
| | | | | | | | | | | | | | | | | | | | | | There are several platforms using arm_setup_page_tables(), which is supposed to be Arm platform only. This creates several dependency problems between platforms. This patch adds the definition XLAT_TABLES_LIB_V2 to the xlat tables lib v2 makefile. This way it is possible to detect from C code which version is being used and include the correct header. The file arm_xlat_tables.h has been renamed to xlat_tables_compat.h and moved to a common folder. This way, when in doubt, this header can be used to guarantee compatibility, as it includes the correct header based on XLAT_TABLES_LIB_V2. This patch also removes the usage of ARM_XLAT_TABLES_V1 from QEMU (so that is now locked in xlat lib v2) and ZynqMP (where it was added as a workaround). Change-Id: Ie1e22a23b44c549603d1402a237a70d0120d3e04 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* qemu: increase PLAT_QEMU_DT_MAX_SIZE to 1 MiBJerome Forissier2018-10-181-1/+1
| | | | | | | | | | | | | Since upstream QEMU commit 14ec3cbd7c1e ("device_tree: Increase FDT_MAX_SIZE to 1 MiB"), which is included in release v2.12.1 and later, BL2 initialization fails with the following error (-3 is -FDT_ERR_NOSPACE): ERROR: Invalid Device Tree at 0x40000000: error -3 Increase PLAT_QEMU_DT_MAX_SIZE accordingly. Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
* Replace S-EL3 references by EL3John Tsichritzis2018-10-101-1/+1
| | | | | | | | | The "Secure" prefix (S-ELx) is valid only for S-EL0 and S-EL1 but is meaningless for EL3, since EL3 is always secure. Hence, the "S" prefix has been removed from wherever it was used as "S-EL3". Change-Id: Icdeac9506d763f9f83d7297c7113aec7b85e9dbe Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* qemu: Migrate to new interfacesAntonio Nino Diaz2018-09-286-186/+8
| | | | | | | | | | | - Remove references to removed build options. - Remove support for LOAD_IMAGE_V2=0. - Migrate to sp_min_early_platform_setup2(). Change-Id: I884399139fb8e2554adeded888969f44672d56c0 Co-authored-by: Jens Wiklander <jens.wiklander@linaro.org> Tested-by: Jens Wiklander <jens.wiklander@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat: qemu: update the early platform setup APIJens Wiklander2018-09-042-6/+7
| | | | | | | | | Replaces deprecated early platform setup APIs * Replaces bl31_early_platform_setup() with bl31_early_platform_setup2() * Replaces bl2_early_platform_setup() with bl2_early_platform_setup2() Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* qemu: make LOAD_IMAGE_V2=1 mandatoryJens Wiklander2018-09-043-87/+7
| | | | | | | | | The QEMU platform has only been used with LOAD_IMAGE_V2=1 for some time now and bit rot has occurred for LOAD_IMAGE_V2=0. To ease the maintenance make LOAD_IMAGE_V2=1 mandatory and remove the platform specific code for LOAD_IMAGE_V2=0. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* libc: Fix all includes in codebaseAntonio Nino Diaz2018-08-222-5/+4
| | | | | | | | | The codebase was using non-standard headers. It is needed to replace them by the correct ones so that we can use the new libc headers. Change-Id: I530f71d9510cb036e69fe79823c8230afe890b9d Acked-by: Sumit Garg <sumit.garg@linaro.org> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Create a library file for libfdtRoberto Vargas2018-08-031-2/+1
| | | | | | | | | TF Makefile was linking all the objects files generated for the fdt library instead of creating a static library that could be used in the linking stage. Change-Id: If3705bba188ec39e1fbf2322a7f2a9a941e1b90d Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* PSCI: Fix types of definitionsAntonio Nino Diaz2018-07-201-8/+9
| | | | | | | | | Also change header guards to fix defects of MISRA C-2012 Rule 21.1. Change-Id: Ied0d4b0e557ef6119ab669d106d2ac5d99620c57 Acked-by: Sumit Garg <sumit.garg@linaro.org> Acked-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1334 from ↵Dimitris Papastamos2018-04-033-20/+22
|\ | | | | | | | | michpappas/tf-issues#572_qemu_dont_use_C_for_crash_console qemu: don't use C functions for the crash console callbacks
| * qemu: don't use C functions for the crash console callbacksMichalis Pappas2018-03-313-20/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the console_pl011_core_* functions directly in the crash console callbacks. This bypasses the MULTI_CONSOLE_API for the crash console (UART1), but allows using the crash console before the C runtime has been initialized (eg to call ASM_ASSERT). This retains backwards compatibility with respect to functionality when the old API is used. Use the MULTI_CONSOLE_API to register UART0 as the boot and runtime console. Fixes ARM-software/tf-issues#572 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* | Merge pull request #1313 from jonathanwright-ARM/jw/MISRA-switch-statementsDimitris Papastamos2018-03-291-0/+3
|\ \ | | | | | | Fix switch statements to comply with MISRA rules
| * | plat: fix switch statements to comply with MISRA rulesJonathan Wright2018-03-261-0/+3
| |/ | | | | | | | | | | | | | | Ensure (where possible) that switch statements in plat comply with MISRA rules 16.1 - 16.7. Change-Id: Ie4a7d2fd10f6141c0cfb89317ea28a755391622f Signed-off-by: Jonathan Wright <jonathan.wright@arm.com>
* | Merge pull request #1325 from ↵Dimitris Papastamos2018-03-293-2/+29
|\ \ | |/ |/| | | | | michpappas/tf-issues#568_qemu_add_ENABLE_STACK_PROTECTOR qemu: Add support for stack canary protection
| * qemu: Add support for stack canary protectionMichalis Pappas2018-03-203-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow qemu users to enable stack protection. Since the virt platform does not provide an RNG, use a basic, timer-based, canary generation, similarly to FVP. Increase SRAM size and BL2 size to fit images when stack protection is enabled. Notice that stack protection is not enabled by default in qemu. Fixes ARM-software/tf-issues#568 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* | qemu: MULTI_CONSOLE_API=0 causes build errorMichalis Pappas2018-03-242-1/+8
| | | | | | | | | | | | | | | | | | Add crash_console_init declaration to console.h Only enable MULTI_CONSOLE_API for AArch64 Fixes ARM-software/tf-issues#571 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* | [PATCH 2/2] qemu: Support MULTI_CONSOLE_APIMichalis Pappas2018-03-227-17/+52
|/ | | | | | | | | | | | | Add support for the new MULTI_CONSOLE_API Crash information is now displayed in both the runtime and crash consoles, if a crash occurs after the runtime console has been enabled Enable MULTI_CONSOLE_API by default on qemu builds Fixes ARM-software/tf-issues#561 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* Merge pull request #1288 from ↵davidcunado-arm2018-03-057-25/+22
|\ | | | | | | | | michpappas/tf-issues#558_qemu_separate_code_and_data qemu: Support SEPARATE_CODE_AND_RODATA
| * qemu: Support SEPARATE_CODE_AND_RODATAMichalis Pappas2018-02-287-25/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update qemu_configure_mmu_##_el to add an additional region for code, marked as MT_CODE | MT_SECURE. Update ro region attributes to NON_EXEC. Update calls to QEMU_CONFIGURE_BLx_MMU() to pass an additional region for code. Update calls to pass regions defined in common_def.h. Increase MAX_MMAP_REGIONS to 10. Enable SEPARATE_CODE_AND_RODATA by default on QEMU builds. Fixes ARM-software/tf-issues#558 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* | qemu: Accessing UART1 causes a data abortMichalis Pappas2018-03-041-1/+1
|/ | | | | | | | | | | | The register address range of UART1 (crash console) are outside the address ranges mapped for MMIO, resulting to an MMU abort when the device registers are accessed. Increase the size of DEVICE1 memory to include the range of UART1. Fixes ARM-software/tf-issues#560 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* Update ULL() macro and instances of ull to comply with MISRADavid Cunado2018-02-271-2/+2
| | | | | | | | | | MISRA C-2012 Rule 7.3 violation: lowercase l shall not be used as literal suffixes. This patch resolves this for the ULL() macro by using ULL suffix instead of the ull suffix. Change-Id: Ia8183c399e74677e676956e8653e82375d0e0a01 Signed-off-by: David Cunado <david.cunado@arm.com>
* qemu: Fix interrupt type checkSanteri Salko2018-02-093-72/+4
| | | | | | | | | | | | | | Function plat_ic_get_pending_interrupt_type() should return interrupt type, not id. The function is used in aarch64 exception handling and currently the irq/fiq forwarding fails if a secure interrupt happens while running normal world. The qemu-specific gic file does not contain any extra functionality so it can be removed and common file can be used instead. fixes arm-software/tf-issues#546 Signed-off-by: Santeri Salko <santeri.salko@gmail.com>
* Merge pull request #1173 from etienne-lms/armv7-qemudavidcunado-arm2018-02-0710-30/+441
|\ | | | | support to boot OP-TEE on AArch32/Armv7+example with Cortex-A15/Qemu
| * qemu: support ARMv7/Cortex-A15Etienne Carriere2018-02-0510-30/+441
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define Qemu AArch32 implementation for some platform functions (core position, secondary boot cores, crash console). These are derived from the AArch64 implementation. BL31 on Qemu is needed only for ARMv8 and later. On ARMv7, BL32 is the first executable image after BL2. Support SP_MIN and OP-TEE as BL32: create a sp_min make script target in Qemu, define mapping for IMAGE_BL32 Minor fix Qemu return value type for plat_get_ns_image_entrypoint(). Qemu model for the Cortex-A15 does not support the virtualization extension although the core expects it. To overcome the issue, Qemu ARMv7 configuration set ARCH_SUPPORTS_VIRTUALIZATION to 0. Add missing AArch32 assembly macro arm_print_gic_regs from ARM platform used by the Qemu platform. Qemu Cortex-A15 model integrates a single cluster with up to 4 cores. Change-Id: I65b44399071d6f5aa40d5183be11422b9ee9ca15 Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Build: change the first parameter of TOOL_ADD_IMG to lowercaseMasahiro Yamada2018-02-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the next commit, I need the image name in lowercase because output files are generally named in lowercase. Unfortunately, TOOL_ADD_IMG takes the first argument in uppercase since we generally use uppercase Make variables. make_helpers/build_macros.mk provides 'uppercase' macro to convert a string into uppercase, but 'lowercase' does not exist. We can implement it if we like, but it would be more straightforward to change the argument of TOOL_ADD_IMG. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | Build: rename FIP_ADD_IMG to TOOL_ADD_IMGMasahiro Yamada2018-02-011-3/+3
|/ | | | | | | Now FIP_ADD_IMG takes care of both fiptool and cert_create symmetrically. Rename it so that it matches the behavior. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* Do not enable SVE on pre-v8.2 platformsDavid Cunado2017-11-301-0/+3
| | | | | | | | | | | | Pre-v8.2 platforms such as the Juno platform does not have the Scalable Vector Extensions implemented and so the build option ENABLE_SVE is set to zero. This has a minor performance improvement with no functional impact. Change-Id: Ib072735db7a0247406f8b60e325b7e28b1e04ad1 Signed-off-by: David Cunado <david.cunado@arm.com>
* Merge pull request #1142 from etienne-lms/qemu-intdavidcunado-arm2017-11-031-11/+30
|\ | | | | qemu: update deprecated interrupt registering
| * qemu: update deprecated interrupt registeringEtienne Carriere2017-11-021-11/+30
| | | | | | | | | | | | | | | | | | Registered interrupts are configured in edge detection as the default previous configuration assumed in previous code. Not target mask required as Qemu BL31 will not send/route SGIs. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge pull request #1147 from etienne-lms/qemu-optee-loaddavidcunado-arm2017-10-271-3/+2
|\ \ | | | | | | qemu/optee: load OP-TEE pageable part 2MB above OP-TEE image
| * | qemu/optee: load OP-TEE pageable part 2MB above OP-TEE imageEtienne Carriere2017-10-261-3/+2
| |/ | | | | | | | | | | | | | | | | | | | | OP-TEE dedicates the end of the Qemu secure DRAM as specific out-of-TEE secure RAM. To support this configuration the trusted firmware should not load OP-TEE resources in this area. To overcome the issue, OP-TEE pageable image is now loaded 2MByte above the secure RAM base address. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge pull request #1143 from etienne-lms/qemu-hpendavidcunado-arm2017-10-262-1/+3
|\ \ | | | | | | qemu: fix holding pen mailbox sequence
| * | qemu: fix holding pen mailbox sequenceEtienne Carriere2017-10-242-1/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | Before this change, plat_secondary_cold_boot_setup reads wake up mailbox as a byte array but through 64bit accesses on unaligned 64bit addresses. In the other hand qemu_pwr_domain_on wakes secondary cores by writing into a 64bit array. This change forces the 64bit mailbox format as PLAT_QEMU_HOLD_ENTRY_SIZE explicitly specifies it. Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
* / qemu: Add support for Trusted Board BootMichalis Pappas2017-10-254-49/+141
|/ | | | | | | | | | This patch adds support for TBB to qemu. An RSA ROT keypair is generated at build time and is included into BL1/BL2. The key and content certificates are read over semihosting. Fixes ARM-software/tf-issues#526 Signed-off-by: Michalis Pappas <mpappas@fastmail.fm>
* qemu: Add OP-TEE extra image parsing supportJens Wiklander2017-08-245-0/+111
| | | | | | | | | | OP-TEE may have extra images to be loaded. Load them one by one and do the parsing. In this patch, ARM TF need to load up to 3 images for OP-TEE: header, pager and pages images. Header image is the info about optee os and images. Pager image include pager code and data. Paged image include the paging parts using virtual memory. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* qemu: replace deprecated plat_psci_common.cJens Wiklander2017-08-241-1/+1
| | | | | | | Change to compile with new plat/common/plat_psci_common.c instead of the old deprecated plat/common/aarch64/plat_psci_common.c Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* qemu: replace deprecated ADDR_SPACE_SIZEJens Wiklander2017-08-241-1/+2
| | | | | | | Replaces the deprecated ADDR_SPACE_SIZE with PLAT_PHY_ADDR_SPACE_SIZE and PLAT_VIRT_ADDR_SPACE_SIZE. Signed-off-by: Jens Wiklander <jens.wiklander@linaro.org>
* qemu: Add LOAD_IMAGE_V2 supportFu Wei2017-08-166-7/+233
| | | | | | | | | | | | | The generic LOAD_IMAGE_V2 framework has been merged and enable for almost all the arm platform. Because qemu platform doesn't share those common files with arm, QEMU haven't got this support yet. This patch add all the necessary code the files for adding LOAD_IMAGE_V2 support on QEMU and enable it as default. Fixes ARM-software/tf-issues#507 Signed-off-by: Fu Wei <fu.wei@linaro.org>
* qemu: use translation tables library v2 as default.Fu Wei2017-07-312-3/+15
| | | | | | | | | | | | | Almost all the arm platform has switch to translation tables library v2 as default. Because qemu platform doesn't use arm_common.mk like other arm platforms, QEMU haven't switched to v2 yet. This patch adds all the necessary code for adding translation tables library v2 support on QEMU and use it as default. Fixes ARM-software/tf-issues#508 Signed-off-by: Fu Wei <fu.wei@linaro.org>
* Fix order of remaining platform #includesIsla Mitchell2017-07-145-5/+5
| | | | | | | | | This fix modifies the order of system includes to meet the ARM TF coding standard. There are some exceptions to this change in order to retain header groupings and where there are headers within #if statements. Change-Id: Ib5b668c992d817cc860e97b29e16ef106d17e404 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
* Merge pull request #927 from jeenu-arm/state-switchdavidcunado-arm2017-05-111-5/+1
|\ | | | | Execution state switch
| * Add macro to check whether the CPU implements an ELJeenu Viswambharan2017-05-021-5/+1
| | | | | | | | | | | | | | Replace all instances of checks with the new macro. Change-Id: I0eec39b9376475a1a9707a3115de9d36f88f8a2a Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
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