aboutsummaryrefslogtreecommitdiffstats
path: root/plat/nvidia
Commit message (Expand)AuthorAgeFilesLines
* spe: Use generic console_t data structureAndre Przywara2020-02-253-12/+7
* LS 16550: Use generic console_t data structureAndre Przywara2020-02-251-2/+2
* 16550: Use generic console_t data structureAndre Przywara2020-02-254-7/+7
* Tegra: spe: uninit console on a timeoutVarun Wadekar2020-02-201-10/+27
* Tegra: handler to check support for System SuspendVarun Wadekar2020-02-206-2/+60
* Tegra: bpmp_ipc: improve cyclomatic complexityVarun Wadekar2020-02-201-30/+25
* Tegra: platform handler to relocate BL32 imageVarun Wadekar2020-02-205-36/+52
* Tegra: common: improve cyclomatic complexityVarun Wadekar2020-02-201-13/+11
* Tegra210: secure PMC hardware blockkalyani chidambaram2020-02-202-1/+19
* Tegra: delay_timer: support for physical secure timerVarun Wadekar2020-02-201-9/+37
* Tegra194: memctrl: lock mc stream id security configPritesh Raithatha2020-02-201-109/+109
* Tegra210: resume PMC hardware block for all platformskalyani chidambaram2020-02-201-3/+4
* Tegra: macro for legacy WDT FIQ handlingVarun Wadekar2020-02-201-0/+7
* Tegra186: enable higher performance non-cacheable load forwardingVarun Wadekar2020-02-201-0/+4
* Tegra210: enable higher performance non-cacheable load forwardingVarun Wadekar2020-02-201-0/+3
* Tegra194: mce: declare nvg_roc_clean_cache_trbits()Varun Wadekar2020-02-051-0/+1
* Tegra186: memctrl: lock stream id security configPritesh Raithatha2020-01-311-44/+44
* Tegra194: remove support for simulated system suspendVarun Wadekar2020-01-312-73/+20
* Tegra194: mce: fix multiple MISRA issuesVarun Wadekar2020-01-313-236/+237
* Tegra: bpmp: fix multiple MISRA issuesVarun Wadekar2020-01-313-26/+25
* Tegra194: se: fix multiple MISRA issuesVarun Wadekar2020-01-312-7/+14
* Tegra: compile PMC driver for Tegra132/Tegra210 platformsVarun Wadekar2020-01-316-5/+18
* Tegra: memctrl_v2: remove weakly defined TZDRAM setup handlerVarun Wadekar2020-01-311-12/+1
* Tegra: remove weakly defined per-platform SiP handlerVarun Wadekar2020-01-311-26/+1
* Tegra: remove weakly defined PSCI platform handlersVarun Wadekar2020-01-316-91/+85
* Tegra: remove weakly defined platform setup handlersVarun Wadekar2020-01-314-31/+63
* Tegra: per-SoC DRAM base valuesVarun Wadekar2020-01-315-6/+27
* Enable -Wredundant-decls warning checkMadhukar Pappireddy2020-01-282-7/+7
* Tegra194: enable spe-console functionalityVarun Wadekar2020-01-281-1/+1
* Tegra194: mce: remove unused NVG functionsVarun Wadekar2020-01-232-99/+6
* Tegra194: support for NVG interface v6.6Varun Wadekar2020-01-231-102/+188
* Tegra194: smmu: add PCIE0R1 mc reg to system suspend save listPritesh Raithatha2020-01-232-3/+5
* Tegra194: enable driver for general purpose DMA engineVarun Wadekar2020-01-233-1/+14
* Tegra194: access XUSB_PADCTL registers on Si/FPGA platformsVarun Wadekar2020-01-232-24/+30
* Tegra194: organize the memory/mmio map to make it linearVarun Wadekar2020-01-232-37/+35
* Tegra194: memctrl: enable mc sid OVERRIDE for PCIE0R1Pritesh Raithatha2020-01-231-0/+2
* Tegra194: support for boot params wider than 32-bitsSteven Kao2020-01-232-6/+19
* Tegra194: memctrl: set reorder depth limit for PCIE blocksPuneet Saxena2020-01-232-0/+24
* Tegra194: memctrl: program MC_TXN_OVERRIDE reg for PTCR, MPCORE and MIUPritesh Raithatha2020-01-231-0/+22
* Tegra194: memctrl: set CGID_TAG_ADR instead of CGID_TAG_DEFAULTPritesh Raithatha2020-01-231-157/+119
* Tegra194: memctrl: update mss reprogramming as HW PROD settingsPuneet Saxena2020-01-232-98/+164
* Tegra194: memctrl: Disable PVARDC coalescerArto Merilainen2020-01-232-1/+13
* Tegra194: memctrl: force seswr/rd transactions as passsthru & coherentPuneet Saxena2020-01-231-2/+6
* Tegra194: Request CG7 from last core in clusterVignesh Radhakrishnan2020-01-231-0/+2
* Tegra194: toggle SE clock during context save/restoresteven kao2020-01-234-1/+41
* Tegra: bpmp: fix header file pathsVarun Wadekar2020-01-232-4/+4
* Tegra194: platform handler for entering CPU standby stateVarun Wadekar2020-01-171-8/+31
* Tegra194: memctrl: force viw and vifalr/w transactions as non-coherentKrishna Reddy2020-01-172-16/+13
* Tegra194: memctrl: fix bug in client order id reg value generationKrishna Reddy2020-01-172-9/+6
* Tegra194: memctrl: enable mc coalescerPritesh Raithatha2020-01-172-1/+7