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* Fixup register handling in aarch32 reset_handlerHeiko Stuebner2019-03-081-3/+3
| | | | | | | | | | | | | | | | The BL handover interface stores the bootloader arguments in registers r9-r12, so when the reset_handler stores the lr pointer in r10 it clobers one of the arguments. Adapt to use r8 and adapt the comment about registers allowed to clober. I've checked aarch32 reset_handlers and none seem to use higher registers as far as I can tell. Fixes: a6f340fe58b9 ("Introduce the new BL handover interface") Cc: Soby Mathew <soby.mathew@arm.com> Signed-off-by: Heiko Stuebner <heiko@sntech.de>
* Merge pull request #1751 from vwadekar/tegra-scatter-file-supportAntonio Niño Díaz2019-03-012-2/+4
|\ | | | | Tegra scatter file support
| * Tegra: Support for scatterfile for the BL31 imageVarun Wadekar2019-02-272-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides support for using the scatterfile format as the linker script with the 'armlink' linker for Tegra platforms. In order to enable the scatterfile usage the following changes have been made: * provide mapping for ld.S symbols in bl_common.h * include bl_common.h from all the affected files * update the makefile rules to use the scatterfile and armlink to compile BL31 * update pubsub.h to add sections to the scatterfile NOTE: THIS CHANGE HAS BEEN VERIFIED WITH TEGRA PLATFORMS ONLY. Change-Id: I7bb78b991c97d74a842e5635c74cb0b18e0fce67 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Merge pull request #1849 from loumay-arm/lm/a73_errataAntonio Niño Díaz2019-03-012-0/+44
|\ \ | | | | | | Cortex-A73: Implement workaround for errata 852427
| * | Cortex-A73: Implement workaround for errata 852427Louis Mayencourt2019-02-282-0/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | In AArch32, execution of 2 instructions with opposite condition code might lead to either a data corruption or a CPU deadlock. Set the bit 12 of the Diagnostic Register to prevent this. Change-Id: I22b4f25fe933e2942fd785e411e7c0aa39d5c1f4 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | | Merge pull request #1845 from ambroise-arm/av/errataAntonio Niño Díaz2019-03-016-5/+488
|\ \ \ | |/ / |/| | Apply workarounds for errata of Cortex-A53, A55 and A57
| * | Cortex-A53: Workarounds for 819472, 824069 and 827319Ambroise Vincent2019-02-283-2/+122
| | | | | | | | | | | | | | | | | | | | | | | | The workarounds for these errata are so closely related that it is better to only have one patch to make it easier to understand. Change-Id: I0287fa69aefa8b72f884833f6ed0e7775ca834e9 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A57: Implement workaround for erratum 817169Ambroise Vincent2019-02-283-0/+52
| | | | | | | | | | | | | | | Change-Id: I25f29a275ecccd7d0c9d33906e6c85967caa767a Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A57: Implement workaround for erratum 814670Ambroise Vincent2019-02-283-2/+79
| | | | | | | | | | | | | | | Change-Id: Ice3dcba8c46cea070fd4ca3ffb32aedc840589ad Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 903758Ambroise Vincent2019-02-282-0/+42
| | | | | | | | | | | | | | | Change-Id: I07e69061ba7a918cdfaaa83fa3a42dee910887d7 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 846532Ambroise Vincent2019-02-282-0/+46
| | | | | | | | | | | | | | | Change-Id: Iacb6331c1f6b27340e71279f92f147ebbc71862f Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 798797Ambroise Vincent2019-02-282-0/+42
| | | | | | | | | | | | | | | Change-Id: Ic42b37b8500d5e592af2b9fe130f35a0e2db4d14 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 778703Ambroise Vincent2019-02-282-0/+57
| | | | | | | | | | | | | | | Change-Id: I094e5cb2c44618e7a4116af5fbb6b18078a79951 Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
| * | Cortex-A55: Implement workaround for erratum 768277Ambroise Vincent2019-02-282-1/+48
| |/ | | | | | | | | Change-Id: Iebd45ef5e39ee7080235fb85414ce5b2e776f90c Signed-off-by: Ambroise Vincent <ambroise.vincent@arm.com>
* | Add workaround for errata 1073348 for Cortex-A76Louis Mayencourt2019-02-262-0/+42
| | | | | | | | | | | | | | | | | | Concurrent instruction TLB miss and mispredicted return instruction might fetch wrong instruction stream. Set bit 6 of CPUACTLR_EL1 to prevent this. Change-Id: I2da4f30cd2df3f5e885dd3c4825c557492d1ac58 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 1220197 for Cortex-A76Louis Mayencourt2019-02-262-0/+44
| | | | | | | | | | | | | | | | | | Streaming store under specific conditions might cause deadlock or data corruption. Set bit 25:24 of CPUECTLR_EL1, which disables write streaming to the L2 to prevent this. Change-Id: Ib5cabb997b35ada78b27e75787afd610ea606dcf Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 1130799 for Cortex-A76Louis Mayencourt2019-02-262-1/+48
| | | | | | | | | | | | | | | | | | | | TLBI VAAE1 or TLBI VAALE1 targeting a page within hardware page aggregated address translation data in the L2 TLB might cause corruption of address translation data. Set bit 59 of CPUACTLR2_EL1 to prevent this. Change-Id: I59f3edea54e87d264e0794f5ca2a8c68a636e586 Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 790748 for Cortex-A75Louis Mayencourt2019-02-262-0/+44
| | | | | | | | | | | | | | | | Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 764081 of Cortex-A75Louis Mayencourt2019-02-262-1/+48
| | | | | | | | | | | | | | | | | | Implicit Error Synchronization Barrier (IESB) might not be correctly generated in Cortex-A75 r0p0. To prevent this, IESB are enabled at all expection levels. Change-Id: I2a1a568668a31e4f3f38d0fba1d632ad9939e5ad Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* | Add workaround for errata 855423 of Cortex-A73Louis Mayencourt2019-02-262-2/+51
|/ | | | | | | | Broadcast maintainance operations might not be correctly synchronized between cores. Set bit 7 of S3_0_C15_C0_2 to prevent this. Change-Id: I67fb62c0b458d44320ebaedafcb8495ff26c814b Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
* Rename Cortex-Helios to Neoverse E1John Tsichritzis2019-02-191-18/+18
| | | | | Change-Id: I1adcf195c0ba739002f3a59e805c782dd292ccba Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Rename Cortex-Helios filenames to Neoverse E1John Tsichritzis2019-02-191-0/+0
| | | | | Change-Id: I33bdb9df0462b056adbd00922b2e73eb720560b3 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Rename Cortex-Ares to Neoverse N1John Tsichritzis2019-02-193-48/+48
| | | | | Change-Id: Ideb49011da35f39ff1959be6f5015fa212ca2b6b Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Rename Cortex-Ares filenames to Neoverse N1John Tsichritzis2019-02-192-0/+0
| | | | | Change-Id: I0bb5aca9bb272332340b5baefc473a01f8a27896 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Sanitise includes across codebaseAntonio Nino Diaz2019-01-0420-33/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enforce full include path for includes. Deprecate old paths. The following folders inside include/lib have been left unchanged: - include/lib/cpus/${ARCH} - include/lib/el3_runtime/${ARCH} The reason for this change is that having a global namespace for includes isn't a good idea. It defeats one of the advantages of having folders and it introduces problems that are sometimes subtle (because you may not know the header you are actually including if there are two of them). For example, this patch had to be created because two headers were called the same way: e0ea0928d5b7 ("Fix gpio includes of mt8173 platform to avoid collision."). More recently, this patch has had similar problems: 46f9b2c3a282 ("drivers: add tzc380 support"). This problem was introduced in commit 4ecca33988b9 ("Move include and source files to logical locations"). At that time, there weren't too many headers so it wasn't a real issue. However, time has shown that this creates problems. Platforms that want to preserve the way they include headers may add the removed paths to PLAT_INCLUDES, but this is discouraged. Change-Id: I39dc53ed98f9e297a5966e723d1936d6ccf2fc8f Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* AArch64: Use SSBS for CVE_2018_3639 mitigationJeenu Viswambharan2018-12-101-2/+11
| | | | | | | | | | | | | | | | | | | | | | | The Armv8.5 extensions introduces PSTATE.SSBS (Speculation Store Bypass Safe) bit to mitigate against Variant 4 vulnerabilities. Although an Armv8.5 feature, this can be implemented by CPUs implementing earlier version of the architecture. With this patch, when both PSTATE.SSBS is implemented and DYNAMIC_WORKAROUND_CVE_2018_3639 is active, querying for SMCCC_ARCH_WORKAROUND_2 via. SMCCC_ARCH_FEATURES call would return 1 to indicate that mitigation on the PE is either permanently enabled or not required. When SSBS is implemented, SCTLR_EL3.DSSBS is initialized to 0 at reset of every BL stage. This means that EL3 always executes with mitigation applied. For Cortex A76, if the PE implements SSBS, the existing mitigation (by using a different vector table, and tweaking CPU ACTLR2) is not used. Change-Id: Ib0386c5714184144d4747951751c2fc6ba4242b6 Signed-off-by: Jeenu Viswambharan <jeenu.viswambharan@arm.com>
* Fix MISRA defects in workaround and errata frameworkAntonio Nino Diaz2018-10-293-9/+14
| | | | | | | No functional changes. Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Fix MISRA defects in extension libsAntonio Nino Diaz2018-10-291-2/+2
| | | | | | | No functional changes. Change-Id: I2f28f20944f552447ac4e9e755493cd7c0ea1192 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Make errata reporting mandatory for CPU filesSoby Mathew2018-10-299-0/+84
| | | | | | | | | | | | | Previously the errata reporting was optional for CPU operation files and this was achieved by making use of weak reference to resolve to 0 if the symbol is not defined. This is error prone when adding new CPU operation files and weak references are problematic when fixing up dynamic relocations. Hence this patch removes the weak reference and makes it mandatory for the CPU operation files to define the errata reporting function. Change-Id: I8af192e19b85b7cd8c7579e52f8f05a4294e5396 Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* ti: k3: common: Do not disable cache on TI K3 core powerdownAndrew F. Davis2018-10-161-0/+4
| | | | | | | | | Leave the caches on and explicitly flush any data that may be stale when the core is powered down. This prevents non-coherent interconnect access which has negative side- effects on AM65x. Signed-off-by: Andrew F. Davis <afd@ti.com>
* Fix the Cortex-ares errata reporting function nameSoby Mathew2018-09-101-2/+2
| | | | | | | | This patch fixes the name of the Cortex-ares errata function which was previously named `cortex_a72_errata_report` which was an error. Change-Id: Ia124df4628261021baa8d9a30308bc286d45712b Signed-off-by: Soby Mathew <soby.mathew@arm.com>
* cpus: denver: Implement static workaround for CVE-2018-3639Varun Wadekar2018-09-041-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For Denver CPUs, this approach enables the mitigation during EL3 initialization, following every PE reset. No mechanism is provided to disable the mitigation at runtime. This approach permanently mitigates the EL3 software stack only. Other software components are responsible to enable it for their exception levels. TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN3 and earlier: * By setting bit 11 (Disable speculative store buffering) of `ACTLR_EL3` * By setting bit 9 (Disable speculative memory disambiguation) of `ACTLR_EL3` TF-A implements this approach for the Denver CPUs with DENVER_MIDR_PN4 and later: * By setting bit 18 (Disable speculative store buffering) of `ACTLR_EL3` * By setting bit 17 (Disable speculative memory disambiguation) of `ACTLR_EL3` Change-Id: If1de96605ce3f7b0aff5fab2c828e5aecb687555 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* cpus: denver: reset power state to 'C1' on bootVarun Wadekar2018-09-041-0/+9
| | | | | | | | | Denver CPUs expect the power state field to be reset to 'C1' during boot. This patch updates the reset handler to reset the ACTLR_.PMSTATE field to 'C1' state during CPU boot. Change-Id: I7cb629627a4dd1a30ec5cbb3a5e90055244fe30c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* denver: use plat_my_core_pos() to get core positionVarun Wadekar2018-09-041-4/+7
| | | | | | | | | | | | | | | The current functions to disable and enable Dynamic Code Optimizer (DCO) assume that all denver cores are in the same cluster. They ignore AFF1 field of the mpidr_el1 register, which leads to incorect logical core id calculation. This patch calls the platform handler, plat_my_core_pos(), to get the logical core id to disable/enable DCO for the core. Original change by: Krishna Sitaraman <ksitaraman@nvidia.com> Change-Id: I45fbd1f1eb032cc1db677a4fdecc554548b4a830 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* DSU erratum 936184 workaround: bug fixJohn Tsichritzis2018-08-231-7/+17
| | | | | | | | The initial implementation was corrupting registers that it shouldn't. Now this is fixed. Change-Id: Iaa407c18e668b2d9381391bf10d6876fe936aded Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Merge pull request #1388 from vwadekar/report-cve-2017-5715Dimitris Papastamos2018-08-201-5/+55
|\ | | | | cpus: denver: report CVE_2017_5715 mitigation to higher layers
| * cpus: denver: report CVE_2017_5715 mitigation to higher layersVarun Wadekar2018-08-171-5/+55
| | | | | | | | | | | | | | | | | | | | | | This patch uses the 'declare_cpu_ops_wa' macro, to set the check function, to report that Denver cores are mitigated. Denver cores are vulnerable to this anomaly and require the mitigation to be enabled always. Change-Id: I1bb6eefdec8c01fb8b645e112f8d04d4bb8811ef Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | DSU erratum 936184 workaroundJohn Tsichritzis2018-08-175-5/+114
|/ | | | | | | | | | | | | | | | If the system is in near idle conditions, this erratum could cause a deadlock or data corruption. This patch applies the workaround that prevents this. This DSU erratum affects only the DSUs that contain the ACP interface and it was fixed in r2p0. The workaround is applied only to the DSUs that are actually affected. Link to respective Arm documentation: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.epm138168/index.html Change-Id: I033213b3077685130fc1e3f4f79c4d15d7483ec9 Signed-off-by: John Tsichritzis <john.tsichritzis@arm.com>
* Add initial CPU support for Cortex-HeliosJoel Hutton2018-07-111-0/+34
| | | | | | Change-Id: Ic0486131c493632eadf329f80b0b5904aed5e4ef Signed-off-by: Joel Hutton <joel.hutton@arm.com> Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Add initial CPU support for Cortex-DeimosJoel Hutton2018-07-111-0/+51
| | | | | | Change-Id: I2c4b06423fcd96af9351b88a5e2818059f981f1b Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com> Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Add end_vector_entry assembler macroRoberto Vargas2018-07-114-80/+80
| | | | | | | | | | | | | | Check_vector_size checks if the size of the vector fits in the size reserved for it. This check creates problems in the Clang assembler. A new macro, end_vector_entry, is added and check_vector_size is deprecated. This new macro fills the current exception vector until the next exception vector. If the size of the current vector is bigger than 32 instructions then it gives an error. Change-Id: Ie8545cf1003a1e31656a1018dd6b4c28a4eaf671 Signed-off-by: Roberto Vargas <roberto.vargas@arm.com>
* cpulib: Add ISBs or comment why they are unneededDimitris Papastamos2018-06-194-0/+4
| | | | | Change-Id: I18a41bb9fedda635c3c002a7f112578808410ef6 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Fix MISRA Rule 5.7 Part 1Daniel Boulby2018-06-121-4/+4
| | | | | | | | | | | | | | | | | | | | Rule 5.7: A tag name shall be a unique identifier There were 2 amu_ctx struct type definitions: - In lib/extensions/amu/aarch64/amu.c - In lib/cpus/aarch64/cpuamu.c Renamed the latter to cpuamu_ctx to avoid this name clash To avoid violation of Rule 8.3 also change name of function amu_ctxs to unique name (cpuamu_ctxs) since it now returns a different type (cpuamu_ctx) than the other amu_ctxs function Fixed for: make LOG_LEVEL=50 PLAT=fvp Change-Id: Ieeb7e390ec2900fd8b775bef312eda93804a43ed Signed-off-by: Daniel Boulby <daniel.boulby@arm.com>
* Merge pull request #1397 from dp-arm/dp/cortex-a76Dimitris Papastamos2018-06-084-1/+461
|\ | | | | Add support for Cortex-A76 and Cortex-Ares
| * Implement dynamic mitigation for CVE-2018-3639 on Cortex-A76Dimitris Papastamos2018-06-081-2/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Cortex-A76 implements SMCCC_ARCH_WORKAROUND_2 as defined in "Firmware interfaces for mitigating cache speculation vulnerabilities System Software on Arm Systems"[0]. Dynamic mitigation for CVE-2018-3639 is enabled/disabled by setting/clearning bit 16 (Disable load pass store) of `CPUACTLR2_EL1`. NOTE: The generic code that implements dynamic mitigation does not currently implement the expected semantics when dispatching an SDEI event to a lower EL. This will be fixed in a separate patch. [0] https://developer.arm.com/cache-speculation-vulnerability-firmware-specification Change-Id: I8fb2862b9ab24d55a0e9693e48e8be4df32afb5a Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * Implement Cortex-Ares 1043202 erratum workaroundDimitris Papastamos2018-06-082-2/+74
| | | | | | | | | | | | | | The workaround uses the instruction patching feature of the Ares cpu. Change-Id: I868fce0dc0e8e41853dcce311f01ee3867aabb59 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * Add AMU support for Cortex-AresDimitris Papastamos2018-06-082-4/+51
| | | | | | | | | | Change-Id: Ia170c12d3929a616ba80eb7645c301066641f5cc Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
| * Add support for Cortex-Ares and Cortex-A76 CPUsIsla Mitchell2018-06-082-0/+102
| | | | | | | | | | | | | | | | | | Both Cortex-Ares and Cortex-A76 CPUs use the ARM DynamIQ Shared Unit (DSU). The power-down and power-up sequences are therefore mostly managed in hardware, and required software operations are simple. Change-Id: I3a9447b5bdbdbc5ed845b20f6564d086516fa161 Signed-off-by: Isla Mitchell <isla.mitchell@arm.com>
* | Fast path SMCCC_ARCH_WORKAROUND_1 calls from AArch32Dimitris Papastamos2018-06-071-11/+12
|/ | | | | | | | | | | | | | When SMCCC_ARCH_WORKAROUND_1 is invoked from a lower EL running in AArch32 state, ensure that the SMC call will take a shortcut in EL3. This minimizes the time it takes to apply the mitigation in EL3. When lower ELs run in AArch32, it is preferred that they execute the `BPIALL` instruction to invalidate the BTB. However, on some cores the `BPIALL` instruction may be a no-op and thus would benefit from making the SMCCC_ARCH_WORKAROUND_1 call go through the fast path. Change-Id: Ia38abd92efe2c4b4a8efa7b70f260e43c5bda8a5 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
* Add support for dynamic mitigation for CVE-2018-3639Dimitris Papastamos2018-05-236-4/+42
| | | | | | | | | | | | | | | | | | Some CPUS may benefit from using a dynamic mitigation approach for CVE-2018-3639. A new SMC interface is defined to allow software executing in lower ELs to enable or disable the mitigation for their execution context. It should be noted that regardless of the state of the mitigation for lower ELs, code executing in EL3 is always mitigated against CVE-2018-3639. NOTE: This change is a compatibility break for any platform using the declare_cpu_ops_workaround_cve_2017_5715 macro. Migrate to the declare_cpu_ops_wa macro instead. Change-Id: I3509a9337ad217bbd96de9f380c4ff8bf7917013 Signed-off-by: Dimitris Papastamos <dimitris.papastamos@arm.com>
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