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* FVP: Add BL2 hash calculation in BL1Alexei Fedorov2020-03-252-0/+9
| | | | | | | | This patch provides support for measured boot by adding calculation of BL2 image hash in BL1 and writing these data in TB_FW_CONFIG DTB. Change-Id: Ic074a7ed19b14956719c271c805b35d147b7cec1 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* Merge "Fix 'tautological-constant-compare' error" into integrationMark Dykes2020-03-251-2/+2
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| * Fix 'tautological-constant-compare' errorManish V Badarkhe2020-03-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed below 'tautological-constant-compare' error when building the source code with latest clang compiler <clang version 11.0.0>. plat/common/plat_psci_common.c:36:2: error: converting the result of '<<' to a boolean always evaluates to true [-Werror,-Wtautological-constant-compare] PMF_STORE_ENABLE) ^ include/lib/pmf/pmf.h:28:29: note: expanded from macro 'PMF_STORE_ENABLE' PMF_STORE_ENABLE (1 << 0) This error is observed beacuse of CASSERT placed in "PMF_DEFINE_CAPTURE_TIMESTAMP" which do below stuff: CASSERT(_flags, select_proper_config); where _flags = PMF_STORE_ENABLE (1 << 0) which always results true. Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ifa82ea202496a23fdf1d27ea1798d1f1b583a021
* | Merge "context: TPIDR_EL2 register not saved/restored" into integrationManish Pandey2020-03-241-2/+4
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| * context: TPIDR_EL2 register not saved/restoredOlivier Deprez2020-03-201-2/+4
| | | | | | | | | | | | | | | | TPIDR_EL2 is missing from the EL2 state register save/restore sequence. This patch adds it to the context save restore routines. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I35fc5ee82f97b72bcedac57c791312e7b3a45251
* | raw_nand: correct static analysis tool warningYann Gautier2020-03-231-1/+2
| | | | | | | | | | | | | | | | | | Correct the following warning given by sparse tool: include/drivers/raw_nand.h:158:3: warning: symbol '__packed' was not declared. Should it be static? Change-Id: I03bd9a8aee5cdc5212ce5225be8033f1a6e92bd9 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | spd: tlkd: support new TLK SMCs for RPMB serviceMustafa Yigit Bilgen2020-03-211-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support to handle following TLK SMCs: {TLK_SET_BL_VERSION, TLK_LOCK_BL_INTERFACE, TLK_BL_RPMB_SERVICE} These SMCs need to be supported in ATF in order to forward them to TLK. Otherwise, these functionalities won't work. Brief: TLK_SET_BL_VERSION: This SMC is issued by the bootloader to supply its version to TLK. TLK can use this to prevent rollback attacks. TLK_LOCK_BL_INTERFACE: This SMC is issued by bootloader before handing off execution to the OS. This allows preventing sensitive SMCs being used by the OS. TLK_BL_RPMB_SERVICE: bootloader issues this SMC to sign or verify RPMB frames. Tested by: Tests TLK can receive the new SMCs issued by bootloader Change-Id: I57c2d189a5f7a77cea26c3f8921866f2a6f0f944 Signed-off-by: Mustafa Yigit Bilgen <mbilgen@nvidia.com>
* | Merge "el3_entrypoint_common: avoid overwriting arg3" into integrationManish Pandey2020-03-191-1/+9
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| * | el3_entrypoint_common: avoid overwriting arg3Yann Gautier2020-02-211-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At each BL entry point, the registers r9 to r12 are used to save info from the previous BL parameters put in r0 to r3. But zeromem uses r12, leading to a corruption of arg3. Therefore this change copies r12 to r7 before zeromem() call and restores r12 afterwards. It may be better to save it in r7 in el3_arch_init_common and not at the entrypoint as r7 could be used in other functions, especially platform ones. This is a fix for Task T661. Change-Id: Icc11990c69b5d4c542d08aca1a77b1f754b61a53 Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | tlkd: remove system off/reset handlersVarun Wadekar2020-03-181-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TLK does not participate in the system off/reset process and so has no use for the SYSTEM_OFF/RESET notifications. This patch removes the system off/reset handlers as a result. Change-Id: Icf1430b1400cea88000e6d54426eb604a43cbe6c Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | Tegra194: enable dual execution for EL2 and EL3Kalyani Chidambaram2020-03-181-0/+5
| |/ |/| | | | | | | | | | | | | This patch enables dual execution optimized translations for EL2 and EL3 CPU exception levels. Change-Id: I28fe98bb05687400f247e94adf44a1f3a85c38b1 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | Merge changes from topic "rpix-multi-console" into integrationSandrine Bailleux2020-03-181-5/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: rpi: docs: Update maintainers file to new RPi directory scheme rpi: console: Autodetect Mini-UART vs. PL011 configuration rpi3: build: Include GPIO driver in all BL stages rpi: Allow using PL011 UART for RPi3/RPi4 rpi3: console: Use same "clock-less" setup scheme as RPi4 rpi3: gpio: Simplify GPIO setup
| * | rpi3: gpio: Simplify GPIO setupAndre Przywara2020-03-171-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is really no reason to use and pass around a struct when its only member is the (fixed) base address. Remove the struct and just use the base address on its own inside the GPIO driver. Then set the base address automatically. This simplifies GPIO setup for users, which now don't need to deal with zeroing a struct and setting the base address anymore. Change-Id: I3060f7859e3f8ef9a24cc8fb38307b5da943f127 Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | Implement SMCCC_ARCH_SOC_ID SMC callManish V Badarkhe2020-03-173-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented SMCCC_ARCH_SOC_ID call in order to get below SOC information: 1. SOC revision 2. SOC version Implementation done using below SMCCC specification document: https://developer.arm.com/docs/den0028/c Signed-off-by: Manish V Badarkhe <Manish.Badarkhe@arm.com> Change-Id: Ie0595f1c345a6429a6fb4a7f05534a0ca9c9a48b
* | | Merge "SPMD: Add support for SPCI_ID_GET" into integrationSandrine Bailleux2020-03-131-0/+5
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| * | | SPMD: Add support for SPCI_ID_GETMax Shvetsov2020-03-121-0/+5
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces the `SPCI_ID_GET` interface which will return the ID of the calling SPCI component. Returns 0 for requests from the non-secure world and the SPCI component ID as specified in the manifest for secure world requests. Change-Id: Icf81eb1d0e1d7d5c521571e04972b6e2d356e0d1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com> Signed-off-by: Marc Bonnici <marc.bonnici@arm.com>
* | | Merge changes from topic "mp/enhanced_pal_hw" into integrationMark Dykes2020-03-122-2/+11
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat/arm/fvp: populate pwr domain descriptor dynamically fconf: Extract topology node properties from HW_CONFIG dtb fconf: necessary modifications to support fconf in BL31 & SP_MIN fconf: enhancements to firmware configuration framework
| * | | fconf: necessary modifications to support fconf in BL31 & SP_MINMadhukar Pappireddy2020-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Necessary infrastructure added to integrate fconf framework in BL31 & SP_MIN. Created few populator() functions which parse HW_CONFIG device tree and registered them with fconf framework. Many of the changes are only applicable for fvp platform. This patch: 1. Adds necessary symbols and sections in BL31, SP_MIN linker script 2. Adds necessary memory map entry for translation in BL31, SP_MIN 3. Creates an abstraction layer for hardware configuration based on fconf framework 4. Adds necessary changes to build flow (makefiles) 5. Minimal callback to read hw_config dtb for capturing properties related to GIC(interrupt-controller node) 6. updates the fconf documentation Change-Id: Ib6292071f674ef093962b9e8ba0d322b7bf919af Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
| * | | fconf: enhancements to firmware configuration frameworkMadhukar Pappireddy2020-03-111-2/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A populate() function essentially captures the value of a property, defined by a platform, into a fconf related c structure. Such a callback is usually platform specific and is associated to a specific configuration source. For example, a populate() function which captures the hardware topology of the platform can only parse HW_CONFIG DTB. Hence each populator function must be registered with a specific 'config_type' identifier. It broadly represents a logical grouping of configuration properties which is usually a device tree source file. Example: > TB_FW: properties related to trusted firmware such as IO policies, base address of other DTBs, mbedtls heap info etc. > HW_CONFIG: properties related to hardware configuration of the SoC such as topology, GIC controller, PSCI hooks, CPU ID etc. This patch modifies FCONF_REGISTER_POPULATOR macro and fconf_populate() to register and invoke the appropriate callbacks selectively based on configuration type. Change-Id: I6f63b1fd7a8729c6c9137d5b63270af1857bb44a Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | Merge "Use Speculation Barrier instruction for v8.5 cores" into integrationMark Dykes2020-03-122-1/+11
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| * | | | Use Speculation Barrier instruction for v8.5 coresMadhukar Pappireddy2020-03-112-1/+11
| |/ / / | | | | | | | | | | | | | | | | Change-Id: Ie1018bfbae2fe95c699e58648665baa75e862000 Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | / / spd: tlkd: secure timer interrupt handlerVarun Wadekar2020-03-111-0/+2
| |/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds an interrupt handler for TLK. On receiving an interrupt, the source of the interrupt is determined and the interrupt is marked complete. The IRQ number is passed to TLK along with a special SMC function ID. TLK issues an SMC to notify completion of the interrupt handler in the S-EL1 world. Change-Id: I76f28cee6537245c5e448d2078f86312219cea1a Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
* | | Merge "Fix crash dump for lower EL" into integrationMark Dykes2020-03-112-2/+7
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| * | | Fix crash dump for lower ELAlexei Fedorov2020-03-062-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a fix for incorrect crash dump data for lower EL when TF-A is built with HANDLE_EA_EL3_FIRST=1 option which enables routing of External Aborts and SErrors to EL3. Change-Id: I9d5e6775e6aad21db5b78362da6c3a3d897df977 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | | Merge "TF-A GICv3 driver: Separate GICD and GICR accessor functions" into ↵Mark Dykes2020-03-111-3/+3
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| * | | | TF-A GICv3 driver: Separate GICD and GICR accessor functionsAlexei Fedorov2020-03-101-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides separation of GICD, GICR accessor functions and adds new macros for GICv3 registers access as a preparation for GICv3.1 and GICv4 support. NOTE: Platforms need to modify to include both 'gicdv3_helpers.c' and 'gicrv3_helpers.c' instead of the single helper file previously. Change-Id: I1641bd6d217d6eb7d1228be3c4177b2d556da60a Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
* | | | | Merge changes from topic "xlat" into integrationSandrine Bailleux2020-03-113-47/+39
|\ \ \ \ \ | |_|_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | * changes: Factor xlat_table sections in linker scripts out into a header file xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPEC xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}
| * | | | Factor xlat_table sections in linker scripts out into a header fileMasahiro Yamada2020-03-111-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TF-A has so many linker scripts, at least one linker script for each BL image, and some platforms have their own ones. They duplicate quite similar code (and comments). When we add some changes to linker scripts, we end up with touching so many files. This is not nice in the maintainability perspective. When you look at Linux kernel, the common code is macrofied in include/asm-generic/vmlinux.lds.h, which is included from each arch linker script, arch/*/kernel/vmlinux.lds.S TF-A can follow this approach. Let's factor out the common code into include/common/bl_common.ld.h As a start point, this commit factors out the xlat_table section. Change-Id: Ifa369e9b48e8e12702535d721cc2a16d12397895 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | xlat_tables_v2: use ARRAY_SIZE in REGISTER_XLAT_CONTEXT_FULL_SPECMasahiro Yamada2020-03-111-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With this, it is clearer that .base_table_entries and .tables_num are the array size of .base_table and .tables, respectively. Change-Id: I634e65aba835ab9908cc3919355df6bc6e18d42a Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
| * | | | xlat_tables_v2: merge REGISTER_XLAT_CONTEXT_{FULL_SPEC,RO_BASE_TABLE}Masahiro Yamada2020-03-112-45/+15
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | xlat_tables_v2_helpers.h defines two quite similar macros, REGISTER_XLAT_CONTEXT_FULL_SPEC and REGISTER_XLAT_CONTEXT_RO_BASE_TABLE. Only the difference is the section of _ctx_name##_base_xlat_table. Parameterize it and unify these two macros. The base xlat table goes into the .bss section by default. If PLAT_RO_XLAT_TABLES is defined, it goes into the .rodata section. Change-Id: I8b02f4da98f0c272e348a200cebd89f479099c55 Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
* | | | Merge changes from topic "sb/dualroot" into integrationMark Dykes2020-03-101-1/+1
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: plat/arm: Pass cookie argument down to arm_get_rotpk_info() plat/arm: Add support for dualroot CoT plat/arm: Provide some PROTK files for development
| * | | | plat/arm: Pass cookie argument down to arm_get_rotpk_info()Sandrine Bailleux2020-02-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The cookie will be leveraged in the next commit. Change-Id: Ie8bad275d856d84c27466461cf815529dd860446 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | | | Merge changes from topic "sb/dualroot" into integrationSandrine Bailleux2020-03-101-0/+19
|\| | | | | |/ / / |/| | | | | | | | | | | | | | | | | | | * changes: Build system: Changes to drive cert_create for dualroot CoT cert_create: Define the dualroot CoT Introduce a new "dualroot" chain of trust
| * | | Introduce a new "dualroot" chain of trustSandrine Bailleux2020-02-241-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This new chain of trust defines 2 independent signing domains: 1) One for the silicon firmware (BL1, BL2, BL31) and optionally the Trusted OS. It is rooted in the Silicon ROTPK, just as in the TBBR CoT. 2) One for the Normal World Bootloader (BL33). It is rooted in a new key called Platform ROTPK, or PROTPK for short. In terms of certificates chain, - Signing domain 1) is similar to what TBBR advocates (see page 21 of the TBBR specification), except that the Non-Trusted World Public Key has been removed from the Trusted Key Certificate. - Signing domain 2) only contains the Non-Trusted World Content certificate, which provides the hash of the Non-Trusted World Bootloader. Compared to the TBBR CoT, there's no Non-Trusted World Key certificate for simplicity. Change-Id: I62f1e952522d84470acc360cf5ee63e4c4b0b4d9 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* | | | Merge "aarch32: stop speculative execution past exception returns" into ↵Mark Dykes2020-03-092-2/+15
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| * | | | aarch32: stop speculative execution past exception returnsMadhukar Pappireddy2020-03-012-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | aarch32 CPUs speculatively execute instructions following a ERET as if it was not a jump instruction. This could lead to cache-based side channel vulnerabilities. The software fix is to place barrier instructions following ERET. The counterpart patch for aarch64 is merged: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=f461fe346b728d0e88142fd7b8f2816415af18bc Change-Id: I2aa3105bee0b92238f389830b3a3b8650f33af3d Signed-off-by: Madhukar Pappireddy <madhukar.pappireddy@arm.com>
* | | | | TBB: Add an IO abstraction layer to load encrypted firmwaresSumit Garg2020-03-065-2/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TBBR spec advocates for optional encryption of firmwares (see optional requirement: R060_TBBR_FUNCTION). So add an IO abstaction layer to support firmware decryption that can be stacked above any underlying IO/ packaging layer like FIP etc. It aims to provide a framework to load any encrypted IO payload. Also, add plat_get_enc_key_info() to be implemented in a platform specific manner as handling of encryption key may vary from one platform to another. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I9892e0ddf00ebecb8981301dbfa41ea23e078b03
* | | | | drivers: crypto: Add authenticated decryption frameworkSumit Garg2020-03-063-4/+45
| |_|/ / |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add framework for autheticated decryption of data. Currently this patch optionally imports mbedtls library as a backend if build option "DECRYPTION_SUPPORT = aes_gcm" is set to perform authenticated decryption using AES-GCM algorithm. Signed-off-by: Sumit Garg <sumit.garg@linaro.org> Change-Id: I2966f0e79033151012bf4ffc66f484cd949e7271
* | | | Merge changes from topic "spmd-sel2" into integrationOlivier Deprez2020-03-065-21/+177
|\ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: SPMD: add command line parameter to run SPM at S-EL2 or S-EL1 SPMD: smc handler qualify secure origin using booleans SPMD: SPMC init, SMC handler cosmetic changes SPMD: [tegra] rename el1_sys_regs structure to sys_regs SPMD: Adds partially supported EL2 registers. SPMD: save/restore EL2 system registers.
| * | | | SPMD: add command line parameter to run SPM at S-EL2 or S-EL1Max Shvetsov2020-03-031-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added SPMD_SPM_AT_SEL2 build command line parameter. Set to 1 to run SPM at S-EL2. Set to 0 to run SPM at S-EL1 (pre-v8.4 or S-EL2 is disabled). Removed runtime EL from SPM core manifest. Change-Id: Icb4f5ea4c800f266880db1d410d63fe27a1171c0 Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
| * | | | SPMD: SPMC init, SMC handler cosmetic changesMax Shvetsov2020-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change-Id: I8881d489994aea667e3dd59932ab4123f511d6ba Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
| * | | | SPMD: Adds partially supported EL2 registers.Max Shvetsov2020-03-032-86/+134
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds EL2 registers that are supported up to ARMv8.6. ARM_ARCH_MINOR has to specified to enable save/restore routine. Note: Following registers are still not covered in save/restore. * AMEVCNTVOFF0<n>_EL2 * AMEVCNTVOFF1<n>_EL2 * ICH_AP0R<n>_EL2 * ICH_AP1R<n>_EL2 * ICH_LR<n>_EL2 Change-Id: I4813f3243e56e21cb297b31ef549a4b38d4876e1 Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
| * | | | SPMD: save/restore EL2 system registers.Max Shvetsov2020-03-023-8/+123
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTE: Not all EL-2 system registers are saved/restored. This subset includes registers recognized by ARMv8.0 Change-Id: I9993c7d78d8f5f8e72d1c6c8d6fd871283aa3ce0 Signed-off-by: Jose Marinho <jose.marinho@arm.com> Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Artsem Artsemenka <artsem.artsemenka@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
* | | | SPMD: loading Secure Partition payloadsManish Pandey2020-03-041-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements loading of Secure Partition packages using existing framework of loading other bl images. The current framework uses a statically defined array to store all the possible image types and at run time generates a link list and traverse through it to load different images. To load SPs, a new array of fixed size is introduced which will be dynamically populated based on number of SPs available in the system and it will be appended to the loadable images list. Change-Id: I8309f63595f2a71b28a73b922d20ccba9c4f6ae4 Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | | | fconf: Add Secure Partitions information as propertyOlivier Deprez2020-03-032-0/+31
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the firmware configuration framework to retrieve information about Secure Partitions to facilitate loading them into memory. To load a SP image we need UUID look-up into FIP and the load address where it needs to be loaded in memory. This patch introduces a SP populator function which gets UUID and load address from firmware config device tree and updates its C data structure. Change-Id: I17faec41803df9a76712dcc8b67cadb1c9daf8cd Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Manish Pandey <manish.pandey2@arm.com>
* | | Merge changes I75f6d135,I4add470e,I0ecd3a2b,I67a63d73 into integrationManish Pandey2020-02-283-12/+3
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | * changes: board/rddaniel: intialize tzc400 controllers plat/arm/tzc: add support to configure multiple tzc400 plat/arm: allow boards to specify second DRAM Base address plat/arm: allow boards to define PLAT_ARM_TZC_FILTERS
| * | | plat/arm/tzc: add support to configure multiple tzc400Suyash Pathak2020-02-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms that have two or more TZC400 controllers instantiated, allow the TZC400 driver to be usable with all those instances. This is achieved by allowing 'arm_tzc400_setup' function to accept the base address of the TZC400 controller. Change-Id: I4add470e6ddb58432cd066145e644112400ab924 Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
| * | | plat/arm: allow boards to specify second DRAM Base addressSuyash Pathak2020-02-191-8/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The base address for second DRAM varies across different platforms. So allow platforms to define second DRAM by moving Juno/SGM-775 specific definition of second DRAM base address to Juno/SGM-775 board definition respectively, SGI/RD specific definition of DRAM 2 base address to SGI board definition. Change-Id: I0ecd3a2bd600b6c7019c7f06f8c452952bd07cae Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
| * | | plat/arm: allow boards to define PLAT_ARM_TZC_FILTERSSuyash Pathak2020-02-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A TZC400 can have upto 4 filters and the number of filters instantiated within a TZC400 is platform dependent. So allow platforms to define the value of PLAT_ARM_TZC_FILTERS by moving the existing Juno specific definition of PLAT_ARM_TZC_FILTERS to Juno board definitions. Change-Id: I67a63d7336595bbfdce3163f9a9473e15e266f40 Signed-off-by: Suyash Pathak <suyash.pathak@arm.com>
* | | | Merge "fconf: Fix misra issues" into integrationSandrine Bailleux2020-02-282-6/+6
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