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* Merge pull request #1653 from JackyBai/masterAntonio Niño Díaz2018-12-051-0/+159
|\ | | | | Add NXP i.MX8MQ basic support
| * drivers: add tzc380 supportPeng Fan2018-12-041-0/+159
| | | | | | | | | | | | | | Add tzc380 support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Bai Ping <ping.bai@nxp.com>
* | Merge pull request #1702 from MISL-EBU-System-SW/patches-18.12Antonio Niño Díaz2018-12-041-0/+14
|\ \ | | | | | | Update code with latest changes from Marvell LSP 18.12
| * | ble: ap807: Switch to PLL mode and update CPU frequencyChristine Gharzuzi2018-12-041-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | - Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | | Merge pull request #1699 from chandnich/sgi-mt-supportSoby Mathew2018-12-032-3/+1
|\ \ \ | |_|/ |/| | Add support to implement multi-threaded platforms for SGI
| * | plat/arm/common: add an additional platform power levelChandni Cherukuri2018-11-271-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For platforms using multi-threaded CPUs, there can be upto four platform power domain levels. At present, there are three platform power domain levels that are defined for the CSS platforms. Define a fourth level 'ARM_PWR_LVL3' as well to provide support for an additional platform power domain level. Change-Id: I40cc17a10f4690a560776f504364fd7277a7e72a Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
| * | plat/css: allow platforms to define the system power domain levelChandni Cherukuri2018-11-271-3/+0
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CSS_SYSTEM_PWR_DMN_LVL macro that defines the system power domain level is fixed at ARM_PWR_LVL2 for all CSS platforms. However, the system power domain level can be different for CSS platforms that use multi-threaded CPUs. So, in preparation towards adding support for platforms that use multi-threaded CPUs, refactor the definition of CSS_SYSTEM_PWR_DMN_LVL such that CSS_SYSTEM_PWR_DMN_LVL is uniquely defined for each of the CSS platform. Change-Id: Ia837b13f6865e71da01780993c048b45b7f36d85 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | Merge pull request #1688 from JoelHutton/jh/variant_1_mitigationsAntonio Niño Díaz2018-11-291-0/+7
|\ \ | | | | | | Initial Spectre V1 mitigations (CVE-2017-5753).
| * | Initial Spectre V1 mitigations (CVE-2017-5753).Joel Hutton2018-11-261-0/+7
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Initial Spectre Variant 1 mitigations (CVE-2017-5753). A potential speculative data leak was found in PSCI code, this depends on a non-robust implementation of the `plat_get_core_pos_by_mpidr()` function. This is considered very low-risk. This patch adds a macro to mitigate this. Note not all code paths could be analyzed with current tools. Add a macro which makes a variable 'speculation safe', using the __builtin_speculation_safe_value function of GCC and llvm. This will be available in GCC 9, and is planned for llvm, but is not currently in mainline GCC or llvm. In order to implement this mitigation the compiler must support this builtin. Support is indicated by the __HAVE_SPECULATION_SAFE_VALUE flag. The -mtrack-speculation option maintains a 'tracker' register, which determines if the processor is in false speculation at any point. This adds instructions and increases code size, but avoids the performance impact of a hard barrier. Without the -mtrack-speculation option, __builtin_speculation_safe_value expands to a ISB DSB SY sequence after a conditional branch, before the speculation safe variable is used. With -mtrack-speculation a CSEL tracker, tracker, XZR, [cond]; AND safeval,tracker; CSDB sequence is added instead, clearing the vulnerable variable by AND'ing it with the tracker register, which is zero during speculative execution. [cond] are the status flags which will only be true during speculative execution. For more information on __builtin_speculation_safe_value and the -mtrack-speculation option see https://developer.arm.com/support/arm-security-updates/speculative-processor-vulnerability/compiler-support-for-mitigations The -mtracking option was not added, as the performance impact of the mitigation is low, and there is only one occurence. Change-Id: Ic9e66d1f4a5155e42e3e4055594974c230bfba3c Signed-off-by: Joel Hutton <Joel.Hutton@Arm.com>
* | Merge pull request #1679 from pangupta/masterAntonio Niño Díaz2018-11-291-0/+17
|\ \ | |/ |/| ccn: Introduce API to set and read value of node register
| * ccn: Introduce API to set and read value of node registerPankaj Gupta2018-11-231-0/+17
| | | | | | | | Signed-off-by: Pankaj Gupta <pankaj.gupta@nxp.com>
* | Merge pull request #1697 from antonio-nino-diaz-arm/an/archAntonio Niño Díaz2018-11-265-83/+193
|\ \ | | | | | | Synchronise arch.h and arch_helpers.h with TF-A-Tests
| * | Synchronise arch.h and arch_helpers.h with TF-A-TestsAntonio Nino Diaz2018-11-265-58/+191
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The headers forked at some point in the past and have diverged a lot. In order to make it easier to share code between TF-A-Tests and TF-A, this patch synchronises most of the definitions in the mentioned headers. This is not a complete sync, it has to be followed by more cleanup. This patch also removes the read helpers for the AArch32 instructions ats1cpr and ats1hr (they are write-only). Change-Id: Id13ecd7aeb83bd2318cd47156d71a42f1c9f6ba2 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
| * | Revert "aarch32: Apply workaround for errata 813419 of Cortex-A57"Antonio Nino Diaz2018-11-221-25/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 6f512a3dfd61662dbdae4912fb6a320ae4d754d5. According to the 'Cortex-A57 MPCore Software Developers Errata Notice': This bug will only affect secure AArch64 EL3. If the above conditions occur, the CPU will not invalidate the targeted EL3 TLB entries and incorrect translations might occur. For this reason it is not needed in AArch32. Change-Id: I6f7b333817515499723e8f306145790ad6af9975 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | Merge pull request #1691 from vijayenthiran-arm/sgi-dmc620-tzcAntonio Niño Díaz2018-11-231-0/+104
|\ \ \ | |/ / |/| | Add support for dmc620 tzc driver
| * | drivers/tzc-dmc620: add driver to setup DMC-620 TZC controllerVijayenthiran Subramaniam2018-11-211-0/+104
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ARM CoreLink DMC-620 Dynamic Memory Controller includes a TZC controller to setup secure or non-secure regions of DRAM memory. The TZC controller allows to setup upto eight such regions of memory in DRAM. This driver provides helper functions to setup the TZC controller within DMC-620. Change-Id: Iee7692417c2080052bdb7b1c2873a024bc5d1d10 Signed-off-by: Vijayenthiran Subramaniam <vijayenthiran.subramaniam@arm.com>
* | | xlat v2: Support mapping regions with allocated VAAntonio Nino Diaz2018-11-221-0/+36
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide new APIs to add new regions without specifying the base VA. - `mmap_add_region_alloc_va` adds a static region to mmap choosing as base VA the first possible address after all the currently mapped regions. It is aligned to an appropriate boundary in relation to the size and base PA of the requested region. No attempt is made to fill any unused VA holes. - `mmap_add_dynamic_region_alloc_va` it adds a region the same way as `mmap_add_region_alloc_va` does, but it's dynamic instead of static. - `mmap_add_alloc_va` takes an array of non const `mmap_region_t`, maps them in the same way as `mmap_add_region_alloc_va` and fills their `base_va` field. A helper macro has been created to help create the array, called `MAP_REGION_ALLOC_VA`. Change-Id: I5ef3f82ca0dfd0013d2e8034aa22f13ca528ba37 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1682 from MISL-EBU-System-SW/migrate-multi-consoleAntonio Niño Díaz2018-11-193-0/+91
|\ \ | | | | | | Marvell: Migrate to multi console API
| * | plat/marvell: Migrate to multi-console APIKonstantin Porotchkin2018-11-153-0/+91
| | | | | | | | | | | | | | | | | | | | | | | | Migrate Marvell platforms from legacy console API to multi-console API. Change-Id: I647f5f49148b463a257a747af05b5f0c967f267c Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | | drivers: st: update console driver to support MULTI_CONSOLE_APIYann Gautier2018-11-151-0/+34
| | | | | | | | | | | | Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | stm32mp1: add a new file for UART registers definitionYann Gautier2018-11-151-0/+199
| | | | | | | | | | | | Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | | utils_def: add an assembly version for GENMASKYann Gautier2018-11-151-0/+8
|/ / | | | | | | | | | | | | | | When compiling assembly files, stdint.h is not included. UINT32_C and UINT64_C are then not defined. A new GENMASK macro for assembly is then created. Signed-off-by: Yann Gautier <yann.gautier@st.com>
* | Merge pull request #1676 from Yann-lms/static_analysisAntonio Nino Diaz2018-11-133-7/+6
|\ \ | | | | | | | | | Correct some issues found with static analysis tools
| * | stm32mp1: remove duplicate function declarationYann Gautier2018-11-091-2/+0
| | | | | | | | | | | | | | | | | | It is already in include/drivers/st/stm32mp1_ddr_helpers.h. Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | stm32mp1: correct some static analysis tools issuesYann Gautier2018-11-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These issues wer found by sparse: drivers/st/clk/stm32mp1_clk.c:1524:19: warning: incorrect type in assignment (different base types) expected restricted fdt32_t const [usertype] *pkcs_cell got unsigned int const [usertype] * plat/st/stm32mp1/plat_image_load.c:13:6: warning: symbol 'plat_flush_next_bl_params' was not declared. Should it be static? plat/st/stm32mp1/plat_image_load.c:21:16: warning: symbol 'plat_get_bl_image_load_info' was not declared. Should it be static? plat/st/stm32mp1/plat_image_load.c:29:13: warning: symbol 'plat_get_next_bl_params' was not declared. Should it be static? plat/st/stm32mp1/bl2_io_storage.c:40:10: warning: symbol 'block_buffer' was not declared. Should it be static? Signed-off-by: Yann Gautier <yann.gautier@st.com>
| * | psci: put __dead2 attribute after void in plat_psci_opsYann Gautier2018-11-091-4/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | These warnings were issued by sparse: plat/st/stm32mp1/stm32mp1_pm.c:365:36: warning: incorrect type in initializer (different modifiers) expected void ( *[noreturn] pwr_domain_pwr_down_wfi )( ... ) got void ( [noreturn] *<noident> )( ... ) plat/st/stm32mp1/stm32mp1_pm.c:366:23: warning: incorrect type in initializer (different modifiers) expected void ( *[noreturn] system_off )( ... ) got void ( [noreturn] *<noident> )( ... ) plat/st/stm32mp1/stm32mp1_pm.c:367:25: warning: incorrect type in initializer (different modifiers) expected void ( *[noreturn] system_reset )( ... ) got void ( [noreturn] *<noident> )( ... ) This cannot be changed the other way in all platforms pm drivers or else there is a compilation error: plat/st/stm32mp1/stm32mp1_pm.c:234:1: error: attributes should be specified before the declarator in a function definition Signed-off-by: Yann Gautier <yann.gautier@st.com>
* / cadence: uart: comply to console_register prototypeAlexei Colin2018-11-121-1/+1
|/ | | | Signed-off-by: Alexei Colin <acolin@isi.edu>
* Standardise header guards across codebaseAntonio Nino Diaz2018-11-08188-543/+586
| | | | | | | | | | | | | | | | | | All identifiers, regardless of use, that start with two underscores are reserved. This means they can't be used in header guards. The style that this project is now to use the full name of the file in capital letters followed by 'H'. For example, for a file called "uart_example.h", the header guard is UART_EXAMPLE_H. The exceptions are files that are imported from other projects: - CryptoCell driver - dt-bindings folders - zlib headers Change-Id: I50561bf6c88b491ec440d0c8385c74650f3c106e Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Arm platforms: Fix DRAM address macrosSandrine Bailleux2018-11-071-2/+2
| | | | | | | | | | | | | | | On AArch32, ARM_DRAM1_BASE and ARM_DRAM1_SIZE constants are currently 32-bit values (because they are suffixed with UL and the value 0x80000000 fits in a unsigned long int, i.e. a 32-bit value). When summing them up, the result overflows the maximum value that can be encoded in a 32-bit value so it wraps around and does not result in the expected value. This patch changes the suffix of these constants into ULL so that they always are 64-bit values. Change-Id: I3b19b1805e35cc7e43050458df379081b1e882d5 Signed-off-by: Sandrine Bailleux <sandrine.bailleux@arm.com>
* Introduce fdtw_read_array() helperAntonio Nino Diaz2018-11-021-0/+2
| | | | | | | | fdtw_read_cells() can only read one or two cells, sometimes it may be needed to read more cells from one property. Change-Id: Ie70dc76d1540cd6a04787cde7cccb4d1bafc7282 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Introduce new fdt helper to read string propertiesAntonio Nino Diaz2018-11-021-0/+3
| | | | | | | Introduced fdtw_read_string() to read string properties. Change-Id: I854eef0390632cf2eaddd2dce60cdb98c117de43 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* libc: Adapt strlcpy to this codebaseAntonio Nino Diaz2018-11-021-0/+1
| | | | | Change-Id: I2f5f64aaf90caae936510e1179392a8835f493e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* bakery: Fix MISRA defectsAntonio Nino Diaz2018-11-012-14/+32
| | | | | Change-Id: I600bc13522ae977db355b6dc5a1695bce39ec130 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm: Fix MISRA defects in dyn configAntonio Nino Diaz2018-11-011-3/+3
| | | | | Change-Id: Iae6758ca6395560131d1e1a69a1ecfe50ca8bf83 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* plat/arm: Fix types of constants in headersAntonio Nino Diaz2018-11-013-31/+31
| | | | | Change-Id: I33eaee8e7c983b3042635a448cb8d689ea4e3a12 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* context_mgmt: Fix MISRA defectsAntonio Nino Diaz2018-11-017-37/+49
| | | | | | | | The macro EL_IMPLEMENTED() has been deprecated in favour of the new function el_implemented(). Change-Id: Ic9b1b81480b5e019b50a050e8c1a199991bf0ca9 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* Merge pull request #1657 from antonio-nino-diaz-arm/an/libfdtAntonio Niño Díaz2018-11-012-68/+9
|\ | | | | libfdt: Downgrade to version 1.4.6-9
| * libfdt: Downgrade to version 1.4.6-9Antonio Nino Diaz2018-10-302-68/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Version 1.4.7 introduces a big performance hit to functions that access the FDT. Downgrade the library to version 1.4.6-9, before the changes that introduce the problem. Version 1.4.6 isn't used because one of the libfdt files (fdt_overlay.c) is missing the license header. This problem is also fixed in 1.4.6-9. This version corresponds to commit <aadd0b65c987> checks: centralize printing of property names in failure messages. Fixes ARM-software/tf-issues#643 Change-Id: I73c05f2b1f994bcdcc4366131ce0647553cdcfb8 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | Merge pull request #1623 from MISL-EBU-System-SW/a3700-supportAntonio Niño Díaz2018-11-018-5/+379
|\ \ | | | | | | Add support for Armada 3700 and COMPHY porting layer
| * | plat: marvell: Add support for Armada-37xx SoC platformKonstantin Porotchkin2018-10-316-3/+370
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add supprot for Marvell platforms based on Armada-37xx SoC. This includes support for the official Armada-3720 modular development board and EspressoBin community board. The Armada-37xx SoC contains dual Cortex-A53 Application CPU, single secure CPU (Cortex-M3) and the following interfaces: - SATA 3.0 - USB 3.0 and USB 2.0 - PCIe - SDIO (supports boot from eMMC) - SPI - UART - I2c - Gigabit Ethernet Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | plat: marvell: Fix the wrong include protectorKonstantin Porotchkin2018-10-181-2/+2
| | | | | | | | | | | | | | | | | | Fix the include protector to be in sync with file name Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
| * | lib/mmio: Add mmio_clrsetbits_16 inline functionKonstantin Porotchkin2018-10-181-0/+7
| | | | | | | | | | | | | | | | | | | | | Add 16-bit variant of mmio_clrsetbits function Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
* | | Merge pull request #1650 from chandnich/sgiclark-ares-supportAntonio Niño Díaz2018-10-311-0/+7
|\ \ \ | | | | | | | | Sgiclark ares support
| * | | plat/arm/css: Add SID registers for SGx platformsChandni Cherukuri2018-10-261-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some of the SGx platforms use System Identification (SID) registers for platform identification. Add support for these registers in css. Change-Id: If00b18744a31ff2cf14338f18c8c680eb69c9027 Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com>
* | | | Merge pull request #1646 from Andre-ARM/allwinner/pmic-v2Antonio Niño Díaz2018-10-311-0/+20
|\ \ \ \ | | | | | | | | | | Allwinner/pmic v2
| * | | | allwinner: Add RSB driverAndre Przywara2018-10-201-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "Reduced Serial Bus" is an Allwinner specific bus, bearing many similarities with I2C. It sports a much higher bus frequency, though, (typically 3 MHz) and requires much less handholding for the typical task of manipulating slave registers (fire-and-forget). On most A64 boards this bus is used to connect the PMIC to the SoC. This driver provides basic primitives to read and write slave registers, it will be later used by the PMIC code. Signed-off-by: Andre Przywara <andre.przywara@arm.com>
* | | | | Fix MISRA defects in PMFAntonio Nino Diaz2018-10-292-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Change-Id: I64abd72026082218a40b1a4b8f7dc26ff2478ba6 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | | Fix MISRA defects in workaround and errata frameworkAntonio Nino Diaz2018-10-296-23/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Change-Id: Iaab0310848be587b635ce5339726e92a50f534e0 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | | plat/arm: Fix MISRA defects in SiP SVC handlerAntonio Nino Diaz2018-10-292-14/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional changes. Change-Id: I9b9f8d3dfde08d57706ad5450de6ff858a55ac01 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
* | | | | Fix MISRA defects in extension libsAntonio Nino Diaz2018-10-296-30/+36
| |_|_|/ |/| | | | | | | | | | | | | | | | | | | | | | | No functional changes. Change-Id: I2f28f20944f552447ac4e9e755493cd7c0ea1192 Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com>
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